JPH0667249B2 - Motor control device for electronic camera - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor control device for an electronic camera that records an instantaneous image of a copy on a magnetic medium such as a video floppy.

2. Description of the Related Art A conventional motor control device for an electronic camera is disclosed in, for example, Japanese Patent Application Laid-Open No. 59-163106.

In this conventional motor control device for an electronic camera, a high control accuracy is required to record a video signal, and since the signal must be always recorded from a specific position of the magnetic disk, the rotation phase of the magnetic disk and the image are recorded. Since it is necessary to always hold the phase of the signal synchronization signal in a constant relationship, a phase control loop is provided in addition to the speed control loop as a motor rotation control loop. Since the phase control in this device requires that the response frequency to the disturbance be as high as possible, rather than using the so-called PG signal that generates one pulse signal per revolution of the magnetic disk to give the rotational phase information of the magnetic disk, Compare the phase of the so-called FG signal, which is proportional to the rotation speed of the motor used for speed control with a high comparison frequency, with the phase of the reference clock signal that has the same frequency as the FG signal, and keep the phase relationship between them constant. There is. Furthermore, since the relationship between the rotation phase of the magnetic disk and the phase of the synchronizing signal is not uniquely determined as it is, in this device, the phase control loop is locked, so that the predetermined phase relationship is obtained by using the PG signal described above. This phase relationship is defined by resetting the sync signal at least once. The conventional motor control device for this electronic camera will be described in more detail below with reference to the drawings, but the resetting of the synchronization signal by the PG signal is not directly related to this requirement, and is therefore omitted.

FIG. 3 is a block diagram of a motor control device for this conventional electronic camera. 101 is a motor for driving a magnetic disk, 102 is a plurality of pulses for each rotation of the motor, and the rotational speed is detected. Frequency generator (hereinafter referred to as FG) for 103, 103 is a speed comparison circuit that compares the rotation speed of the motor with a reference signal based on the FG signal and outputs the result, 104 is a speed comparison circuit Based on the output of 103, the speed lock detection circuit that detects the lock of the speed control loop depending on whether the rotation speed of the motor is within a predetermined range and outputs a speed lock signal when the speed is within that range, 105 is switched by the output of speed lock detection circuit 104
An integral filter that turns ON / OFF 111 to turn ON / OFF the integral operation, and that keeps the steady-state deviation of the control loop constant even if the load applied to the motor 101 changes, because 106 drives the motor 101 Motor drive circuit 107, a reference clock signal generation circuit 107 that generates a clock in synchronization with the FG signal after giving a reference phase of the FG signal and obtaining the speed lock signal from the speed lock detection circuit 104, and 108 is a phase of the FG signal And a phase of a reference clock signal and outputs the result. Here, the FG 102, the speed comparison circuit 103, the integration filter 105, and the motor drive circuit 106 form a speed control loop, and the FG 102, the phase comparison circuit 108, and the preceding speed control loop form a phase control loop. Fourth
The figure is an operation waveform diagram at the time of starting the motor in this device. (A) ′ is a motor ON / OFF signal 110 which is inputted to the motor drive circuit 106 and controls start / stop of the motor.
(B) ′ is output from FG102 and is input to speed comparison circuit 103, phase comparison circuit 108, and reference clock signal generation circuit 107.
The G signal, (c) 'is output from the speed lock detection circuit 104.
A speed lock signal for controlling the SW111 and the reference clock signal generation circuit 107, (e) 'is a reference clock signal output from the reference clock signal generation circuit 107 and input to the phase comparison circuit 108, and (f)' is a speed comparison circuit 103. Is the speed comparison output voltage output from the integration filter 105 and the speed lock detection circuit 104, and (g) 'is the phase comparison output voltage output from the phase comparison circuit 108 and applied to the speed control loop via a resistor.

In the motor control device for the conventional electronic camera configured as described above, the motor ON / OFF signal 110 of the motor 101 is L
When the level changes from H level to H level, the motor drive circuit 106 becomes O
Then, the motor 101 starts to rotate, and an FG signal (b) 'having a frequency proportional to the rotation speed is output from the FG 102 and input to the speed comparison circuit 103. The speed comparison circuit 103 converts the voltage into a voltage according to the frequency of the FG signal (b) ', and outputs a voltage according to the difference from the reference voltage as a speed comparison output voltage (f)'. The value of the speed comparison output voltage (f) 'is high when the frequency of the FG signal (b)' is low, that is, when the rotation speed of the motor 101 is slow, and the value of the FG signal (b) 'is high, that is, the rotation of the motor 101. The higher the speed, the lower the speed. Also motor 101
It is configured such that a constant high voltage is output until the rotation speed of is higher than a certain value. Therefore, FIG. 4 (b)
Immediately after starting the motor 101, a constant high voltage is output until the rotation speed reaches a certain value or more, and then the value decreases as the rotation speed increases, as shown in FIG.
When the motor 101 reaches a predetermined rotation speed, it hangs near the center voltage of the control loop. At this time, the speed lock detection circuit 10
4 constantly monitors the speed comparison output voltage (f) 'which is the output of the speed comparison circuit 103, and its value is Va as shown in FIG.
And within the range of Vb, that is, when the rotation speed of the motor 101 falls within a predetermined range, the output level is changed from H to L and a speed lock signal (c) 'is output. The integration filter 105 keeps both ends of the capacitor at the same potential with the SW111 kept ON until the speed lock signal (C) ′ is input, and is almost in a steady state (the state where the motor 101 is rotating at a predetermined rotation speed). Set to the same state, and its operation works just as an amplifier. When the rotation speed of the motor 101 exceeds a predetermined value and the speed lock signal (c) 'is output as described above, the SW111 turns off.
It becomes FF and operates as an integral filter. It is well known that both ends of the capacitor of the integration filter 105 are short-circuited with SW111 in advance and kept at the same potential until the rotation speed reaches a certain value, that is, until the speed comparison voltage (C) ′ falls within a predetermined range. This is because the transient response time of the integration filter 105 is shortened and the time from the startup of the motor 101 until it stabilizes at a constant speed and constant phase (hereinafter simply referred to as the startup time) is shortened.

The reference clock signal generation circuit 107 is in a reset state as shown in FIG. 4 (a) until the speed lock signal (c) 'is input, and when the speed lock signal (c)' is input, FG The reference clock signal (e) 'is generated at a timing synchronized with the rising edge of the signal (b)' and shifted in phase by θ, which is the phase relationship in the steady state. Further, the phase comparison circuit 108 has its output fixed to the central voltage until the reference clock signal (e) 'is inputted, and starts the original phase comparison operation when the reference clock signal (e)' is inputted.

As described above, the reason why the phase comparison circuit 108 is not operated until the speed lock signal (c) ′ is output is that the speed is controlled by performing wasteful phase control until the rotation speed of the motor reaches a predetermined range. This is to avoid meaningless disturbance to the control loop and conversely to lengthen the start-up time so that the phase can be quickly pulled in after the speed is locked.

Problems to be Solved by the Invention However, in the above configuration, when the motor is started,
Since the SW111 of the integration filter 105 is turned off to start the integration operation and the reference clock signal (e) 'is generated at the same timing by using the speed lock signal (c)', the following problem occurs. Had.

The speed lock detection in the speed lock detection circuit 104 detects that the rotation speed of the motor is within a certain range, but this setting range cannot be narrowed too much. Because, if this range is narrow, it is equivalent to the state where there is no integral filter 105 in the speed control loop at startup, so the speed control loop has a large deviation (steady deviation) from the target value depending on the load state applied to the motor 101. In other words, since the speed comparison output voltage (F) 'does not enter between Va and Vb and becomes stable, the integration filter 10
In addition to the fact that 5 does not operate as an integration filter, a state occurs in which the reference clock signal (e) 'is not generated and the phase control cannot be performed. For this reason, this setting range needs to be wide with some width. When the setting range is widened so that the above problem does not occur, the rotation speed of the motor 101 does not reach the target value even if the speed lock signal (c) ′ is output, and the integral filter is set in such a state. Even if only the speed control loop is used, it takes the transient response time after the SW111 is turned off until the potential state across both ends of the capacitor of 105 is released until it becomes a steady state. In this conventional device, the phase control loop also operates in such a state, and therefore, as shown in FIG. 4 (a), the reference clock signal is generated in synchronization with the FG signal so as to have the phase relationship in the steady state. However, the phase control loop cannot be immediately pulled in because the speed control loop is not yet stable, and in the end, when the speed control loop and the phase control loop interact with each other and the speed control loop exists independently. It takes longer to stabilize, and as a result, it takes longer to stabilize the phase control loop. This state is shown in FIG. 4B, and T ₂ ′ shows the time from the motor ON command 110 until the phase control loop is pulled in.

In the conventional method of shortening the start-up time like this, it is not possible to pull in the phase control loop in a time almost equal to the pull-in time of the speed control loop alone, and this point is required to quickly respond to the shutter chance. This has been a serious problem for motor control devices for electronic cameras.

Means for Solving the Problems The present invention provides a means for generating a signal proportional to the rotation speed of a motor and an integration filter for controlling the rotation speed of the motor based on this signal and integrating an error voltage in a control loop. And a phase control means for controlling the phase of the reference clock signal and the phase of the signal proportional to the rotation speed of the motor in a predetermined phase relationship, and that the rotation speed of the motor becomes approximately a predetermined value. A speed lock detection means for detecting the speed change, an integration operation control means for controlling ON / OFF of the integration operation of the integration filter by the speed lock detection signal, and an integration operation of the integration filter turned on by the speed lock detection signal. And a reference clock signal generating means for generating the reference clock signal in synchronism with a signal proportional to the rotation speed of the motor after being delayed by a predetermined time. A motor control device of the electronic camera according to symptoms.

Operation According to the present invention, with the above-described structure, when the motor is started, after the integration operation of the integration filter is turned ON by the speed lock signal, a predetermined time, that is, a time until the speed control loop is stabilized is delayed, and then the reference clock signal is set. Generate and activate the phase control loop.

Embodiment FIG. 1 is a block diagram of a motor control device for an electronic camera according to an embodiment of the present invention, in which 1 is a motor, 2 is FG, 3 is a speed comparison circuit, 4 is a speed lock detection circuit, 5 is an integration filter, Reference numeral 6 is a motor drive circuit, and 8 is a phase comparison circuit. Since these operations are the same as those of the above-described conventional device, detailed description thereof will be omitted.

Reference numeral 9 is a delay circuit for outputting a speed lock delay signal obtained by delaying the speed lock signal by a predetermined time. Reference numeral 7 is a reference phase of the FG signal and after obtaining the speed lock delay signal, a clock is generated in synchronization with the FG signal. It is a reference clock signal generation circuit.

FIG. 2 is an operation waveform diagram at the time of starting the motor in the device of the present invention. (D) shows a speed lock signal (c) delayed by T ₀ by the delay circuit 9 and inputted to the reference clock signal generation circuit. It is a delayed signal.

The operation of the motor control device for the electronic camera of the present embodiment having the above configuration will be described below.

When the motor ON / OFF signal 10 changes from L level to H level, the motor 1 starts to rotate, the rotation speed increases, the speed comparison output voltage (f) enters the range of Va and Vb, and the speed lock signal (c) locks the speed. When output from the detection circuit, SW11
When turned off, the integration filter 5 starts the integration operation. The reference clock signal generation circuit 7 considers the time T ₀ until the speed lock signal (C) becomes stable in the speed control loop by the delay circuit 9 (the time until the potential difference between both ends of the capacitor of the integral filter 5 becomes a steady state). When the speed lock delay signal (d) delayed by only 1) is input, the reset state is released, and as shown in FIG. 2, the phase relationship is in a steady state in synchronization with the rising of the FG signal (b). A timing reference clock signal (e) whose phase is shifted by θ is generated. That is, after the speed lock signal (C) is output, T ₁ (T ₁ = T ₀ +
After θ), the reference clock signal (e) is generated (FIG. 2 (a)). Therefore, the phase control loop operates after T ₁ after the speed lock signal (C) is output.

As described above, according to the present embodiment, the phase control loop is not operated until the speed control loop reaches the steady state, so that the speed control loop is almost the transient response time of the integral filter 5 after SW11 is turned off. It becomes stable, and after that, the reference clock signal is generated to operate the phase control loop so as to have a phase relation of a steady state from the time of generation, so that as shown in FIG. (F) and (g) are stable immediately without large fluctuations, that is, both control loops can be immediately pulled in. Where T ₂
Indicates the time from the motor ON command to the phase pull-in, and indicates that the phase is pulling in immediately after pulling in the speed loop.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to pull in the phase control loop at a time substantially equal to the pulling time of the speed control loop at the time of starting the motor, and to quickly respond to a shutter chance. Can be satisfied, and the power consumption required for starting the motor can be saved as compared with the conventional one, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a motor control device for an electronic camera according to an embodiment of the present invention, FIG. 2 is an operation waveform diagram at the time of starting the motor of the embodiment, and FIG. 3 is a motor control device for a conventional electronic camera. A block diagram and FIG. 4 are operation waveform diagrams at the time of starting the motor. 1 ... motor, 2 ... frequency generator, 3 ... speed comparison circuit, 4 ... speed lock detection circuit, 5 ... integration filter,
6 ... Motor drive circuit, 7 ... Phase comparison circuit, 8 ... Reference clock signal generation circuit, 9 ... Delay circuit.

Claims (2)

[Claims] 1. A means for generating a signal proportional to a rotation speed of a motor, and a speed control means having an integration filter for controlling a rotation speed of the motor based on the signal and integrating an error voltage in a control loop. Phase control means for controlling the phase of the reference clock signal and the phase of the signal proportional to the rotation speed of the motor in a predetermined phase relationship, and speed lock detection means for detecting that the rotation speed of the motor has reached a substantially predetermined value. And an integral operation control means for controlling ON / OFF of the integral operation of the integral filter by the speed lock detection signal, and an integral operation of the integral filter by the speed lock detection signal.
And a reference clock signal generating means for generating the reference clock signal in synchronism with a signal proportional to the rotation speed of the motor after a predetermined time delay. 2. The integration operation of the integration filter is turned on for a predetermined time.
The motor control device for an electronic camera according to claim 1, wherein the control loop of the speed control means is set to be equal to or longer than a time until the control loop is stabilized.