JPH043020B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention compares a servo comparison pulse output based on the rotation of a magnetic disk with a reference signal, and calculates the phase difference of the comparison pulse with respect to the reference signal. It relates to a magnetic disk device in which a phase lock detection circuit is provided in a servo control circuit that servo-controls the rotational phase of the magnetic disk so that the rotational phase of the magnetic disk is maintained within an allowable range. This invention relates to an improvement of the phase lock detection circuit of the device.

(Prior art) Conventionally, in magnetic disk devices, a comparison pulse for servo output based on the rotation of a magnetic disk is compared with a reference signal, and the phase difference of the comparison pulse with respect to this vertical synchronization signal is within an allowable range. A servo control circuit is provided to servo control the rotational phase of the magnetic disk so that the rotational phase of the magnetic disk is maintained.

For example, in electronic still cameras, a so-called PG yoke is installed in the center core of a magnetic disk called a still video floppy.
A so-called PG coil is provided facing the rotation range of the PG yoke, and the PG yoke and PG coil constitute a phase detector, and the PG pulse generated when the PG yoke passes through the PG coil is detected by A comparison pulse for the servo is output based on the rotation of the servo, and a vertical synchronization signal generated by a synchronization signal generation circuit is used as a reference signal to detect the phase difference of the comparison pulse with respect to the vertical synchronization signal. The speed of the spindle motor for rotating the magnetic disk is controlled by the FG signal from the frequency generator FG, and the rotational phase of the magnetic disk is servo-controlled.

(Problem to be Solved by the Invention) By the way, in order to properly record video, etc., the comparison pulse must be synchronized with the vertical synchronization signal, that is, the phase of the comparison pulse must match the vertical synchronization signal. Unlike video recording systems, electronic still cameras record images instantaneously.
When photographing, it is strictly required that the phase of the comparison signal be locked to the phase of the vertical synchronization signal.

In particular, in electronic still cameras, when the spindle motor is started up, its rotation is unstable, and the phase difference of the comparison pulse with respect to the vertical synchronization signal fluctuates.If the phase of the comparison pulse is unstable, it may be difficult to record images. There is a problem in which accurate video recording cannot be performed.

Conventionally, when the spindle motor is started, the electronic still camera's release button is operated in anticipation of the time from the start until the phase of the comparison pulse is locked to the phase of the vertical synchronization signal. Measures such as prohibiting photographing and recording even when the vertical synchronization signal and comparison pulse are used will reduce the fluctuation of the phase error signal, which changes based on the phase difference between the vertical synchronization signal and the comparison pulse, and the phase error signal will approach a constant value when the phase is locked. Therefore, efforts have been made to utilize this approach to a constant value to construct a phase lock detection circuit.

When the spindle motor is started, the time from the start until the phase of the comparison pulse is locked to the phase of the vertical synchronization signal is taken into account, and during that time, even if the release button of the electronic still camera is operated, shooting will not be recorded. The advantage of taking measures to prohibit this is that it is possible to record images without the need for a phase lock detection circuit, but the time it takes for the phase to be locked varies slightly each time the image is taken. is not constant,
Therefore, when using this method, in order to record images accurately, it is necessary to set the video recording prohibition time assuming the longest time until the phase is locked. , when shooting,
This has the disadvantage that it often causes unnecessary waiting time.

Also, with this conventional method, for some reason,
For example, if an electronic still camera that you are holding hits something and receives a shock, the rotation of its spindle motor may be disrupted, resulting in a temporary loss of phase lock even after phase lock has been achieved. However, with the means of setting the video recording prohibition time, there may be cases where this cannot be detected and normal video recording cannot be performed because there is no phase lock detection circuit.

On the other hand, since the phase error signal, which changes according to the phase difference between the vertical synchronization signal and the comparison pulse, approaches a constant value when the phase is locked, a phase lock detection circuit is configured by utilizing this approach to a constant value. This method has the advantage that there is no need for unnecessary waiting time during photographing, and that temporary loss of phase lock can be detected after phase lock has been achieved.

By the way, the phase error signal, which changes based on the phase difference between the vertical synchronization signal and the comparison pulse, approaches a constant value when the phase is locked. Set a tolerance range (usually within 2 to 5%) from the final phase error signal value when locked, and use a comparator etc. to check whether the phase error signal value falls within that tolerance range. The final value of the phase error signal depends on variations in the characteristics of electronic components such as resistors and capacitors that make up the servo circuit, and the resistance of the volume to adjust the variations. Each electronic still camera differs slightly due to variations in values, etc., and the phase lock detection circuit is provided with adjustment means to adjust its tolerance range in response to variations in the final value of the phase error signal. The disadvantage is that the adjustment is troublesome.

In addition, even if the tolerance range is adjusted to be appropriate, the final value of the actual phase error signal may deviate from the value at the time of adjustment due to fluctuations in the power supply voltage or environmental temperature. As a result, it may be determined that the phase lock is within the permissible range even though it is actually not within the permissible range, and the phase lock may not be detected accurately.

Furthermore, since this device only detects when the phase error signal falls within the permissible range, it may fall outside the permissible range of 7H ± 2H as the phase difference standard for electronic still cameras due to changes in electronic components over time, etc. Even if the phase is locked, there is a problem that this cannot be detected. Note that here, the symbol H means one horizontal synchronization period of the video recording signal.

(Object of the Invention) The present invention has been made in consideration of the above circumstances, and its purpose is to detect accurate phase lock by directly detecting the phase difference of a comparison pulse with respect to a reference signal. An object of the present invention is to provide a magnetic disk device equipped with a phase lock detection circuit capable of performing the following steps.

(Means for Solving the Problems) A feature of the magnetic disk device according to the present invention is that its phase lock detection circuit defines an allowable range of phase difference between a comparison pulse generated based on rotation of the magnetic disk and a reference signal. A delay pulse generation circuit that generates a delayed pulse based on its reference signal, and a detection pulse generation circuit that outputs a detection pulse when the phase difference is within an allowable range based on the delayed pulse and its comparison pulse. , a count number setting circuit that outputs a setting signal for setting the count number of this detection pulse based on the reference signal and the missing detection pulse, and the count number is set by the setting signal, and the phase difference starts counting the number of detected pulses when it changes from outside the allowable range to within the allowable range, and after counting a predetermined number of detected pulses, outputs a phase lock detection signal indicating that the phase of the comparison pulse has been locked. However, when the phase difference changes from within the permissible range to outside the permissible range during counting, the count circuit is configured to reset the number of counts according to the setting signal.

(Function) According to the phase lock detection circuit of the magnetic disk device according to the present invention, when the reference signal is input to the delayed pulse generation circuit, the phase difference between the comparison pulse generated based on the rotation of the magnetic disk and the reference signal is determined. A delayed pulse is generated that defines a tolerance range. Based on the delayed pulse and the comparison pulse, the detection pulse generation circuit outputs a detection pulse when the phase difference is within an allowable range. The count number setting circuit outputs a setting signal for setting the count number of detection pulses based on the reference signal and the omission of the detection pulse. The count circuit has a count number set by the setting signal, and when the phase difference changes from outside the tolerance range to within the tolerance range, it starts counting the number of detection pulses, and finishes counting the predetermined number of detection pulses. Thereafter, it is determined that the phase of the comparison pulse is locked, and a phase lock detection signal is output. Further, when the phase difference of the count circuit changes from within the permissible range to outside the permissible range during counting, the count number is set again using the setting signal.

(Example) Hereinafter, an example of a magnetic disk device according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic circuit configuration of a magnetic disk device used in an electronic still camera. In FIG. 1, 1 is a magnetic disk called a still video floppy, 2 is a spindle motor, and 3 4 is a drive circuit for driving the spindle motor; 4 is a magnetic head that is reciprocated in the radial direction of the magnetic disk 1 to record images; 5 is a stepping motor for reciprocating the magnetic head 4; 6 is a stepping motor for reciprocating the magnetic head 4; Reference numeral 1 indicates a drive circuit for the stepping motor 5, 7 an amplifier circuit for amplifying and outputting a video signal to the magnetic head 4, and 8 a control circuit for servo-controlling the spindle motor 2 and the stepping motor 5.

A so-called PG yoke 9 is provided in the center core at the center of the magnetic disk 1, and a so-called PG coil 10 is provided in the rotation range of the PG yoke 9 facing this PG yoke 9. A phase detector is configured by the PG coil 10, and a PG pulse is generated when the PG yoke 9 passes the PG yoke 10. The PG pulse is input to a phase lock detection circuit 12 via an amplifier 11 as a comparison pulse P for servo output based on the rotation of the magnetic disk 1. Note that, here, the comparison pulse P is one per rotation of the magnetic disk 1.

The phase lock detection circuit 12 has a delay pulse generation circuit 13 and a detection pulse generation circuit 14, as shown in FIG. Delay pulse generation circuit 13
is monostable multivibrator 15,16
A vertical synchronization signal VD generated by a synchronization signal generation circuit (not shown) is input to the monostable multivibrator 15 as a reference signal. The monostable multivibrators 15 and 16 are of the rising edge trigger type, and are also of the analog type in which the time constant is set by a combination of ordinary resistors and capacitors.

The monostable multivibrator 15 receives a pulse of constant pulse width T ₁ from its Q terminal (Fig. 3,
(see FIG. 4) is periodically output to the monostable multivibrator 16, and the monostable multivibrator 16 generates a delayed pulse K which is delayed by a certain period of time from the vertical synchronization signal VD based on the rising edge of the pulse of the monostable multivibrator 15.
is periodically output from its Q terminal. In FIGS. 3 and 4, the symbol τ indicates the delay time of the delay pulse K with respect to the vertical synchronization signal VD, and the pulse width T ₂ of the delay pulse K is the allowable range of the phase difference φ with respect to the vertical synchronization signal VD ( 7H±2H), and here, the delayed pulse K rises at 9H and falls at 5H from the later vertical synchronizing signal VD.

The detection pulse generation circuit 14 generates the delayed pulse K
and its comparison pulse P, the vertical synchronization signal
The detection pulse G is output when the phase difference φ of the comparison pulse P with respect to VD is within the permissible range, and the detection pulse generation circuit 14 is composed of an AND circuit, and the comparison pulse P is a monostable multivibrator. The signal is inputted to the detection pulse generation circuit 14 via 17. The monostable multivibrator 17 adjusts the pulse width T ₃ of the comparison pulse P based on the rise of the comparison pulse P.
It has the function of outputting a pulse with a pulse width T ₄ that is shorter than T ₂ and is also sufficiently shorter than T 2 . In addition,
The configuration of the monostable multivibrator 17 is as follows: monostable multivibrator 15,1
The configuration is similar to No. 6.

The phase lock detection circuit 12 receives the vertical synchronization signal.
A setting signal S for setting the count number of this detection pulse G based on VD and the omission of the detection pulse G
The count number is set by the count number setting circuit 18 that outputs , and its setting signal S, and when the phase difference φ changes from outside the tolerance range to within the tolerance range, it starts counting the number of detection pulses G. After counting a predetermined number of detection pulses G,
If the phase lock detection signal R is output assuming that the phase of the comparison pulse P is locked, and the phase difference φ changes from within the tolerance range to outside the tolerance range during counting, the setting signal S is used to output the phase lock detection signal R. A count circuit 19 is provided in which a count number is set.

The count number setting circuit 18 is composed of D flip-flops 20 and 21. Vertical synchronization signal is applied to the CK terminal of D flip-flop 20.
VD is input, power supply voltage +V is applied to its D terminal, detection pulse G is input to its CL terminal, and the D flip-flop 20 outputs an output from its Q terminal based on the clock rise of the vertical synchronizing signal VD. becomes high level, is cleared based on the rising edge of detection pulse G, and the output of the Q terminal becomes low level. Therefore, when the phase difference φ of the comparison pulse P is within the allowable range and there is no loss of the detection pulse G, the output waveform of the Q terminal changes between a high level and a low level at regular intervals as shown in Figure 3. As shown in FIG. 4, when the phase difference φ of the comparison pulse P is out of the allowable range and a dropout occurs in the detection pulse G, the waveform continues to be at a high level. Note that the details of the omission of the detection pulse G will be described later.

The Q terminal of the D flip-flop 20 is connected to the D terminal of the D flip-flop 21, and the CK terminal of the D flip-flop 21 is connected to the vertical synchronizing signal VD.
is input, and when the vertical synchronizing signal VD is input to the D flip-flop 21 when the Q terminal of the D flip-flop 20 is at a high level, the output of the Q terminal becomes high level based on the rising edge of the vertical synchronizing signal VD. . The output of this Q terminal is used as the setting signal S. This setting signal S is
As shown in FIG. 3, when the phase difference φ of the comparison pulse P is within the permissible range, a detection pulse G is generated every time the vertical synchronization signal VD is generated, and the vertical synchronization signal VD at the Q terminal of the D flip-flop 20 is generated. Vertical synchronization signal that continues even if it becomes high level due to
This does not occur because the output of the Q terminal of the D flip-flop 21 is maintained at a low level by the detection pulse G before VD is input, and the output of the Q terminal of the D flip-flop 21 is maintained at a low level.

The count circuit 19 here includes a presettable counter 22, an AND circuit 23, an OR circuit 24, and a memory circuit 25. The memory circuit 25 has a function of storing count data of the presettable counter 22. This storage circuit 25 is constituted by, for example, a programmable read-only memory (P-ROM) and a data entry switch (DIP). The count data is input to the presettable counter 22 based on the setting signal S. This presettable counter 22 is equipped with Q ₁ to Qn terminals, and Q ₁ to
The Qn terminal is connected to the OR circuit 24. the
The Q ₁ to Qn terminals are set to high level based on the count data and sequentially go from high level to low level based on the clock of the detection pulse G input via the AND circuit 23. The presettable counter 22 counts down the number of detection pulses G, and when the count value reaches zero, the outputs of all Q ₁ to Qn terminals become low level, and the OR circuit 24 A phase lock detection signal R is output from the circuit.

The phase lock detection signal R is input to the control circuit 8 and the AND circuit 23. If the phase difference φ of the comparison pulse P is within the allowable range, the AND circuit 23 connects the phase of the comparison pulse P and the vertical synchronization signal.
When the phase of VD is synchronized, it is assumed that the phase is locked and the passage of the detection pulse G is prohibited. As a result, the presettable counter 22 stops counting, and as long as the phase lock continues, the presettable counter 22 holds the count content "zero", and the output of the OR circuit 24 is When locked, the low level is maintained as shown in FIG.

Next, as shown in Figure 4, a certain vertical synchronization signal
Even if the phase difference φ of comparison pulse P ₁ with respect to VD ₁ was within the allowable range, the phase difference φ of comparison pulse P ₂ with respect to the next vertical synchronization signal VD ₂ was outside the allowable range, and the phase was locked. When the phase lock is removed from the vertical synchronization signal VD ₁
Since the comparison pulse P ₂ does not rise within the period of pulse width T ₂ of the delayed pulse K' delayed by the delay time τ, the detection pulse G is not output from the detection pulse generation circuit 14 and the detection pulse G is Missing occurs.

Therefore, when the output of the Q terminal of the D flip-flop 20 is at a high level based on the rise of a certain vertical synchronizing signal VD ₁ , if the detection pulse G is missing, the output of the Q terminal of the D flip-flop 20 continues to maintain a high level. Since the output of the Q terminal of the D flip-flop 20 is at a high level, the output of the Q terminal of the D flip-flop 21 changes from a low level to a high level based on the next rising edge of the vertical synchronization signal VD ₂ (time t ₁ ). Vertical sync signal following that vertical sync signal VD ₂
It continues to maintain a high level until its state is reversed by VD ₃ . If the comparison pulse P ₂ is generated at time t ₂ and the phase difference φ of the comparison pulse P falls within the allowable range at time t ₃ , then the detection pulse G is generated at time t ₃ .
is output, and the output of the Q terminal of the D flip-flop 20 changes from high level to low level with the rise of the detection pulse G. From now on, comparison pulse P
Assuming that _{the phase} difference φ of (time t ₅ ), it becomes low level, and this is repeated periodically.

At time _t1 , the output of the Q terminal of the D flip-flop 21 becomes high level, so the setting signal S is input to the presettable counter 22, and the count data is transferred from the storage circuit 25. Then, the outputs of the Q ₁ to Qn terminals become high level, and the output of the OR circuit 24 changes from low level to high level. When the output of the OR circuit 24 becomes high level, the output of the AND circuit 24 becomes high level.
3, the AND circuit 23 outputs the detection pulse G to the CK terminal of the presettable counter 22 every time the detection pulse G is input.
The presettable counter 22 repeats counting down the detection pulse G until the counted number becomes "zero". When the counted number reaches "zero", the outputs of the Q ₁ to Qn terminals become low level, and the OR circuit 24 maintains the high level until the counted number reaches "zero". When the count number reaches "zero", the outputs of the Q ₁ to Qn terminals become low level, so the output becomes low level and the OR circuit 2
4 outputs a phase lock detection signal R to a control circuit 8. Time tn indicates the point in time when the countdown number reaches "zero".

The control circuit 8 has a function of comparing the comparison pulse P with the vertical synchronization signal VD and servo-controlling the rotational phase of the magnetic disk 1 so that the phase difference φ of the comparison pulse P with respect to the vertical synchronization signal VD is maintained within an allowable range. In addition, it has a function of prohibiting photography even if the photography start signal A is input until the phase lock detection signal R is output, and the phase lock detection signal R is input. Under this condition, a video signal is output to the magnetic head 4, and thereby the video is normally recorded on the magnetic disk 1. The servo control of the magnetic disk is performed to automatically follow the rotational phase of the magnetic disk 1 as a control object to a target value, and is performed immediately after the spindle motor 2 is started by the start signal of the control circuit 8. In this case, the rotational phase of the magnetic disk 1 is unstable, and the phase difference φ of the comparison pulse P with respect to the vertical synchronization signal VD is far from the allowable range of the target value, and there is no way to approach the target value. is also oscillatory, and even if the phase difference φ of the comparison pulse P is within the permissible range at a certain time, the phase difference φ of the comparison pulse P may be outside the permissible range at the next time. , according to the invention:
The number of comparison pulses P whose phase difference φ is within the allowable range is counted, and after confirming that the phase difference φ of the comparison pulses P is stable for a certain period of time, the phase lock detection circuit R is output and the phase difference φ is within the allowable range. When the detection pulse G is out of range, the setting signal S is set based on the missing detection pulse G.
is output and the count data is set again, so phase lock detection can be performed accurately. In particular, according to the magnetic disk device according to the present invention, it is possible to accurately detect whether the phase difference φ of the comparison pulse P is within the permissible range (7H±2H), and the phase lock can be detected digitally. It is stable against temperature fluctuations in electronic circuits.

In the above embodiments, the monostable multivibrators 15 to 17 are of the analog type, but for example, by counting the number of clock signals that are periodically and accurately output, the number becomes a constant value. It is also possible to use a digital type whose output is maintained at a high level until the end.

Furthermore, in the embodiment, the configuration is such that the phase lock is detected by causing the count circuit to count down, but it is not necessary to limit it to countdown.

Further, the magnetic disk device according to the present invention may be any device having a servo control circuit, and can be applied not only to electronic still cameras but also to ordinary video magnetic disk devices, and not limited to video recording, but also digital audio recording. It can also be applied to magnetic disk devices.

(Effects of the Invention) As explained above, in the magnetic disk device according to the present invention, the phase lock detection circuit has a delay that defines the permissible range of phase difference between the comparison pulse generated based on the rotation of the magnetic disk and the reference signal. A delayed pulse generation circuit that generates a pulse based on its reference signal; a detection pulse generation circuit that outputs a detection pulse when the phase difference is within an allowable range based on the delayed pulse and its comparison pulse; A count number setting circuit that outputs a setting signal for setting the count number of detection pulses based on the reference signal and the omission of the detection pulse, and the count number is set by the setting signal, and the phase difference is set within an allowable range. Starts counting the number of detected pulses when the pulse changes from the outside to within an allowable range, and after counting a predetermined number of detected pulses, outputs a phase lock detection signal indicating that the phase of the comparison pulse is locked, and , when the phase difference changes from within the permissible range to outside the permissible range during counting, the count circuit is configured to reset the number of counts according to the setting signal.
This has the effect that it is possible to directly detect the phase difference between the comparison pulse and the reference signal, and to accurately detect the phase lock.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic circuit configuration of a magnetic disk device according to the present invention, FIG. 2 is a block diagram showing a detailed configuration of its phase lock detection circuit, and FIG. 3 is a block diagram showing a detailed configuration of its phase lock detection circuit. FIG. 4 is a timing chart showing the timing of the waveform when the phase lock detection circuit shifts from the phase non-lock state to the phase lock state. 1...Magnetic disk, 8...Control circuit, 12...Phase lock detection circuit, 13...Delay pulse generation circuit, 14...Detection pulse generation circuit,
18...Count number setting circuit, 19...Count circuit.

Claims (1)

[Scope of Claims] 1. A comparison pulse for servo output based on the rotation of a magnetic disk is compared with a reference signal, and the comparison pulse is controlled so that the phase difference of the comparison pulse with respect to the reference signal is maintained within an allowable range. In a magnetic disk device in which a servo control circuit for servo-controlling the rotational phase of a magnetic disk is provided with a phase lock detection circuit, the phase lock detection circuit generates a delay pulse for defining a tolerance range based on the reference signal. a delay pulse generation circuit; a detection pulse generation circuit that outputs a detection pulse when the phase difference is within an allowable range based on the delay pulse and the comparison pulse; and a detection pulse generation circuit that outputs a detection pulse when the phase difference is within an allowable range; a count number setting circuit that outputs a setting signal for setting the count number of the detection pulse based on the count number setting circuit, and the count number is set by the setting signal, and the phase difference changes from outside the tolerance range to within the tolerance range. When the count of the number of detection pulses is started, and after counting a predetermined number of detection pulses, a phase lock detection signal is output assuming that the phase of the comparison pulse is locked, and the phase difference is detected during counting. A magnetic disk device comprising: a counting circuit that resets the count number according to the setting signal when the number changes from within the permissible range to outside the permissible range.