JPS6374165A - Magnetic disk device - Google Patents

Abstract

PURPOSE:To accurately detect a phase clock by carrying out a counting action based on a phase clock detecting signal and a position error detecting pulse and therefore detecting directly the phase difference between a reference signal and its comparison pulse. CONSTITUTION:When a reference signal VD is supplied to a delay pulse generating circuit 13, a phase clock detecting circuit produces a delay pulse K to prescribe an allowable range of phase difference between a comparison pulse and the signal VD based on the revolution of a disk. A detection pulse generating circuit 14 outputs a detection pulse G based on the pulse K and the comparison pulse and when said phase difference is kept within its allowable range. A count number setting circuit 18 outputs a number setting signal S for pulses G based on omission of the signal VD and the pulse G. A counting circuit 19 counts the number of pulses G when the phase difference is set inside the allowable range from outside this range and then outputs a phase lock detecting sigal R. Furhermore the circuit 19 sets again its count value by the signal S when the phase difference is set outside the allowable range from inside this range.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention compares a servo comparison pulse output based on the rotation of a magnetic disk with a reference signal, and calculates the phase difference of the comparison pulse with respect to the reference signal. It relates to a magnetic disk device in which a phase lock detection circuit is provided in a servo control circuit that servo-controls the rotational phase of the magnetic disk so as to keep it within an allowable range. This invention relates to an improvement of the phase lock detection circuit of the device.

(Prior Art) Traditionally, in magnetic disk drives, a comparison pulse for servo output based on the rotation of a magnetic disk is compared with a reference signal, and the phase difference of the comparison pulse with respect to this vertical synchronization signal is within an allowable range. A servo control circuit is provided to servo control the rotational phase of the magnetic disk so that the rotational phase of the magnetic disk is maintained.

For example, in an electronic still camera, a so-called PG yoke is installed in the center core of a magnetic disk called a still video floppy, and a so-called PG coil is installed facing the rotation range of the PG yoke. PG coil constitutes a phase detector, and PG
The PG pulse generated when the yoke passes through the PG coil is used as a servo comparison pulse output based on the rotation of the magnetic disk, and the vertical synchronization signal generated by the synchronization signal generation circuit is used as a reference signal. Detecting the phase difference of the comparison pulse with respect to the vertical synchronization signal, and
The speed of the spindle motor for driving and rotating the magnetic disk is controlled by the FG multiplied signal from the frequency generator FG, and the rotational phase of the magnetic disk is servo-controlled.

(Problem to be Solved by the Invention) By the way, in order to properly record video, etc., the comparison pulse must be synchronized with the vertical synchronization signal, that is, the phase of the comparison pulse must match the vertical synchronization signal. Unlike video recording systems, electronic still cameras record images instantaneously, so the phase of the comparison signal must be locked to the phase of the vertical synchronization signal when shooting. There is a strict requirement to be present.

In particular, in electronic still cameras, when the spindle motor is started up, its rotation is unstable, and the phase difference of the comparison pulse with respect to the vertical synchronization signal fluctuates.If the phase of the comparison pulse is unstable, it may be difficult to record images. There is a problem in which accurate video recording cannot be performed.

Conventionally, when starting the spindle motor, the electronic still camera's release button is operated in anticipation of the time from the start until the phase of the comparison pulse is locked to the phase of the vertical synchronization signal. Measures such as prohibiting shooting and recording even when the vertical synchronization signal and the comparison pulse are in progress are taken to reduce the fluctuation of the phase error signal, which changes based on the phase difference between the vertical synchronization signal and the comparison pulse, and the phase error signal approaches a constant value when the phase is locked. Therefore, efforts are being made to utilize this approach to a constant value to construct a phase lock detection circuit.

When the spindle motor is started, allow for the time from the start until the phase of the comparison pulse is locked to the phase of the vertical synchronization signal, and during that time, shooting will not be recorded even if the release button of the electronic still camera is operated. The advantage of taking measures to prohibit this is that it is possible to record images without the need for a phase lock detection circuit, but the time it takes for the phase to be locked increases each time a photograph is taken.
They differ slightly and are not constant. Therefore, when using this method, in order to record images accurately, record the images assuming the longest time until the phase is locked. This method has the disadvantage that a prohibition time must be set, which often results in unnecessary waiting time during photographing.

In addition, with this conventional device, for some reason, for example, the electronic still camera held in one hand may hit something and receive a shock, and the rotation of the spindle motor will be disrupted. However, since there is no phase lock detection circuit by setting the video recording prohibition time, this cannot be detected and normal video recording may not be possible. .

On the other hand, since the phase error signal, which changes depending on the phase difference between the vertical synchronization signal and the comparison pulse, approaches a constant value when the phase is locked, a phase lock detection circuit is configured by utilizing this approach to the constant value. This method has the advantage that it does not require unnecessary waiting time during photographing, and that temporary loss of phase lock after phase lock can be detected.

By the way, the phase error signal that changes based on the phase difference between the vertical synchronization signal and the comparison pulse approaches a constant value when the phase is locked. Set the allowable range (usually within 2 to 5%) from the final phase error signal value when locked, and use a comparator etc.
Phase lock is determined based on whether the value of the phase error signal falls within the allowable range, but the final value of the phase error signal depends on the characteristics of the electronic components that make up the servo circuit, such as resistors and capacitors. Each electronic still camera is slightly different due to variations in the resistance value of the volume for adjusting the variations, etc., and the phase lock detection circuit is adjusted to accommodate the variations in the final value of the phase error signal. This has the disadvantage that adjustment means must be provided to adjust the range, and adjustment is troublesome.

Furthermore, even if the tolerance range is adjusted to be appropriate, the final value of the actual phase error signal may deviate from the value at the time of adjustment due to fluctuations in the power supply voltage or environmental temperature. There is a possibility that phase lock detection may not be performed accurately because it is determined that the phase lock is within the permissible range even though it is actually not within the permissible range.

Furthermore, since this device only detects when the phase error signal falls within the allowable range, it is possible that the phase error signal may fall outside the allowable range of 7H ± 2H as the phase difference standard for electronic still cameras due to changes in electronic components over time. Even if it is locked, there is a problem in which this cannot be detected. Note that here, the symbol H means one horizontal synchronization period of the video recording signal.

(Object of the Invention) The present invention has been made in consideration of the above circumstances, and its purpose is to detect accurate phase lock by directly detecting the phase difference of a comparison pulse with respect to a reference signal. An object of the present invention is to provide a magnetic disk device equipped with a phase lock detection circuit capable of performing the following steps.

(Means for Solving the Problems) A feature of the magnetic disk device according to the present invention is that its phase lock detection circuit defines an allowable range of phase difference between a comparison pulse generated based on rotation of a magnetic disk and a reference signal. A delay pulse generation circuit that generates a delayed pulse based on its reference signal, and a detection pulse generation circuit that outputs a detection pulse when the phase difference is within an allowable range based on the delayed pulse and its comparison pulse. , a count number setting circuit that outputs a setting signal for setting the count number of this detection pulse based on the reference signal and the missing detection pulse, and a count number setting circuit that outputs a setting signal for setting the count number of this detection pulse based on the reference signal and the missing detection pulse, and a count number setting circuit that outputs a setting signal for setting the count number of this detection pulse. When the detection pulse changes from outside the range to within the allowable range, it starts counting the number of detection pulses, and after counting a predetermined number of detection pulses, outputs a phase lock detection signal, assuming that the phase of the comparison pulse is locked; In addition, when the phase difference changes from within the permissible range to outside the permissible range during counting, the count circuit is configured to reset the count number using the setting signal.

(Function) According to the phase lock detection circuit of the magnetic disk device according to the present invention, when the reference signal is input to the delayed pulse generation circuit, the phase difference between the comparison pulse generated based on the rotation of the magnetic disk and the reference signal is determined. A delayed pulse is generated that defines a tolerance range. Based on the delayed pulse and the comparison pulse, the detection pulse generation circuit outputs a detection pulse when the phase difference is within an allowable range. The count number setting circuit outputs a setting signal for setting the count number of detection pulses based on the reference signal and the omission of the detection pulse. The count circuit has a count number set by the setting signal, starts counting the number of detection pulses when the phase difference changes from outside the tolerance range to within the tolerance range, and after counting a predetermined number of detection pulses, It outputs a phase lock detection signal assuming that the phase of the comparison pulse is locked. Further, when the phase difference of the count circuit changes from within the permissible range to outside the permissible range during the first run, the count number is set anew by the setting signal.

(Embodiment) An embodiment of a magnetic disk device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic circuit configuration of a magnetic disk device used in an electronic still camera. In FIG. 1, 1 is a magnetic disk called a still video floppy, 2 is a spindle motor, and 3 is a A drive circuit for driving the spindle motor, 4 a magnetic head that is reciprocated in the radial direction of the magnetic disk 1 to record an image, 5 a stepping motor for reciprocating the magnetic head 4, and 6 a magnetic head for reciprocating in the radial direction of the magnetic disk 1 to record an image. stepping motor 5
7 is an amplifier circuit for amplifying and outputting a video signal to the magnetic head 4, and 8 is a control circuit for servo-controlling the spindle motor 2 and stepping motor 5.

A so-called PG yoke 9 is provided in the center core at the center of the magnetic disk 1, and a so-called PG coil 1 is provided facing the PG yoke 9 in the rotation range of the PG yoke 9.
0 is provided, the PG yoke 9 and the PG coil 10 constitute a phase detector, and when the PG yoke 9 passes the PG yoke 10, a PG pulse is generated. That P
The G pulse is input to a phase lock detection circuit 12 via an amplifier 11 as a comparison pulse P for servo output based on the rotation of the magnetic disk 1. Note that here, the comparison pulse P is one per rotation of the magnetic disk 1.

The phase lock detection circuit 12 includes a delay pulse generation circuit 13 and a detection pulse generation circuit 14, as shown in FIG. The delayed pulse generation circuit 13 is composed of monostable multivibrators 15 and 16, and a vertical synchronization signal VD generated by a synchronization signal generation circuit (not shown) is input to the monostable multivibrator 15 as a reference signal. There is. The monostable multivibrators 15, 16 are of the rising edge trigger type, and are also of the analog type in which the time constant is set by a combination of ordinary resistors and capacitors.

The monostable multivibrator 15 periodically outputs a pulse with a constant pulse width T1 (see FIGS. 3 and 4) from its terminal to the monostable multivibrator 16. Based on the rising edge of the pulse No. 15, a delayed pulse K is periodically outputted from its Q terminal after being delayed for a certain period of time from the vertical synchronizing signal VD. In FIGS. 3 and 4, the symbol τ indicates the delay time of the delay pulse with respect to the vertical synchronization signal VD, and the pulse width T2 of the delay pulse is the tolerance range (7 ±2H), and here, the delay pulse is 9I-I than the later vertical synchronizing signal VD.
It is set to rise at the time of , and to fall at the time of 5H.

The detection pulse generation circuit 14 outputs a detection pulse G based on the delayed pulse and the comparison pulse P when the phase difference φ of the comparison pulse P with respect to the vertical synchronization signal VD is within the permissible range. The pulse generation circuit 14 here is constituted by an AND circuit, and the comparison pulse P is inputted to the detection pulse generation circuit 14 via a monostable multivibrator 17. The monostable multivibrator 17 has a function of outputting a pulse having a pulse width T that is shorter than the pulse width T3 of the comparison pulse P, and further shorter than the pulse width T, based on the rise of the comparison pulse P. Note that the configuration of the monostable multivibrator 17 is similar to that of the monostable multivibrator 15 and 16.

The phase lock detection circuit 12 includes a count number setting circuit 18 that outputs a setting signal S for setting the count number of detection pulses G based on the vertical synchronization signal VD and the omission of the detection pulse G, and When the count number is set and the phase difference φ changes from outside the tolerance range to within the tolerance range, counting of the number of detection pulses G is started, and after counting a predetermined number of detection pulses G, the comparison pulse P When the phase lock detection signal R is output assuming that the phase of is locked, and the phase difference φ changes from within the permissible range to outside the permissible range during counting, the count number is set anew by the setting signal S. A count circuit 19 is provided.

The count number setting circuit 18 is composed of D flip-flops 20 and 21. D flip flop 2
A vertical synchronizing signal VD is input to the CK terminal of 0.

A power supply voltage +V is applied to the D terminal, a detection pulse G is input to the CL terminal, and the D flip-flop 2
0, the output of its Q terminal becomes high level based on the clock rise of the vertical synchronization signal VD.

It is cleared based on the rising edge of the detection pulse G, and the output of the Q terminal becomes low level.

Therefore, when the phase difference φ of the comparison pulse P is within the allowable range and there is no dropout of the detection pulse G, the output waveform of the Q terminal changes between a high level and a low level at regular intervals as shown in FIG. As shown in FIG. 4, when the phase difference φ of the comparison pulse P is out of the allowable range and a dropout occurs in the detection pulse G, the waveform remains high. Note that the details of the omission of the detection pulse G will be described later.

The Q terminal of the D flip-flop 20 is connected to the D terminal of the D flip-flop 21, and the vertical synchronization signal VD is input to the CK terminal of the D flip-flop 21. When the vertical synchronizing signal VD is input while the terminal is at high level, the output of the Q terminal becomes high level based on the rising edge of the vertical synchronizing signal VD. The output of this Q terminal is used as the setting signal S. As shown in FIG. 3, when the phase difference φ of the comparison pulse P is within the allowable range, this setting signal S generates a detection pulse G every time the vertical synchronization signal VD is generated, and the Q Even if the terminal becomes high level due to a certain vertical synchronizing signal VD, the output of that Q terminal becomes low level due to the detection pulse G before the subsequent vertical synchronizing signal VD is input, and the Q terminal of the D flip-flop 21 becomes low level. This does not occur because the output is maintained at a low level.

The count circuit 19 here includes a presettable counter 22, an AND circuit 23, an OR circuit 24, and a memory circuit 25. The memory circuit 25 has a function of storing count data of the presettable counter 22. This storage circuit 25 is configured by, for example, a programmable read-only memory (P-ROM) and a data entry switch (DIP). The count data is input to the presettable counter 22 based on the setting signal S. This presettable counter 22 has Q1 to Qn terminals, and the Q1 to Qn terminals are connected to an OR circuit 24. The Q0 to Qn terminals are set to high level based on the count data and sequentially go from high level to low level based on the clock of the detection pulse G input via the AND circuit 23. The presettable counter 22 counts down the number of detection pulses G, and when the count value reaches zero, the outputs of all Q1 to Qn terminals become low level, and the OR circuit 24 detects the phase lock. A signal R is output.

The phase lock detection signal R is input to the control circuit 8 and the AND circuit 23. When the phase difference φ of the comparison pulse P is within the allowable range and the phase of the comparison pulse P and the phase of the vertical synchronization signal VD are synchronized, the AND circuit 23 determines that the phase is locked and prohibits the passage of the detection pulse G. do. As a result, the presettable counter 22 stops counting, and as long as the phase lock continues, the presettable counter 22 holds the count content "zero", and the output of the OR circuit 24 is The low level is maintained as shown in Figure 3.

Next, as shown in FIG. 4, assuming that the phase difference φ of the comparison pulse P□ with respect to a certain vertical synchronization signal VD is within the permissible range, the comparison pulse P2 with respect to the next vertical synchronization signal vD2 is
When the phase difference φ goes out of the allowable range and the phase lock goes from the phase locked state to the phase locked state, the delayed pulse delayed by the delay time from the vertical synchronizing signal VD1 is generated within the period of the pulse width T2 of '. Since the comparison pulse P2 does not rise, the detection pulse G is not output from the detection pulse generation circuit 14, and the detection pulse G is missing.

Therefore, when the output of the Q terminal of the D flip-flop 20 is at a high level based on the rise of a certain vertical synchronizing signal VD□, if the detection pulse G is missing, the Q terminal of the D flip-flop 20 output continues to maintain a high level. Since the output of the Q terminal of the D flip-flop 20 is at a high level, the output of the Q terminal of the D flip-flop 21 changes from a low level to a high level based on the next rise of the vertical synchronization signal VD (time ○). Then, the vertical synchronizing signal VD3 follows the vertical synchronizing signal VD.
The high level will continue to be maintained until the state is reversed. If the comparison pulse P2 is generated at time t, and the phase difference φ of the comparison pulse P falls within the allowable range at time t, then the detection pulse G is output at time t, and the Q terminal of the D flip-flop 20 is output. The output changes from high level to low level with the rise of the detection pulse G. From then on,
When it is assumed that the phase difference φ of the comparison pulse P is within the permissible range, the output of the Q terminal of the D flip-flop 20 becomes high level at the next rise of the vertical synchronization signal VD (time t 4 ), and the output of the Q terminal of the D flip-flop 20 becomes high level at the rise of the next vertical synchronization signal VD (time t 4 ). It becomes low level at the rise of (time ts), and this is repeated periodically.

At time t1, the presettable counter 22 has the following information:
Since the output of the Q terminal of the D flip-flop 21 becomes high level, the setting signal S is input, and the count number data is transferred from the storage circuit 25.
The outputs of the 1 to Qn terminals become high level, and the OR circuit 24
The output changes from low level to high level. OR circuit 2
When the output of 4 becomes high level, the output is input to the AND circuit 23, so the AND circuit 23 outputs the detection pulse G to the GK terminal of the presettable counter 22 every time the detection pulse G is input. . The presettable counter 22 repeats counting down the detection pulse G until the counted number becomes "zero".

Then, when the counted number becomes "zero", the Q
, ~The output of the Qn terminal becomes low level, and the OR circuit 24
maintains a high level until the counted number becomes "zero", and when the counted number reaches "zero", the output of the Q - Qn terminals becomes low level.
The output becomes low level, and the phase lock detection signal R is output from the OR circuit 24 to the control circuit 8. Time tn indicates the point in time when the countdown number reaches "zero".

The control circuit 8 converts the comparison pulse P into a vertical synchronization signal V
D, so that the phase difference φ of the comparison pulse P with respect to the vertical synchronization signal VD is kept within an allowable range.

In addition to having the function of servo-controlling the rotational phase of the magnetic disk 1, it also has a function of prohibiting photography even if the photography start signal A is input until the phase lock detection signal R is output. Ori.

On the condition that the phase lock detection signal R is input,
A video signal is output to the magnetic head 4, whereby video recording is normally performed on the magnetic disk 1. Servo control of the magnetic disk is performed to automatically follow the rotational phase of the magnetic disk 1 as a control target to a target value. Immediately after the spindle motor 2 is started by the start signal of the control circuit 8,
The rotational phase of the magnetic disk 1 is unstable, and the phase difference φ of the comparison pulse P with respect to the vertical synchronization signal VD is significantly different from the allowable range as a target value, and the way it approaches the target value also oscillates. Even if the phase difference φ of the comparison pulse P is within the tolerance range at a certain time, the phase difference φ of the comparison pulse P may be outside the tolerance range at the next time. According to the invention, the phase lock detection circuit R counts the number of comparison pulses P in which the one phase difference φ is within the allowable range, and confirms that the phase difference φ of the comparison pulses P is stable for a certain period of time. When the detection pulse G is out of the allowable range, the setting signal S is output based on the missing detection pulse G, and the count data is set again, so that phase lock detection can be performed accurately. In particular, according to the magnetic disk device according to the present invention, the phase difference φ of the comparison pulse P is within the permissible range (7H
±2H), and since the phase lock is detected digitally, it is stable against temperature fluctuations in the electronic circuit.

In the above embodiments, the monostable multivibrators 15 to 17 were of analog type, but
For example, it may be of a digital type that counts the number of clock signals output periodically and accurately and maintains the output at a high level until the number reaches a constant value.

Further, in the embodiment, the phase lock is detected by causing the count circuit to count down, but it is not necessary to limit it to countdown.

Furthermore, the magnetic disk device according to the present invention can be applied not only to electronic still cameras but also to ordinary video magnetic disk devices, as long as it has a servo control circuit, and can be applied not only to video recording but also to digital audio recording. The present invention can also be applied to magnetic disk drives.

(Effects of the Invention) As explained above, in the magnetic disk device according to the present invention, the phase lock detection circuit has a delay that defines the permissible range of phase difference between the comparison pulse generated based on the rotation of the magnetic disk and the reference signal. A delayed pulse generation circuit that generates a pulse based on its reference signal; a detection pulse generation circuit that outputs a detection pulse when the phase difference is within an allowable range based on the delayed pulse and its comparison pulse; A count number setting circuit outputs a setting signal for setting the count number of detection pulses based on the reference signal and the omission of the detection pulse, and the count number is set by the setting signal, and the phase difference is set from outside the tolerance range When the detected pulse changes within the allowable range, it starts counting the number of detected pulses, and after counting a predetermined number of detected pulses, it outputs a phase lock detection signal as if the phase of the comparison pulse is locked, and then starts counting. If the phase difference changes from within the permissible range to outside the permissible range during the process, the count circuit is configured to re-set the number of pulses to be counted according to the setting signal. This has the effect that accurate phase lock detection can be performed by detecting the phase lock.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic circuit configuration of a magnetic disk device according to the present invention, FIG. 2 is a block diagram showing a detailed configuration of a phase lock detection circuit, and FIG. 3 is a block diagram showing a detailed configuration of a phase lock detection circuit. FIG. 4 is a timing chart showing the timing of the waveform when the phase lock detection circuit shifts from the phase non-lock state to the phase lock state. 1... Magnetic disk 8... Control circuit 12... Phase lock detection circuit 13... Delay pulse generation circuit 14... Detection pulse generation circuit 18... Count number setting circuit 19... Count circuit Labor Diagram 2 Procedures Amendment Book May-22, 1986

Claims (1)

[Claims] (1) A comparison pulse for servo that is output based on the rotation of the magnetic disk is compared with a reference signal, and the rotation of the magnetic disk is performed so that the phase difference of the comparison pulse with respect to the reference signal is maintained within an allowable range. In a magnetic disk drive in which a servo control circuit that servo-controls a phase is provided with a phase lock detection circuit, the phase lock detection circuit includes a delay pulse generation circuit that generates a delay pulse for defining a tolerance range based on the reference signal. and based on the delayed pulse and the comparison pulse,
a detection pulse generation circuit that outputs a detection pulse when the phase difference is within an allowable range; and a count number that outputs a setting signal for setting the count number of the detection pulse based on the reference signal and the omission of the detection pulse. a setting circuit, and when the count number is set by the setting signal and the phase difference changes from outside the tolerance range to within the tolerance range, starts counting the number of detection pulses, and counts a predetermined number of detection pulses; After the completion, output a phase lock detection signal indicating that the phase of the comparison pulse is locked, and
A magnetic disk drive comprising: a counting circuit that resets the count number by the setting signal when the phase difference changes from within the permissible range to outside the permissible range during counting.