JP2604701B2 - Motor drive control device - Google Patents

Description

The present invention relates to a motor drive control device, for example, a CLV (Con
DRAW (Direc) using stant Linear Velocity disk
This device is suitable for application to an information recording / reproducing device such as a (t Read after Write) device.

[Summary of the Invention]

In a motor drive control device having a speed control system that locks the rotation speed of a motor to target speed information and a phase control system that locks the rotation phase of the motor to target phase information, when the speed control system is in a locking operation. The capacitor of the loop filter of the phase control system is charged with a voltage corresponding to the stable point voltage (the voltage generated when the speed control system locks at the supply point for supplying the speed target voltage from the phase control system). By doing so, when the phase control system enters the lock pull-in operation, it is not necessary to charge the capacitor with the stable point voltage.

[Conventional technology]

Conventionally, for example, in a DRAW device, as shown in FIG. 3, a CLV disk 3 is mounted on a turntable 2 coupled to an output shaft of a spindle motor 1, thus facing the disk 3 which rotates integrally with the turntable 2. to Yotsute to head 4 as required to move in the radial direction of the Deisusuku 3, Yotsute a track recorded in the recording range R _VAL of the disk 3 to tracking, information recorded in each track (For example, a television image signal), and the spindle motor 1
Conventionally, a PLL system as shown in FIG. 4 is used as the motor drive control device 5.

In FIG. 4, reference numeral 11 denotes a speed control system, and 12 denotes a phase control system. The speed control system 11 is supplied with a speed target voltage V _O corresponding to the speed at which the motor 1 is to be controlled from the reference input source 13, The system 11 drives and controls the motor 1 at a speed corresponding to the target speed voltage V _O. Further, the phase control system 12 outputs a reference clock signal CL corresponding to a horizontal synchronizing signal included in a video signal reproduced from the disk 3, for example, from the clock generation source.
_REF is supplied, and the phase control system 12 receives the reference clock signal C
The drive of the motor 1 is controlled with a phase synchronized with L _REF .

The speed control system 11 obtains a detection clock signal CL _DET indicating the rotation speed of the motor 1 from the rotation detector 21, and converts this into a detection speed voltage signal V _S in a frequency / speed conversion circuit (F / V) 22. The signal is supplied to the adding circuit 24 via the low-pass filter 23. Thus, the speed target voltage is applied to the output terminal of the adder circuit 24.
Target voltage signal FVS that is the sum of V _O and detection speed voltage signal V _S
Get. The target voltage signal FVS is supplied to the adding circuit 25, and the added output is supplied to the drive circuit 27 of the motor 1 via the amplifier circuit 26, thus forming a speed control loop.

The speed control system 11, by fed back the detected speed voltage signal V _S to the velocity target voltage V _O, output voltage of the adding circuit 25 is in a state where the speed lock time has decreased to a stable point voltage V _a.

The phase control system 12 has a phase comparison circuit 28, in which the phase of the detected clock signal CL _DET obtained from the rotation detector 21 is compared with the phase of the reference clock signal CL _REF , and the phase error output PHE Is supplied to the loop filter 29 to charge the capacitor C via the resistors R1 and R2. Thus, a DC voltage having a level corresponding to the phase error is formed in the capacitor C. Thus, the capacitor C
Is supplied to the addition circuit 25 as a target voltage signal for the speed control system 11.

Here, the loop gain of the speed control system 11 is selected to be a sufficiently large value, and when the speed target voltage V _O of the reference input source 13 is variably controlled, the rotation speed of the spindle motor 1 is set to a sufficiently short time. While the loop filter 29 is formed of a low-pass filter having a sufficiently long time constant, whereby the speed target voltage V _O
When the speed is changed, the speed control system 11
After the state becomes stable with respect to V _O , the phase of the motor 1 is locked to the reference clock signal CL _REF .

[Problems to be solved by the invention]

In conventional motor drive control device having the configuration of FIG. 3 and FIG. 4, 1 head 4 between the recording range R _VAL of the disk 3
When tracking one track,
A speed target voltage V _O corresponding to the radius of the track being tracked is supplied from the reference input source 13, and the spindle motor 1 rotates at a peripheral speed corresponding to the speed target voltage V _O.
At this time, the phase control system 12 controls the rotation of the motor 1 so that the phase of the detection clock signal CL _DET is locked to the reference clock signal CL _REF .

In this state, when the playback track of the head 4 is moved to the outside (or inside) of the disk 3, the speed target voltage V _O supplied from the reference input source 13 in response to the movement is changed to the circumference of the track tracked by the head 4. The speed is changed stepwise so as to decrease (or increase) so as to maintain a constant value. Therefore, the output FVS of the adder circuit 24 instantaneously decreases (or increases) by the change in the speed target voltage V _O , and the spindle motor 1 controls the speed control system 11 so that the rotation speed follows the change. The drive is controlled by At this time, since the loop gain of the speed control system 11 is selected to be a sufficiently large value, the rotation speed of the spindle motor 1 reaches a stable point in a short time, and thus the disk 3 has the changed speed / speed target voltage V It is driven to rotate at a peripheral speed equivalent to _O.

On the other hand, the reference clock signal CL supplied to the phase control system 12
_Since the frequency of _REF is simultaneously switched when the speed target voltage _VO is switched, the phase error output PHE at the output terminal of the phase comparison circuit 28 also varies. However, since the time constant of the loop filter 29 is selected to be a sufficiently large value, the phase error voltage PHC obtained at the output terminal of the loop filter 29 is the detection clock signal CL after the speed control system 11 has completed the following operation.
_The spindle motor 1 has a value corresponding to the phase difference between _DET and the reference clock signal CL _REF, and thus the spindle motor 1 is driven and controlled with the phase locked to the new reference clock signal CL _REF .

However, according to the conventional configuration shown in FIG. 4, the output of the loop filter 29 is added to the speed target voltage signal FVS by the adding circuit 25.
When the speed target voltage signal FVS greatly changes stepwise,
The charging voltage of the capacitor constituting the loop filter 29 is
Until the voltage signal FVS changes to a voltage that matches the voltage after the change (that is, during the charging time), there is a problem that the normal phase error voltage PHC cannot be supplied from the phase control system 12 to the adding circuit 25.

This means that, in principle, the phase lock operation cannot be performed during the follow-up time required to charge the capacitor C of the loop filter 29 to the voltage signal FVS, and the phase lock pull-in time is required accordingly. This means that the time constant of the loop filter 29 of the phase control system 12 must be selected to be a sufficiently large value from the viewpoint of the stability of the phase lock operation, and accordingly, the phase lock pull-in time becomes considerably long. Inevitable.

The present invention has been made in consideration of the above points, so that the phase control system 12 can enter the phase lock state in a time as short as possible after the speed following operation of the spindle motor 1 by the speed control system 11 is completed. It is intended to propose a motor drive control device as described above.

[Means for solving the problem]

In order to solve such a problem, in the present invention, a target clock signal CL _REF representing a target value of the rotation speed of the motor 1 is provided.
There is provided, the pulse of the target clock signal CL _REF is input for a predetermined time period, the first monostable multivibrator 31 outputs a logic "1" (or "0") output, a first monostable multivibrator First to convert the output from vibrator 31 to DC
And a detection clock signal CL _DET from the low-pass filter 32 and the rotation detector 21 for detecting the rotation of the motor 1 are supplied.
When a pulse of the detection clock signal CL _DET is input, a second monomultiplier that outputs a logical "0" (or "1") output in reverse to the output of the first monomultivibrator 31 for a predetermined period. A vibrator 35 and a second low-pass filter for converting the output from the second monomultivibrator 35 into a direct current
Motor control means (34, 2) for controlling the motor 1 based on an addition signal DC3 obtained by adding the output DC1 of the first low-pass filter 32 and the output DC2 of the second low-pass filter 36.
Speed control means 1 for locking the rotation speed of the motor 1 to a rotation speed corresponding to the target clock signal CL _REF.
1, a phase comparator 28 for comparing the phase of the detected clock signal CL _DET from the rotation detector 21 with the phase of the target clock signal CL _REF , and a capacitor C. A loop filter 29 to be superimposed on the addition signal DC3, and the addition signal DC3 when the speed control means 11 locks while the speed control means 11 performs the locking operation.
Is added to the voltage stability point voltage V _a to form a phase control starting voltage supplied to the capacitor C, when the speed control unit 11 is retracted to lock state, to cut off the supply of stable point voltage V _a phase Switching means 41 for supplying the phase error output PHE of the comparing circuit 28 to the capacitor C, and a phase control means 12 for clocking the phase of the detection clock signal CL _{DET and} the phase of the target clock signal CL _REF. I do.

[Action]

When the speed control unit 11 has decreased to the lock state, the voltage of the supply point of the target voltage signal PHC supplied from the phase control means 12 becomes stable point voltage V _a. The phase control means 12 includes a switching means 41
When the speed control unit 11 is in locking pull operation via a loop filter voltage corresponding to the stable point voltage V _a
The capacitor C of 29 is charged in advance and the speed control means 11
There when you exit lock pull operation switches from the voltage corresponding to the voltage of the capacitor C to the stable point voltage V _a to a voltage based on the phase error output PHE of the phase comparison circuit 28.

In this way, when the phase control means 12 starts the lock pull operation, the capacitor C of the loop filter 29, the need to charge the stable point voltage V _a is eliminated, the partial phase control means 12 Phase lock pull-in time can be reduced.

Thus, in a state where the rotation speed of the motor 1 rotates at a speed that matches the target clock signal CL _REF ,
The relative period T ₂ of the target clock signal CL _REF 1 and the second
Even if the ratio of the operation time T ₁ of the multivibrator 31 and 35 are changed, the output DC1 from the first monostable multivibrator 31 which is obtained through the first low-pass filter 32, the second
Output DC3 obtained by adding the output DC2 from the second monostable multivibrator 35 which is obtained through the low-pass filter 35 can always be maintained at a constant value, the period T ₂ of the result if the target clock signal CL _REF Even in the case of a change, the stable point voltage always set to a constant value may be prepared in the phase control means 12.

〔Example〕

Referring to the drawings, an embodiment of the present invention will be described in detail with reference to FIG.

In FIG. 1, a speed control system 11 is adapted to output a target clock signal.
It has a first mono-multivibrator 31 that receives CL _REF as target speed information. The output ▼ is converted to a direct current in a low-pass filter 32 and output to an addition circuit 34 through an addition resistor 33.

Further, the speed control system 11 has a second monomultivibrator 35 which receives a detection clock signal CL _DET of the rotation detector 21 as detection speed information, and converts the Q output 35Q of the rotation into a direct current by a low-pass filter 36. , The output end is a resistor for addition
The signal is sent to an adding circuit 34 through an adding resistor 37 connected to 33.

The operation time T1 of the mono-multi vibrators 31 and 35
Is selected equal time to each other, thereby, in a state where the rotation speed of the motor 1 is rotating at a speed that matches the speed target value represented Te cowpea to the frequency of the target clock signal CL _REF, monostable multivibrator 31 Is triggered by the target clock signal CL _REF (FIG. 2 (A1)) and its output ▲ ▼ (FIG. 2 (B1)) is during the operation time T1.
While the logic "1" falls to logic "0", the monomultivibrator 35 is triggered by the detection clock signal CL _DET (FIG. 2 (C1)) and its Q output 35Q (FIG. 2 (C1)). D1)) is logic “0” to logic “1” during the operation time T1.
It is made to rise.

As a result, the value of the DC voltage DC1 obtained at the output terminal of the low-pass filter 32 is, as shown in FIG. 2 (E1), a mono-multiplier for the pulse interval T2 (FIG. 2 (A1)) of the target clock signal CL _REF . The value is determined by the ratio of the section T3 of the logic “1” of the output ▼ of the vibrator 31. On the other hand, the value of the DC output DC2 obtained at the output end of the low-pass filter 36 is, as shown in FIG.
_The value corresponds to the ratio of the interval T1 of the logic "1" of the output 35Q of the monomultivibrator 35 to the pulse interval T2 of _DET (FIG. 2 (C1)).

However, as apparent from comparison of FIGS. 2 (B1) and (D1), the sections T3 and T1 of the logic "1" of the outputs ▲ ▼ and 35Q are clock signals CL _REF and CL _DET respectively.
Has a value corresponding to the duty ratio of
The value of the DC output DC3 (FIG. 2 (G1)) obtained by adding the DC outputs DC1 and DC2 through 33 and 37 is always a constant value even if the ratio of the section T1 (or T3) to the section T2 changes. Will be maintained.

The reason is that the DC voltages DC1 and DC2 output ▲
▼ and the value corresponding to the interval T3 and T1 of the logic “1” of 35Q, but the sum of the intervals T3 and T1 is equal to the interval T2, and therefore, even if the ratio of T3 and T1 becomes smaller T2 Therefore, even if it changes, the value of the output DC3, which is the sum of the outputs DC1 and DC2, maintains a constant value.

For example, FIG. 2 (A1) to FIG.
2) As shown in (G2), clock signals CL _REF and CL
_When the repetition period T2 of the _DET becomes, for example, 1/2 (this means that the rotation speed of the motor has become 2 times), since the operation time T1 of the mono-multi vibrators 31 and 35 does not change, The ratio of the sections T1 and T3 to the section T2 changes,
As a result, the DC outputs DC1 and DC2 of the low-pass filters 32 and 36 change (FIGS. (E2) and (F2)), and the sum of the outputs DC3 (FIG. 2 (G2)) is the value of the motor 1 Of the output DC3 before the rotation speed is changed (Fig. 2 (G
1)).

In addition to the above configuration, the phase control system 12 includes a stable point voltage source.
Stable point voltage V _a from 42 to capacitor C of the loop filter 29
Is supplied through a switch circuit 41, and the output of the loop filter 29 is supplied through a buffer amplifier circuit 43 to an adder circuit 34.
Is supplied to the resistor 44.

Switching circuit 41 is switched controlled Te speed lock signal SPL Niyotsu, Yotsute to ON operation during speed control system 11 is the speed lock pull operation, the output voltage V _a stable point voltage source 42 switch The capacitor C of the loop filter 29 is charged through the circuit 41.

In this case, the phase control system is provided with the target clock signal CL _REF as the target phase information and the detected clock signal CL _DET as the detected phase information to the phase comparison circuit 28 in the same manner as described above with reference to FIG. And the error output PHE is charged in the capacitor C of the loop filter 29.

In the above configuration, when the track being tracked by the head 4 is changed, the rotation speed of the motor 1 is switched so that the peripheral speed at the position of the head 4 becomes constant, and therefore, the target clock signal CL _REF is changed. The repetition period is changed. At this time, when the trigger cycle of the mono-multivibrator 31 is changed, the ratio of the section T3 in which the output ▲ ▼ is at logic “1” to the repetition cycle T2 is changed, so that the output of the low-pass filter 32 is changed. DC1 voltage level drops. As a result, the output of the addition circuit 34 decreases due to the once-decreased addition output voltage DC3,
This is inverted in the amplifier circuit 26 and supplied to the drive circuit 27, so that the rotation speed of the motor 1 increases. When the rotation speed of the motor 1 increases, the repetition period of the detection clock signal CL _DET becomes shorter, and accordingly, the period T1 during which the output 35Q of the monomultivibrator 35 becomes logic "1".
Is increased with respect to the period T2, and the voltage level of the output DC2 of the low-pass filter 36 rises correspondingly, and as a result, the signal level of the output DC3 rises and returns.

Eventually, the rotation speed of the motor 1 becomes the target clock signal CL _REF
When the speed is increased to the speed corresponding to, the trigger periods for the mono-multi vibrators 31 and 35 become equal to each other,
Thus ready described above for FIG. 2 (A2) ~ (G2), the signal level of the output DC3 this time is supplied to the addition circuit 34 returns to a stable point voltage V _a.

In this way, the speed control system 11 operates to keep the motor 1 in a state in which it coincides with the repetition period of the target clock signal CL _REF . During this time, the phase control system 12 is controlled so as not to perform the phase lock pull-in operation. . That is, while the speed control system 11 is performing the lock pull-in operation, the speed lock signal SPL is supplied to the switch circuit 41 of the phase control system to turn on.
Accordance connexion stable point output voltage V _a of the voltage source 42 is supplied to the capacitor C of the loop filter 29 through the switching circuit 41, this voltage is supplied to the adding circuit 34 through a buffer amplifier circuit 43.

In this state, when the speed control system 11 is eventually pulled into the locked state, the logic level of the speed lock signal SPL changes and the switch circuit 41 is turned off, and the stable point voltage source 42
Voltage V _a of ready not supplied to the capacitor C, the capacitor C switches to a state in which the phase error output PHE of the phase comparator 28 is supplied. Accordingly, thereafter, the phase control system 12 sends a phase lock signal to the adding circuit 34 based on the charging voltage of the capacitor C which changes according to the phase error output PHE of the phase comparing circuit 28.

Thus while the phase lock error signal PHC supplied through a buffer amplifier circuit 43 from the loop filter 29, the output DC3 when the speed control system 11 is locking which has a stable point voltage V _a, the phase error Output PHC is stable point voltage source 42
It means that the stable point voltage V _a with respect to changes from the voltage, it is not necessary to phase control system 12 charges the stable point voltage V _a of the output capacitor C DC3 upon entering the phase lock operation, Thus, the phase lock operation can be immediately started.

In the above description, the embodiment in which the present invention is applied to the case where a video signal is reproduced from an LCV disk has been described. However, the present invention can be applied to the case where recording is performed.

Also, the present invention is not limited to CLV discs,
After obtaining the lock control state of the rotation speed of the motor 1 by 1, the present invention can be widely applied to an information recording and reproducing apparatus in which the phase is locked by a phase control system 12.

〔The invention's effect〕

As described above, according to the present invention, the capacitor of the loop filter is charged to the stable point voltage of the speed control system until the lock state is obtained by the speed control system. Can eliminate the need to charge the loop filter capacitor when starting the control operation,
As a result, the phase lock pull-in time of the phase control system can be remarkably shortened as compared with the conventional case.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a motor drive control device according to the present invention, FIG. 2 is a signal waveform diagram for explaining the operation thereof, and FIG. 3 is a schematic configuration of a DRAW device to which the present invention can be applied. FIG. 4 is a block diagram showing a conventional motor drive control device. 11 ... speed control system, 12 ... phase control system, 31, 35 ... mono-multi vibrator, 32, 36 ... low-pass filter, 34
…… Addition circuit, 41… Switch circuit.

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-52-106415 (JP, A) JP-A-57-116239 (JP, U) JP-A-59-118156 (JP, U) 40650 (JP, Y1)

Claims (1)

(57) [Claims] A target clock signal representing a target value of the motor rotation speed is supplied, and when a pulse of the target clock signal is input, a logical "1" (or "0") output is output for a predetermined period. A first mono-multivibrator for outputting, a first low-pass filter for converting the output from the first mono-multivibrator to a direct current, and a detection clock signal from a rotation detector for detecting rotation of the motor; When the pulse of the detection clock signal is input, a second monomulti output that outputs a logical "0" (or "1") output in reverse to the output of the first monomultivibrator during the predetermined period. A vibrator, a second low-pass filter for converting an output from the second mono-multi vibrator into a direct current, an output of the first low-pass filter, and the second low-pass filter A motor control means for controlling the motor based on an addition signal obtained by adding the output to the motor; a speed control means for locking a rotation speed of the motor to a rotation speed corresponding to the target clock signal; A phase comparison circuit for comparing the phase of the detected clock signal from the detector with the phase of the target clock signal, a loop filter having a capacitor, and superimposing the charging voltage of the capacitor on the addition signal as a phase control signal; While the speed control means is performing the lock pull-in operation,
When the speed control means locks, a voltage substantially equal to the stable point voltage which is the voltage of the addition signal is supplied to the capacitor, and when the speed control means is pulled into the locked state,
Switching means for interrupting the supply of a voltage substantially equal to the stable point voltage and supplying the phase error output of the phase comparison circuit to the capacitor, wherein a phase of the detection clock signal and a phase of the target clock signal are determined. A motor drive control device comprising: a locking phase control means.