JPS61177183A - Motor driving controller - Google Patents

Abstract

PURPOSE:To quickly carry out phase control system phase lock leading-in, by charging the condenser of a loop filter at a stable point voltage before a locking state is obtained in a speed control system. CONSTITUTION:The driving controller of a motor 1 is provided with a speed control system 11 based on detection speed information and target speed information, and with a phase control system 12 based on detection phase information and target phase information. The phase control system 12 is provided with a phase comparator 28, a loop filter 29, a switch circuit 41, and a stable point power source 42. In this manner, when the sped control system 11 is put in a locking state, then the voltage of the adder circuit 34 of target voltage signal PH dispatched from the phase control system 12 is decided to be stable point voltage. When the speed control system 11 is under lock-leading-in operation, then the voltage corresponding to the stable point voltage is previously charged into the condenser C of the loop filter 29 by the phase control system 12, and on the termination of the lock-leading-in operation of the system 11, the voltage is switched to voltage based on phase error output PHE.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a motor drive control device, for example, a CLV
(constant Linear Velocity
) D RAW (Direct Re) using a disc
The present invention is suitable for application to information recording and reproducing devices such as ad after write devices.

[Summary of the invention]

In a motor drive control device having a speed control system that locks the rotational speed of the motor to target speed information and a phase control system that locks the rotational phase of the motor to the target phase information, when the speed control system is in a lock retraction operation. , charge the capacitor of the loop filter of the phase control system with a voltage corresponding to the stable point voltage (the voltage that occurs when the speed control system locks to the supply point that supplies the speed target voltage from the phase control system). By doing so, when the phase control system enters the lock pull-in operation, no time is required to charge the stable point voltage to the capacitor.

[Conventional technology]

Conventionally, for example, in a DRAW device, as shown in FIG. 3, a CLV disk 3 is mounted on a turntable 2 connected to the output shaft of a spindle motor 1, and a CLV disk 3 is mounted on a turntable 2 that faces the disk 3 that rotates together with the turntable 2. The information recorded on each track (for example, television video Conventionally, the motor drive control device 5 for the spindle motor 1 is
A PLL system as shown in the figure is used.

In FIG. 4, 11 is a speed control system, I2 is a phase control system, and the speed control system 11 is supplied with a target voltage v0 corresponding to the speed at which the motor 1 is to be controlled from the reference human power [13]. is this speed target voltage■. The motor 1 is driven and controlled at a speed corresponding to . Further, the phase control system 12 is supplied with a reference clock signal CL*tt corresponding to a horizontal synchronizing signal included in a video signal reproduced from the disk 3, for example, from a clock generation source, and the phase control system 12 receives this reference clock signal CLIIKF. The motor l is driven and controlled in a phase synchronized with the .

The speed control system 11 obtains a detection clock signal CLott representing the rotation speed of the motor l from a rotation detector 21, converts it into a detection speed voltage signal V in a frequency speed conversion circuit (F/V) 22, and then converts it into a detection speed voltage signal V. The signal is supplied to an adder circuit 24 via a filter 23. Thus, at the output end of the adder circuit 24, a target voltage signal FVS is obtained which is the sum of the speed target voltage V and the detected speed voltage signal v3. This target voltage signal F
VS is supplied to an adder circuit 25, and the added output is supplied to a drive circuit 27 of the motor 1 via an amplifier circuit 26, thus forming a speed control loop.

This speed control system 11 receives a detected speed voltage signal ■.

By feeding back the speed target voltage vo,
When the output voltage of the adder circuit 25 reaches the stable point voltage ■1, the speed is locked.

The phase control system 12 has a phase comparison circuit 28, and the phase comparison circuit 28 uses the phase of the detected clock signal CI, +xt obtained from the rotation detector 21 as a reference clock signal CL.
□, the phase error output PHE is supplied to the loop filter 29, and charged to the capacitor C via the resistors R1 and R2. In this way, a DC voltage of a level corresponding to the phase error is formed in the capacitor C. In this way, the phase error voltage formed on capacitor C is
The adder circuit 2 serves as a target voltage signal for the speed control system 11.
5.

Here, the loop gain of the speed control system 11 is selected to be a sufficiently large value, so that when the speed target voltage V of the reference input source 13 is variably controlled, the spindle motor 1
The loop filter 29 is constructed of a low-pass filter with a sufficiently long time constant, so that the speed target voltage V can be followed in a sufficiently short time.

When V is changed, after the speed control system 11 becomes stable with respect to the new speed target voltage V, the phase of the motor l is phase-locked to the reference clock signal CL*ty.

[Problem that the invention seeks to solve]

In the conventional motor drive control device having the configuration shown in FIGS. 3 and 4, when the head 4 is tracking one track between the recording range RVAL of the disk 3, the radius corresponds to the radius of the track being tracked. A speed target voltage v0 is supplied from the reference input source 13, and the spindle motor 1 rotates at a circumferential speed corresponding to this speed target voltage v0. At this time, the phase control system 12 outputs the detection clock signal CLD! The rotation of motor l is controlled so that the phase of motor l is phase-locked to reference clock signal CLm*r.

In this state, when the reproduction track of the head 4 is moved to the outside (or inside) of the disk 3, the speed target voltage V supplied from the reference input source 13 correspondingly changes around the track tracked by the head 4. The speed is changed stepwise to decrease (or increase) so as to maintain a constant value.

Therefore, the output FVS of the adder circuit 24 is the speed target voltage v0
The rotational speed of the spindle motor 1 is controlled by the speed control system 11 so that the number of rotations of the spindle motor 1 follows the change. At this time, since the loop gain of the speed control system 11 is selected to be a sufficiently large value, the rotational speed of the spindle motor 1 reaches a stable point in a short time, and thus the disk 3 has the changed speed speed target voltage . It is rotated at a circumferential speed corresponding to .

On the other hand, the reference clock signal CL supplied to the drive control system 12
Since the frequency of the I-F is switched at the same time as the speed target voltage V is switched, the phase error output PHE at the output end of the phase comparison circuit 28 also changes. However, since the time constant of the loop filter 29 is selected to be a sufficiently large value,
Target voltage signal P obtained at the output end of the loop filter 29
HC is the detection clock signal CLD! after the speed control system 11 completes the follow-up operation. The value corresponds to the phase difference between A and reference clock signal CL□2, and thus spindle motor l receives the new reference clock signal CL□.

The drive is controlled in a phase-locked state.

However, according to the conventional configuration shown in FIG.
Since it is configured to be added in an analog manner to VS,
When the speed target voltage signal FVS changes greatly in a stepwise manner, the charging voltage of the capacitor constituting the loop filter 29 changes to a voltage that matches the voltage after the change in the voltage signal FVS (that is, during the charging time). ), the regular target voltage signal PHC is sent from the phase control system 12 to the adder circuit 25.
There is a problem in not being able to supply.

This means that, in principle, phase lock operation can be achieved during the follow-up time required to charge the capacitor C of the loop filter 29 to the voltage signal FVS, but a phase lock pull-in time is required for this period. Moreover, since the time constant of the loop filter 29 of the phase control system 12 needs to be selected to a sufficiently large value from the viewpoint of stability of the phase lock operation, the phase lock pull-in time will be considerably longer. It is unavoidable.

The present invention has been made in consideration of the above points, and is designed to enable the phase control system 12 to enter the phase lock state in as short a time as possible after the speed control system 11 finishes following the speed of the spindle motor 1. The purpose of this paper is to propose a motor drive control device that has the following features.

Means for Solving Problem C] In order to solve this problem, in the present invention, detected speed information CLott representing the rotational speed of the motor 1 and target speed information CL, ll! representing the target value are provided. , and a speed control system 11 that locks the rotational speed of the motor to target speed information CL IEF based on the rotational speed of the motor 1 based on detected phase information CLott representing the rotational phase of the motor 1 and target phase information CLIEF representing the target value. Target phase information CL*tv
In the motor drive control device, the phase control system 12 has a phase control system 12 that locks to the detected phase information CLo.
ty and target phase information CL□2 is charged to a capacitor C of a loop filter 29, and a target voltage signal PHC is supplied to the speed control system 11 based on this charging voltage. When the speed control system 11 is in the lock retracting operation, the capacitor C is charged with a voltage corresponding to the stable point voltage v1 at the supply point of the speed target voltage DC3 of the speed control system 11, and the speed control system 11 When the lock pull-in operation is completed, the voltage of the capacitor C is switched from the voltage corresponding to the stable point voltage V to the voltage based on the phase error output PHE.

[Effect]

When the speed control system 11 is in a locked state, the supply point of the target voltage signal PHC supplied from the phase control system 12, that is, the voltage of the adding circuit 25 becomes a stable point voltage V. When the speed control system 11 is in the lock retraction operation, the phase control system 12 charges the capacitor C of the loop filter 29 with a voltage corresponding to the stable point voltage V in advance, so that the speed control system 11 performs the lock retraction operation. When the operation is completed, the voltage of the capacitor C is switched from the voltage corresponding to the stable point voltage v8 to the voltage based on the phase error output PHE of the phase comparison circuit 28.

By doing this, when the phase control system 12 starts the lock pull-in operation, there is no need to charge the stable point voltage V to the capacitor C of the loop filter 29. Phase lock pull-in time can be shortened.

〔Example〕

Referring now to the drawings, one embodiment of the present invention will be described in detail with reference to FIG. 1, in which parts corresponding to those in FIG. 4 are denoted by the same reference numerals.

In FIG. 1, the speed control system 11 has a first mono-multivibrator 31 that receives a target clock signal CLmtr as target speed information, and converts its output 31Q into DC through a low-pass filter 32 and adds it through an adding resistor 33. Output to circuit 34.

The speed control system 11 also includes a second mono-multivibrator 35 that receives the detection clock signal CLD*T of the rotation detector 21 as detected speed information, and after converting its Q output 35Q to DC using a low-pass filter 36, outputs The signal is sent to the adding circuit 34 through the adding resistor 37 whose side end is connected to the adding resistor 33.

Operating time T of these mono multivibrators 31 and 35
1 are selected to be equal to each other, so that the rotational speed of the motor 1 is set to the target clock signal CLI! In a state in which the mono multivibrator 31 is rotating at a speed matching the speed target value represented by the frequency of F, the mono multivibrator 31 receives the target clock signal CLm! While the mono-multivibrator 35 is triggered by the detection clock signal CL*tv (FIG. 2 (cI)) so that its Q output 35Q (FIG. 2 (DI)) rises from logic rOJ to logic "1" during operating time T1. is being done.

As a result, the value of the DC voltage DCI obtained at the output end of the low-pass filter 32 is as shown in FIG. 2 (El), the target clock signal CLI! The value is determined by the ratio of the logic "1" interval T3 of the output 31Q of the mono multivibrator 31 to the pulse interval T2 of F (FIG. 2 (AI)). On the other hand, the value of the DC output DC2 obtained at the output end of the low-pass filter 36 is as shown in FIG. 2 (Fl), as shown in FIG.
The value corresponds to the ratio of the logic "1" interval Tl of the output 35Q of the mono-multivibrator 35 to the pulse interval T2 of )).

However, as is clear from comparing FIG. 2 (B1) and (DI), the sections T3 and T1 of the logic rlJ of the outputs 31Q and 35Q correspond to the duty ratio of the clock signals CL□2 and CLeit, respectively. Therefore, the DC output DC3 obtained by adding the DC outputs DCI and DC2 through the resistors 33 and 37 (Fig. 2 (
The value of Gl)) always maintains a constant value even if the ratio of the interval TI (or T3) to the interval T2 changes.

The reason for this is that the DC voltages DCI and DC2 are the logic "1" sections T3 and T1 of the output card]2σ and 35Q, respectively.
However, the sum of this interval T3 and T1 is equal to the interval T2, so even if the ratio of T3 and T1 changes as T2 becomes smaller, the output becomes the sum of the output DCI and DC2. The value of DC3 will remain constant.

For example, in correspondence with FIG. 2 (A1) to (G1), FIG.
As shown in A2) to (G2), the clock signals CL□,
When the repetition period T2 of CL□7 becomes, for example, 1/2 (this means that the rotational speed of the motor is doubled), the operating time T1 of the mono multivibrators 31 and 35 changes. Therefore, the interval T for interval T2
1 and T3 change, which causes the DC outputs DCI and DC2 of the low-pass filters 32 and 36 to change (Fig. 2 (F2) and (F2)), but the output DC3 (Fig. The value of G2)) becomes equal to the value of the output DC3 (FIG. 2 CGI)) before the rotational speed of the motor 1 is changed.

In addition to the above configuration, the phase control system 12 is configured to supply the stable point voltage v1 from the stable point voltage source 42 to the capacitor C of the loop filter 29 via the switch circuit 41, and buffer the output of the loop filter 29. Amplification circuit 42
The resistor 43 of the adder circuit 34 is supplied through the resistor 43 of the adder circuit 34.

The switch circuit 41 is switched and controlled by the speed lock signal SPL, and is turned on while the speed control system 11 is performing the speed lock pull-in operation, so that the stable point voltage source 42 is switched on.
The capacitor C of the loop filter 29 is charged with the output voltage v1 of the loop filter 29 through the switch circuit 41.

In this case, in the phase control system, the phase comparator circuit 28 uses the target clock signal CL11! as the target phase information in the same manner as described above with reference to FIG. , and receives the detected clock signal CLl,t? as detected phase information. and charges the capacitor C of the loop filter 29 with the error output PHE.

In the above configuration, when changing the track tracked by the head 4, the rotational speed of the motor 1 is changed so that the circumferential speed at the position of the head 4 is constant. The repetition period is changed. At this time, by changing the trigger cycle of the mono multivibrator 31, its output 31Q becomes logic "1".
By changing the ratio of the interval T3 to the repetition period T2, the voltage level of the output DC1 of the low-pass filter 32 is reduced. As a result, the added output voltage DC3
The output of the adder circuit 34 decreases as a result of the temporary decrease in the output of the adder circuit 34, which is inverted in the amplifier circuit 26 and supplied to the drive circuit 27, thereby increasing the rotational speed of the motor 1. As the rotational speed of the motor 1 increases, the repetition period of the detection clock signal CLott becomes shorter, so that the output 35Q of the mono multivibrator 35 becomes the logic "l".
'' increases, the voltage level of the output DC2 of the low-pass filter 36 increases, and as a result, the signal level of the output DC3 rises again.

Eventually, the rotational speed of motor l reaches the target clock signal CLmt.
When the speed increases to a speed corresponding to The signal level of the output DC3 returns to the stable point voltage v1.

In this way, the speed control system 11 follows the motor 1 to a state that matches the repetition period of the target clock signal CLIItF, but during this time the phase control system 12 is controlled so as not to perform the phase lock pull-in operation. That is, while the speed control system 11 is performing the lock retracting operation, the speed lock signal SPL is supplied to the switch circuit 41 of the phase control system to turn it on. Therefore, the output voltage V of the stable point voltage source 42,
is supplied to the capacitor C of the loop filter 29 through the switch circuit 41, and this voltage is supplied to the buffer amplifier circuit 42.
The signal is supplied to the adder circuit 34 via.

In this state, when the speed mm system 11 is eventually pulled into the locked state, the logic level of the speed lock signal SPL changes to turn off the switch circuit 41, and the voltage 1 of the stable point voltage source 42 is applied to the capacitor C. The capacitor C is supplied with the output Pi (
Switch to a state where E is supplied. Therefore, from now on, the phase control system 12 sends a phase lock signal to the adder circuit 34 based on the charging voltage of the capacitor C, which changes according to the output PHH of the phase comparison circuit 28.

Thus, from the loop filter 29 to the buffer amplifier circuit 42
When the speed control system 11 is locked, the phase lock error signal PHC supplied via the phase lock error signal PHC has a stable point voltage V, whereas the output DC3 has a stable point voltage V, while the phase error output PHC has a stable point voltage V of the stable point voltage source 42. Since the voltage will change from this voltage based on the voltage V, there is no need to charge the capacitor C with the stable point voltage V of the output DC3 when the phase control system 12 enters phase lock operation, and thus the phase will be changed immediately. Lock operation can be entered.

In the above description, an embodiment has been described in which the present invention is applied when reproducing a video signal from an LCV disk, but it can also be applied when recording.

Furthermore, the present invention is not limited to CLV discs, but is widely applicable to information recording and reproducing devices in which the speed control system 11 obtains a locked control state of the rotational speed of the motor 1, and then the phase control system 12 locks the phase. It is possible.

〔Effect of the invention〕

As described above, according to the present invention, the capacitor of the loop filter is charged to the stable point voltage of the speed control system before the speed control system obtains a locked state, so that the phase control system can control the By eliminating the need to charge the capacitor of the loop filter when starting operation, the phase lock pull-in time of the phase control system can be made much faster than in the conventional case.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a motor drive control device according to the present invention, FIG. 2 is a signal waveform diagram for explaining its operation, and FIG. 3 is a schematic configuration of a DRAW device to which the present invention can be applied. The route map shown in FIG. 4 is a block diagram showing a conventional motor-driven control bag/place. 11... Speed control system, 12-... Phase control system, 31.35... Mono multivibrator, 32.36... Low pass filter, 34...
...-m arithmetic circuit, 41... switch circuit.

Claims (1)

[Claims] A speed control system that locks the rotational speed of the motor to the target speed information based on detected speed information representing the rotational speed of the motor and target speed information representing the target value; and a speed control system that locks the rotational speed of the motor to the target speed information; and a phase control system that locks the rotational phase of the motor to the target phase information based on detected phase information representing the target value and target phase information representing the target value, the phase control system comprising: (a) the above-mentioned phase control system; Charge a capacitor of a loop filter with the phase error output of a phase comparison circuit that compares the detected phase information and the target phase information, and (b) supply a speed target voltage to the speed control system based on this charging voltage. (c) when the speed control system is in lock retraction operation, the supply point of the speed target voltage supplied from the phase control system to the speed control system is set to a stable point voltage when the speed control system is locked; Charge the capacitor with a corresponding voltage; (d) When the phase control system enters the lock retracting operation,
A motor drive control device characterized in that the voltage of the capacitor is switched from a voltage corresponding to the stable point voltage to a voltage based on the phase error output.