JPS62283459A - Recovery clock forming circuit for pcm signal - Google Patents

Abstract

PURPOSE:To attain excellent high speed search and special mode reproduction by detecting the frequency change of a PCM signal so as to move the recovered clock frequency band, thereby allowing a recovery clock frequency band to include a channel clock frequency. CONSTITUTION:If the frequency of a PCM signal reproduced by a head 1 by the reproduction of the special mode of a VTR or the high speed search of a digital audio tape recorder, the frequency change is detected by a channel clock frequency detection circuit 11. Then a control signal outputted from the circuit 11 is fed to a voltage variable oscillator VCO 6 to move the output frequency band of the VCO 6 thereby applying control to include the channel clock frequency in the recovered PCM signal. Thus, the high speed search, the VTR special mode reproduction are executed excellently.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Industrial Application Field) The present invention provides a VTR or rotary head type digital audio tape recorder that records image information, audio information, etc.
The present invention relates to a circuit that forms a clock signal for reproducing a CM signal.

To reproduce the PCM signal, a clock signal having a frequency twice that of the PCM signal is used.

(Prior art) When a PCM signal is recorded on a magnetic tape, for example, and the magnetic tape is scanned helically by a magnetic head disposed on a high-speed rotating cylinder to perform a high-speed search, or playback is performed in normal mode, trick playback, or fast forwarding. Alternatively, when monitoring is performed during rewinding, a ninth (21st) PLL (phase locked loop) circuit is used for good reproduction of the picture τ page.

This is because if the relative speed of the magnetic head (1) and magnetic tape (2) differs from that during normal playback, the frequency of the PCM signal from the head changes, so the frequency of the playback clock (i.e. channel clock) changes accordingly. frequency) is also attempted to be changed automatically.

The PLL circuit includes a phase comparator (3), a phase complement (award circuit)
4), limiter circuit (5), voltage variable frequency oscillator (
v c O) (6), and the phase comparator (3) receives the reproduced PCM signal from the head (1>) and the reproduced clock outputted from the vCO by negative feedback.

(Problem to be solved) In the case of a conventional PLL circuit, a limiter circuit (5) is used to prevent the reproduced clock from locking at double frequency, etc.
The operating range of CO(6) is limited to around the target frequency, as shown by the shaded range in FIG.

However, if the frequency of the PCM reproduction signal fluctuates beyond a certain level, it will fall outside the operating range of the co, and a reproduction clock with a frequency outside the range will be required. There was a problem in which the reproduction of PCM signal information became impossible.

(Structure) In the present invention, when the frequency of the PCM signal reproduced by the head changes due to high-speed search of a digital audio tape recorder or reproduction in a special mode of a VTR, this is detected by a channel clock forming circuit, and the VCO By supplying the control ff1l signal to the VCO, the frequency band of the reproduced clock output by the VCO is automatically shifted by an appropriate amount, and even if the PCM signal frequency changes, a corresponding reproduced clock is generated. .

(Functions and Effects) Even if the frequency of the PCM signal fluctuates, it is controlled to include the reproduction clock lock frequency, and high-speed search and special mode reproduction of the VTR can be performed satisfactorily.

<Example) FIG. 1 shows an example of a PLL circuit for PCM signals.

A head (1) is rotationally driven by a cylinder motor (7) to reproduce a PCM recording signal from a magnetic tape (2),
The reproduced PCM signal obtained from the head is supplied to the phase comparator (3) of the PLL circuit (8).

The V CO (6) outputs a reproduced clock for reproducing the PCM signal and supplies it to the terminal (9).As is well known, a part of the output is returned to the phase comparator (3) for phase compensation. A control signal with limited upper and lower limits is outputted via a circuit (4) and a limiter circuit (5), and is applied to an adder (10).

The adder (10) includes a channel clock forming circuit (11).
A band control signal <12) from <12> is also added at the same time and input to the voltage variable oscillator (VCO) (6), and the output frequency band of the VCO (6) is set by the external signal.

■Figure 2 shows the range in which CO should change its frequency.

The movement coordinate is fixed on the tape (2)), Vh is the movement vector of the head during normal playback, VL+ is the relative movement speed of the head to the tape, and the composite vector of Vl+ and The direction G of Tsuk (13) is the same.

When the tape runs at high speed, the relative speed between the head and the tape is t', and the resultant vector is V'.

During normal playback, the composite vector ■ is the signal reading speed a
However, when driving at high speed, the component of V' in the track direction is the signal reading speed.

If the tape speed at high speed is n times the speed, then V'-n
Since V, the rate of change in the signal reading speed is as follows.

('゛(n-L)V L cosθ = a-b
) 0 is 1 - rack angle V CO (6) requires a frequency variable ability of the degree indicated by - above.

As shown in the fourth (2I), V CO (6) is limited by the limiter circuit (5) in the central band (14) during normal playback by the band control signal from the channel clock forming circuit (11). The reproduction clock frequency is adjusted in the diagonally shaded range.When the tape is running at high speed, the reproduction clock is shifted to area II! >(16
) includes the changed channel clock frequency of the PCM signal.

No. 5I2I is another embodiment of the PLL circuit (8),
In place of the adder (10) in the first embodiment, a capacitor (17),
A variable capacitance circuit (20) having a resistor (18) and a Varicab diode (19) is provided.

Depending on the output band control signal from the channel clock forming circuit (11), the input/output characteristics of the VCO (6) are changed to normal playback (21) and high frequency (22) as shown in Figure 6.
, is determined in the low range (23).

Channel clock frequency 'dj1. The number detection circuit (11) detects the rate of change of the frequency r of the PCM signal reproduced by the head from the PCM signal frequency r0 during normal reproduction.

It outputs a band control signal (12) proportional to . - to form a signal of θ in FIG. is the inclination angle of the track when the tape is stopped, which is 6°22' in the case of a rotating head type digital audio recorder.
It is. θ is the trunk inclination angle when the tape is running,
6°22'59.5''.

■L' is the tape running speed, Vl+' is the head rotation speed, vt is the tape speed during normal playback (8.15 mm/sec), Vb is the head rotation speed during normal playback (π/sec),
V' is the actual velocity vector of the head relative to the tape, v' = Vh' + vpi.

Since the track direction component Vo' of V' is proportional to the frequency f of the reproduced PCM signal, r cx: Vo' = Vb' coS < θ-θQ
)-V t' cos θ During normal playback, ro work Vo-Vh
coS<0 (9v) 4F at VteQsθ), so f/f o = V o '/V.

Vh' (cos θ - θ - θ0) - - Vtcos θ Head speed V node V b ' is a signal from a pulse generator "G" installed close to the rotating shaft of the cylinder motor (7) to the head speed detection circuit (26). Also, the tape running speed is ``Vt'', which is the rotation signal of the capstan motor (Z4) and the tape speed detection circuit (Z4).
25>/\ It can be obtained by communicating.

FIG. 7 shows another embodiment of the 20-channel forming circuit (11), in which a single frequency is recorded at a fixed position on the track based on the track format of various signals recorded on one track of the magnetic tape. By utilizing this fact, in high-speed search operation, the reproduction RF at this predetermined value is
(By checking the frequency deviation of No. 3, it is possible to know the deviation of the channel clock frequency of the PCM reproduction signal.

The first gate circuit (30) reports the position at which this single frequency is reproduced based on the RF switch signal inputted to the terminal (35). Also, if this RF multiplied signal is a mixture of reproduction signals from two tracks, it is meaningless to detect that frequency, so it is necessary to extract the signal only during head-on-track. It is the second gate circuit (35) that generates the gate.The shapes of the signals of each part are shown in FIGS. 8a to 8f. When the RF multiplied signal is input to the AM detection circuit &'8 (27), the circuit produces output C, but when the head is on track, R
Since the F-fold signal amplitude expands, by comparing the detection output C with the output of an appropriate reference voltage source (28) using a voltage comparison circuit (29), a second gate d indicating an on-track state of 1g can be obtained. . That is, the overlapped portion of the output e of the first gate circuit (30) and the output d of the second gate circuit 2M (35) is an effective single frequency region, and the third
A gate signal f is generated by an AND gate (31).

Since the RF multiplied signal frequency at the position indicated by the third gate signal f has already been detected by the frequency/voltage conversion circuit (32), this signal is adjusted to the third gate signal r and the sample and hold circuit (33 ), the frequency deviation of the reproduced RF signal, that is, P C
A signal (12) representing the deviation of the channel frequency of the M signal is obtained.

It goes without saying that the configuration of each part of the present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the technical scope described in Patent No. 3+1.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, FIGS. 2 and 3 (2I is a vector diagram showing a situation where the frequency of the PCM signal changes, and FIG. 4 is a VCO diagram in the embodiment of FIG. 1.
The operation J (Fig. 5 is 71 of the embodiment of the pond of the present invention
6 is an explanatory diagram of the operation of the VCO in the embodiment of 5F16, FIG. 7 is a block diagram of the present invention in another embodiment of the PCM channel clock forming circuit, and FIGS. 8 a to f is a signal shape diagram of the channel clock forming circuit shown in FIG. 7, FIG. 9 is a conventional PLL circuit diagram, and FIG. (1)...Magnetic head (2)...Magnetic tape (3
)...Phase comparator (5)...Limiter circuit (
6)... Voltage variable frequency oscillator (VCQ) (8)...
PLL circuit (11)...channel clock formation circuit (12)...
・Bandwidth control signal

Claims (1)

[Claims] (1) A PCM signal recorded on a recording medium is reproduced by a head, and the reproduced PCM signal and the output of a voltage variable frequency oscillator (VCO) forming a reproduction clock of the PCM signal are In a clock forming circuit that compares signals using a phase comparator, feeds back the output signal from the phase comparator to a voltage variable frequency oscillator, and controls the frequency of the reproduced clock in accordance with the frequency change of the reproduced PCM signal, from normal reproduction to By switching to special reproduction, a signal corresponding to a change in the PCM signal frequency is formed in a channel clock frequency detection circuit, a control signal output from the detection circuit is supplied to the voltage variable oscillator, and the output frequency of the voltage variable oscillator is changed. 1. A reproduced clock generation circuit for a PCM signal, characterized in that the output range is controlled to include the channel clock frequency in the reproduced PCM signal by moving the band. (2) The channel clock frequency detection circuit is connected to the tape speed detection circuit and head speed detection circuit, receives signal inputs of tape speed Vt and head speed Vh, and supplies an output formed by the following equation to the voltage variable oscillator. The circuit according to claim 1. Vh'(cosθ-θ_0)-Vt' cosθVh
cos (θ - θ_0) - Vt cosθ However, θ_0 is the head trace angle when the tape is stopped (6°22' for a rotating head type audio tape recorder) θ is the track angle when the tape is running (6°22'59.5 ″
) Vt is the tape speed during normal playback (8.15 mm/sec)
Vh is the head speed during normal playback (πm/sec) (3) The signal from the phase comparator has its upper and lower limits limited by a limiter circuit, and is input to an adder together with the band control signal from the channel clock frequency detection circuit. 3. The circuit according to claim 1, wherein the sum signal is supplied to a voltage variable frequency oscillator. (4) The signal from the phase comparator limits the upper and lower limits by a limiter circuit, and inputs it to the oscillation variable capacitance circuit together with the control circuit from the channel clock frequency detection circuit.
3. A circuit as claimed in claim 1 or claim 2, supplying the output signal to a voltage variable frequency oscillator.