JPH066621A - Deflection circuit - Google Patents

Abstract

PURPOSE:To prevent moving of a display pattern in the horizontal direction by correcting a forward and a backward deflection timing so as to make a relation of phase between a video signal and a deflection signal constant based on a horizontal synchronizing signal. CONSTITUTION:The circuit is provided with a 1st phase control circuit 22 controlling a forward path deflection timing based on a horizontal synchronizing signal HD so as to keep the relation of a phase of a video signal SV forming a forward display picture and a phase of a forward deflection signal constant and with a 2nd phase control circuit 24 controlling a backward path deflection timing based on the horizontal synchronizing signal HD so as to keep the relation of a phase of a video signal SV forming a return display picture and a phase of a backward deflection signal constant and keeping the display picture of the return path to be constant with respect to the display picture of the forward path. Then the 1st and 2nd phase control circuits 22, 24 control the forward and backward deflection timing based on the horizontal synchronizing signal HD to keep the phase of the video signal SV and the phase of the deflection signal constant.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial field of the related art (FIG. 8) Problem to be solved by the invention (FIG. 8) Means for solving the problem (FIGS. 1, 5 and 6) Action (FIGS. 1, 5 and 6) ) Example (1) Overall configuration (Fig. 1) (2) Horizontal deflection drive circuit (Figs. 2 to 4) (3) Deflection control circuit (Figs. 5 to 7) (4) Confirmation of operation (5) Example Effects (6) Other Examples Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a deflection circuit, and is particularly suitable for application to a horizontal deflection circuit for bidirectional deflection.

[0003]

2. Description of the Related Art Conventionally, in a deflection circuit of this type, a horizontal deflection coil is formed by using a drive signal whose signal level changes symmetrically before and after a predetermined time point, such as a sine wave signal. A driving deflection circuit (hereinafter referred to as a bidirectional deflection deflection circuit) has been proposed (US Pat. No. 4,6,6).
72,449).

According to this bidirectional deflection circuit, scanning from left to right of the screen (hereinafter referred to as forward scanning) and conversely, scanning from right to left of the screen (hereinafter referred to as backward scanning) are both performed. A display image can be formed and the deflection frequency can be reduced by half. Further, since it is possible to prevent a sharp change in the deflection current such as a saw-tooth wave signal, it is possible to reduce unnecessary radiation and the like, and it is possible to reduce the load on the deflection circuit element.

Particularly, if the deflection circuit is formed by a resonance circuit and the deflection coil is driven by a sine wave signal as shown in FIG.
(A) and (B)), the power required for deflection can be reduced with a simple configuration (Japanese Patent Laid-Open No. 3-72783).

[0006]

By the way, in this type of bidirectional deflection circuit, there is a problem that the AFC circuit applied to the raster scanning horizontal deflection circuit cannot be applied.

That is, in a conventional horizontal deflection circuit by raster scanning, after generating a sawtooth wave signal from a flyback pulse, a phase comparator obtains a result of phase comparison between the sawtooth wave signal and a horizontal synchronizing signal. The phase comparison result is fed back to the horizontal oscillation circuit.

Thus, in the conventional AFC circuit,
A control voltage for controlling the horizontal oscillation frequency is generated by the phase comparator, and the horizontal deflection circuit is driven so as to follow the frequency change of the horizontal synchronizing signal.

Therefore, since the control voltage changes in accordance with the frequency change of the horizontal synchronizing signal, eventually, in the AFC circuit of this type, when the frequency of the horizontal synchronizing signal changes, the control voltage is changed. A stationary phase error occurs in the phase comparator.

This steady phase error has a problem that it appears as a positional shift of the display image in the horizontal direction. In this case, the horizontal image center must be readjusted each time the horizontal synchronizing frequency shifts.

Further, this steady phase error may change when the temperature changes, and in this case, the display image is displaced in the horizontal direction following the change in ambient temperature.

Particularly in a bidirectional deflection circuit, when the display image is displayed in the reverse direction on the forward and backward paths due to this steady phase error, the display image is displayed as a double image, and when the deviation is small. Has a problem that the resolution deteriorates.

The present invention has been made in consideration of the above points, and a deflection circuit that can prevent horizontal movement of a display image even when applied to bidirectional deflection and the horizontal synchronizing frequency changes. It is a proposal.

[0014]

In order to solve such a problem, in the first aspect of the present invention, the deflection currents I _L3 and I _L4 for the forward and backward passes are horizontally _adjusted so that a display image is formed by the deflection of the forward and backward passes. In the bidirectional deflection circuit 18 that supplies the deflection coil L, the timing of the outward deflection is controlled based on the horizontal synchronizing signal HD, and the video signal SV forming the outward display image and the outward deflection phase are constant. The first phase control circuit 22 which holds the phase relationship of the following, and the timing of the backward deflection on the basis of the horizontal synchronizing signal HD is controlled, and the video signal SV forming the display image on the backward path and the backward deflection phase are controlled. A second phase control circuit 24 is provided which holds a fixed relationship and holds the display image on the return path so as to match the display image on the return path.

Further, in the second invention, the first and second
Of the phase control circuits 22 and 24 of the horizontal deflection signal L with respect to the terminal voltage V _L of the horizontal deflection coil _L for a predetermined period T.
H integration is performed to obtain an integration result V6, and sawtooth wave signals S1 and S2 generated with reference to the horizontal synchronizing signal HD and the integration result V
Based on the result of comparison with 6, the timing of starting the deflection on the outward path and the return path is controlled.

Further, in the third invention, the first resonant circuit for supplying the outward deflection current I _L3 and the return deflection current I _L3.
A second resonance circuit for supplying _L4 is provided, and the first and second phase control circuits 22 and 24 switch the first and second resonance circuits and connect them to the horizontal deflection coil L for forward and return paths. The deflection currents I _L3 and I _L4 are supplied to the horizontal deflection coil L,
The timing of switching the first and second resonance circuits is switched to control the timing of deflection in the forward path and the return path.

Further, in the fourth invention, the first resonance circuit is formed by a series resonance circuit of the first switch circuit 30, the resonance capacitor C, the horizontal deflection coil L and the first S-shaped correction capacitor CS1, and The second resonance circuit is formed by a series resonance circuit of the second switch circuit 32, the resonance capacitor C, the horizontal deflection coil L, and the second S-shaped correction capacitor CS2, and the first and second phase control circuits 22 and 24 are provided. Is
The first and second switch circuits 30 and 32 are complementarily switched, and the switching timing is controlled to control the forward and backward deflection timings.

[0018]

In the first and second phase control circuits 22 and 24,
Even if the frequency of the horizontal synchronizing signal HD changes, if the deflection timings of the forward and backward paths are controlled based on the horizontal synchronizing signal HD and the video signal SV and the deflection phase are held in a constant phase relationship, The display image can be held at a predetermined position.

In the first and second phase control circuits 22 and 24, the terminal voltage V _L of the horizontal deflection coil L is taken in for a predetermined period TH with the horizontal synchronizing signal HD as a reference to obtain an integration result V6 and a sawtooth wave. Signals S1 and S2 and integration result V6
It is possible to effectively avoid the occurrence of a steady phase error by selecting the period TH by controlling the timing of starting the deflection on the outward path and the return path based on the comparison result with.

At this time, the first and second phase control circuits 22
And 24, the timings for switching the first and second resonance circuits are switched to control the timings of the forward and backward deflections, so that it can be easily applied to the bidirectional deflection circuit.

The respective resonance circuits are connected to the first switch circuit 3
0, resonance capacitor C, horizontal deflection coil L and first S
A series resonance circuit of the letter correction capacitor CS1, a second switch circuit 32, a resonance capacitor C, a horizontal deflection coil L,
It is formed by a series resonance circuit of the second S-shaped correction capacitor CS2, and the first and second phase control circuits 22 and 24 complementarily control switching of the first and second switch circuits 30 and 32. Therefore, the deterioration of linearity can be prevented and the deflection current can be efficiently supplied.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Overall Structure In FIG. 1, reference numeral 1 denotes a display device as a whole, and a bidirectional deflection method is applied to drive a cathode ray tube 2 to display a video signal SV.

That is, in the display device 1, the video signal SV is supplied to the video signal input circuit 3, where predetermined signal processing is executed and then converted into a luminance signal and a color difference signal.

Analog digital conversion circuit (A / D) 4
Inputs a luminance signal and a color difference signal via a predetermined filter circuit or the like (not shown), converts them into digital signals, and outputs them.

The delay circuit 6 selectively inputs the output signals of the odd lines with respect to the output signals of the analog digital conversion circuit 4, delays them by one horizontal scanning period, and outputs them.

On the other hand, the sequence inverting circuit 8 is formed of a memory circuit and controls the write / read address to selectively input the output signal of the even digital line with respect to the output signal of the analog digital conversion circuit 4. After that, output is performed in the reverse order of input.

As a result, in the display device 1, the delay circuit 6 and the sequence inverting circuit 8 respectively generate the video signals necessary for the forward and backward scanning.

The video signal processing circuit 10 sequentially takes in the output signals of the delay circuit 6 and the sequence inverting circuit 8, respectively, converts them into analog signals, and then outputs them to the cathode ray tube 2.

As a result, in the display device 1, after converting the video signal SV into a video signal necessary for bidirectional deflection,
The cathode ray tube 2 is driven based on this video signal.

The sync separation circuit 12 separates and outputs the horizontal sync signal HD and the vertical sync signal VD from the video signal SV.

The vertical deflection circuit 14 receives the vertical synchronizing signal V
A drive signal whose signal level changes stepwise with reference to D is generated, and the vertical deflection coil 1 is used with this drive signal as a reference.
Drive 6

Thus, in the display device 1, the vertical deflection magnetic field corresponding to the bidirectional deflection is formed to drive the cathode ray tube 2.

The horizontal deflection circuit 18 gives a horizontal synchronizing signal HD to a reference signal generating circuit 20 having a PLL circuit structure, and generates a predetermined reference signal here.

Further, the horizontal deflection circuit 18 outputs this reference signal to the deflection control circuits 22 and 24, where the deflection start timings of the forward path and the backward path are generated, respectively, and the timing signals obtained as a result are driven by the horizontal deflection drive. Output to the circuit 26.

In the horizontal deflection drive circuit 26, the horizontal deflection coil 30 is driven with the timing signal and the reference signal generated by the reference signal generation circuit 20 as a reference, and the bidirectional deflection method is applied to the horizontal deflection coil 30. Deflection coil 3
Drive 0.

At this time, in the horizontal deflection circuit 18, the deflection control circuits 22 and 24 are assigned to the forward path and the backward path, respectively, and the deflection start timings of the forward path and the backward path are controlled here to synchronize with the horizontal synchronizing signal HD. In addition to forming a display image, the display image is prevented from being deteriorated in quality.

(2) Horizontal Deflection Drive Circuit As shown in FIG. 2, the horizontal deflection drive circuit 26 switches the field effect transistors Q1 and Q2 to the off state at a predetermined timing, whereby the deflection start timings of the forward path and the backward path are started. Is controlled to supply the deflection current I _L to the horizontal deflection coil L.

That is, as shown in FIG. 3, in the horizontal deflection drive circuit 26, the field effect transistor Q1 is used.
And the diode D1 form the first switch circuit 30, whereas the field effect transistor Q2 and the diode D2 form the second switch circuit 32.

As a result, the horizontal deflection drive circuit 26
The first switch circuit 30 is switched to the ON state and the resonance capacitor C, the deflection coil L, and the first S-shaped correction capacitor CS1 form a first resonance circuit, while the second switch circuit 30 is opposite to the second resonance circuit. The switch circuit 32 is turned on, and the resonance capacitor C, the deflection coil L, and the second S-shaped correction capacitor CS2 form a second resonance circuit.

As a result, in each resonance circuit, if the switch circuit 30 or 32 is switched to the ON state, a sinusoidal current will flow continuously if there is no loss in the circuit.

As shown in FIG. 4, the horizontal deflection drive circuit 2
Reference numeral 6 denotes an electric field when the deflection voltage _VL falls and rises to a predetermined voltage with reference to the terminal voltage (hereinafter referred to as deflection voltage) _{VL of} the deflection coil and the horizontal synchronizing signal HD which change in a sinusoidal manner. The effect transistors Q1 and Q2 are switched off.

As a result, the horizontal deflection drive circuit 26
The switch circuits 30 and 32 are alternately turned on at a predetermined timing to supply the deflection coil L with deflection currents I _L3 and I _L4 on the forward path and the backward path.

Further, the horizontal deflection drive circuit 26 sets the resonance frequency of each resonance circuit to a frequency lower than the horizontal scanning frequency, and switches the switch circuits 30 and 32 at a cycle shorter than a half cycle of the resonance frequency. Thus, the deterioration of the linearity can be prevented and the deflection can be efficiently performed.

That is, the deflection coil L
8 is driven, the deflection current I indicated by hatching in FIG.
During the period near the peak of _L , the linearity is deteriorated, so that in this type of deflection circuit, the deflection coil must be driven so as to overscan, and the deflection current I _L is wasted during this hatched period. Was being supplied.

Therefore, in this embodiment, when the deflection voltage V _L passes through the peak and falls to a predetermined voltage at time t1 (FIGS. 4A and 4B), the field effect transistor Q1 is turned off. (FIG. 4 (E)).

At this time, in the horizontal deflection drive circuit 26, the S-shaped correction capacitor CS2 causes the outward deflection current I _L3.
When the field effect transistor Q1 is switched to the off state because of being charged by, the deflection voltage V _L suddenly falls and the diode D2 is immediately switched to the on state (FIG. 4 (F)).

As a result, in the horizontal deflection drive circuit 26, the deflection voltage V _L is rapidly lowered by the amount shown by the diagonal lines in FIG. 8, and the deflection coil L1 is connected from the first resonance circuit to the second resonance circuit. Switch.

In this state, the field effect transistor Q2 is switched on during the period until the deflection voltage V _L passes the peak, and then the deflection voltage V _L passes the peak and rises to a predetermined voltage at time t2. Then, the horizontal deflection drive circuit 26 switches the field effect transistor Q2 to the off state (FIG. 4 (G)).

At this time, in the horizontal deflection drive circuit 26, the S-shaped correction capacitor CS1 is used for the return deflection current I _L4.
When the field-effect transistor Q2 is switched to the off state because it is charged by, the deflection voltage V _L rises rapidly and the diode D1 is immediately switched to the on state (FIG. 4 (D)).

As a result, in the horizontal deflection drive circuit 26, the deflection voltage V _L is rapidly raised by the amount shown by the diagonal lines in FIG. 8 to connect the deflection coil L1 from the second resonance circuit to the first resonance circuit. After the switching, the field effect transistor Q1 is switched to the ON state until the deflection voltage V _L passes the peak.

As a result, in the deflection current I _L , like the deflection voltage V _L , a portion having poor linearity can be removed,
As a result, the horizontal deflection drive circuit 26 can effectively prevent the deterioration of linearity and drive the deflection coil L efficiently.

Further, in the horizontal deflection drive circuit 26, the field effect transistors Q3 and Q4 are alternately turned on by the drive circuit 34 on the basis of the deflection voltage V _L , thereby forming a predetermined drive power source Va ( FIG. 4C).

Further, the horizontal deflection drive circuit 26 supplies the driving power source Va to the connection midpoint of the resonance capacitor C and the deflection coil L via the series circuit of the capacitor C3 and the coil L1, thereby driving the deflection coil L1. Supply the necessary power to.

The pin distortion correction circuit 36 generates a parabolic signal whose signal level changes parabolically in the positive and negative directions in synchronization with the vertical synchronizing signal, and the parabolic signal causes the terminals of the S-shaped correction capacitors CS1 and CS2 to be generated. Modulate the voltage. As a result, the horizontal deflection drive circuit 26 corrects the display screen in an S shape and also corrects the pin distortion of the display screen.

Along with the correction of this pin distortion, the distortion correction circuit 38
Modulates the power supply voltage of the power supply VB so as to change the voltage following the parabolic signal and outputs the modulated power supply voltage to the field effect transistor Q3.
Is designed to prevent the deviation of the forward and backward display images, which occurs when the pin distortion is corrected by this type of horizontal deflection circuit.

Here, the horizontal deflection drive circuit 26 inputs the output signals S7 and S8 of the deflection control circuits 22 and 24 to the field effect transistors Q1 and Q2 via the horizontal drive circuits 40 and 42, respectively. Type transistors Q1 and Q2 are on / off controlled.

As a result, the horizontal deflection drive circuit 26
The deflection start timings of the forward path and the backward path are controlled based on the deflection voltage V _L and the horizontal synchronization signal to form a display image in synchronization with the horizontal synchronization signal and prevent deterioration of the display image in advance.

(3) Deflection Control Circuit As shown in FIG. 5, the deflection control circuit 22 inputs the deflection voltage V _L and the horizontal synchronizing signal HD to the phase comparison circuit 44A,
Here, the timing for starting the deflection on the return path is detected with reference to the horizontal synchronizing signal HD.

Further, the deflection control circuit 22 converts the phase comparison result into a DC voltage by the subsequent filter circuit (F) 46A, and then the predetermined sawtooth wave signal S by the comparison circuit (COM) 48A.
The result of comparison with 1 is obtained, and the timing for starting the deflection on the return path is set based on the horizontal synchronization signal HD.

Here, the sawtooth wave signal S1 is based on the output signal of the reference signal generation circuit 20 and the sawtooth wave generation circuit 49.
It is generated by A.

The horizontal oscillating circuit 50A has a field effect transistor Q based on the output signal of the reference signal generating circuit 20.
The timing for switching 1 to the ON state is generated.

The waveform generation circuit 52A uses the timing of the deflection start of the return path set by the comparison circuit 48A and the timing of switching on the field effect transistor Q1 generated by the horizontal oscillation circuit 50A as a reference. The drive signal S7 for the effect transistor Q1 is generated, and the drive signal S7 is output via the horizontal drive circuit 40.

As a result, the deflection control circuit 22 includes an APC (automatic phase control circuit) in the phase comparison circuit 44A, the filter circuit 46A, the comparison circuit 48A, and the horizontal oscillation circuit 50A.
r) circuit is formed so that the phase relationship between the backward deflection and the video signal is held at a constant value with reference to the horizontal synchronizing signal HD.

[0065] In contrast deflection control circuit 24 inputs the deflection voltage V _L and the horizontal synchronizing signal HD to a phase comparator circuit 46B, the deflection voltage V _L and the horizontal synchronizing signal at this time is a phase comparator circuit 46A in opposite polarity By inputting HD, the deflection start timing in the outward path is detected with reference to the horizontal synchronizing signal HD.

Further, the deflection control circuit 22 converts the phase comparison result into a DC voltage by the subsequent filter circuit (F) 46B and then outputs it to the comparison circuit (COM) 48B. At this time, in the comparison circuit 48B, the comparison result is obtained with reference to the sawtooth wave signal S1 and the sawtooth wave signal S2 whose phase is 180 degrees different from each other, whereby the deflection start timing of the forward path is determined with reference to the horizontal synchronizing signal HD. Set.

Here, the sawtooth wave signal S2 is based on the output signal of the reference signal generation circuit 20 and the sawtooth wave generation circuit 49.
Generated in B.

The horizontal oscillating circuit 50B has a field effect transistor Q based on the output signal of the reference signal generating circuit 20.
The timing to switch 2 to the ON state is generated.

The waveform generating circuit 52B uses the forward deflection start timing set by the comparison circuit 48B and the electric field effect transistor Q2 generated by the horizontal oscillation circuit 50B to switch to the ON state as a reference. The drive signal S8 for the effect transistor Q2 is generated, and the drive signal S8 is output via the horizontal drive circuit 42.

Accordingly, in the horizontal deflection circuit 18,
The deflection start timings of the forward path and the backward path are controlled by the individual deflection control circuits 22 and 24, respectively, to form a display image in synchronization with the horizontal synchronizing signal, and at this time, display images of the forward path and the backward path are at the same position. The image quality of the displayed image can be prevented in advance.

In addition to this, the deflection control circuit 24 is similar to the deflection control circuit 22 in that the phase comparison circuit 44B, the filter circuit 46B, the comparison circuit 48B, and the horizontal oscillation circuit 50B are APs.
The C circuit is formed so that the phase relationship between the outward deflection and the video signal is held at a constant value based on the horizontal synchronizing signal HD.

As a result, the deflection control circuits 22 and 24 are
The forward and backward display images are formed so that the image center of the display image becomes the center of the display screen so that the display position does not change even when the frequency of the horizontal synchronizing signal HD changes.

Specifically, as shown in FIG. 6, the phase comparison circuit 44A connects the transistors Q6 and Q7 and the transistors Q8 and Q9 connected in series to the current source 60 of the current i ₀ via the transistor Q10. The horizontal synchronizing signal HD is input to the transistor Q10.

Further, as shown in FIG. 7, the phase comparison circuit 44
A inputs the deflection voltage V _L (FIG. 7A) to the transistor Q9 via a voltage dividing circuit and an integrating circuit (not shown),
The phase comparison result is output from the collector side of the transistor Q9.

At this time, the phase comparison circuit 44A inverts and inputs the horizontal synchronizing signal HD (see FIG. 7).
(B)) As a result, the operating state is raised for a predetermined period TH before and after this point of time based on the time point of the deflection start of the forward path and the backward path determined by the horizontal synchronizing signal HD.

As a result, in the phase comparator circuit 44A, during this period TH, the signal level rises in synchronization with the horizontal synchronizing signal HD, and then the polarity is inverted at the fall of the deflection voltage V _L , and subsequently. The phase comparison result S4 in which the signal level rises in synchronization with the horizontal synchronizing signal HD can be obtained (FIG. 7 (C)).

On the other hand, the filter circuit 46A is formed by a lag lead filter circuit in which a resistor 62 and a capacitor 64 are connected in series and a capacitor 66 is grounded in parallel, and the phase comparison result S4 is input via a resistor 68. To do.

As a result, the filter circuit 46A integrates and outputs the phase comparison result S4, and when the rising timing of the deflection voltage V _L changes with respect to the middle point of the period TH when the signal level of the horizontal synchronizing signal HD rises. , The detection voltage V in which the overall DC level changes according to this change amount
6 is obtained (FIG. 7 (C)).

That is, in this case, since the deflection voltage V _L rises at a time earlier than the middle time of the period TH,
In the phase comparison result S4, the period in which the signal level rises is shorter, which reduces the DC level by the value ΔV in the integration result.

As a result, the deflection control circuit 22 drives the horizontal deflection drive circuit 26 on the basis of this detection result to form a feedback loop as a whole, and the field effect transistor is set so that this value ΔV becomes 0 [V]. Drive Q1.

That is, in the filter circuit 46A,
This detection voltage V6 is given to the comparison circuit 48A, and the comparison result with the sawtooth wave signal S1 is obtained here (FIGS. 7D and 7E), whereby the timing for switching the field effect transistor Q1 to the OFF state is set. To do.

At this time, in the deflection control circuit 22, the voltage of the detection voltage V6 is corrected by the resistor 70 and the reference power source 72, and thereby the display position of the display screen formed in the outward path is held at a predetermined position.

As a result, the current value of the current source 60 is i ₀ , the currents of the capacitors 64 and 66 are i ₁ and i ₂ , respectively.
When the current of the resistor 70 is i ₃ , when the phase comparator 44A operates in the saturation region,

[Equation 1] And the variation ΔV of the detection voltage V6 is

[Equation 2] Can be expressed as Where C ₆₄ , C ₆₆ , R ₆₂ and R ₇₀
Represents the values of the capacitors 64 and 66 and the resistors 62 and 70.

As a result, the operation period TH of the phase comparison circuit 44A, the values of the capacitors 64 and 66, the resistors 62 and 70 can be selected, and the change amount ΔV can be detected with a predetermined detection sensitivity.

Thus, in the deflection control circuit 22, a feedback loop is formed so that the amount of change ΔV becomes 0 [V], and the phase comparison circuit 44A holds the steady phase error so that it does not occur. The phase relationship between the backward deflection and the video signal is held at a constant value based on the horizontal synchronizing signal HD.

Further, in this embodiment, the reference power source 72 is formed by a latch circuit that latches the control data output from the system control circuit and a digital analog conversion circuit that converts the output data of this latch circuit into an analog signal. As a result, the system control circuit can switch control data to adjust the voltage of the reference power supply 72.

Accordingly, in the deflection control circuit 22,
The position of the image center can be automatically adjusted with respect to the display image on the outward path.

On the other hand, in the deflection control circuit 24 which controls the timing of the outward path, the horizontal synchronizing signal HD is similarly generated.
Is used as a reference to process the deflection voltage V _L , thereby setting the timing for switching the field effect transistor Q2 to the off state.

At this time, in the deflection control circuit 24, similarly to the deflection control circuit 22, a feedback loop is formed so that the change amount ΔV becomes 0 [V], and a steady phase error is generated in the phase comparison circuit 44B. The phase relationship between the outward deflection and the video signal is held at a constant value based on the horizontal synchronizing signal HD.

Further, in the deflection control circuit 24, the control data for adjusting the image center is updated so that the adjustment of the image center of the deflection control circuit 22 can be followed to adjust the image center of the forward display image. Has been done. Thereby, in the display device 1, the control data can be set to a predetermined value to automatically adjust the image center.

(4) Confirmation of Operation In this way, the deflection control circuit 2 dedicated to the forward path and the backward path is used.
The control of providing 2 and 24 to synchronize with the horizontal synchronizing signal HD and prevent the duplicated display of the display image is nothing but the control of changing the duty ratio of the periodic function synchronized with the horizontal synchronizing signal HD.

If a general rectangular wave periodic function f (t) is expressed by a Fourier series, it can be expressed by the following equation.

[0093]

[Equation 3]

[Equation 4]

[Equation 5]

[Equation 6]

Here, τ / T represents the duty ratio, A
Represents the amplitude, and when the duty ratio is 50%,

[Equation 7] By being represented by, the following relational expression is established.

[0095]

[Equation 8]

Considering n in the equations (4) to (6), the value of n changes in bidirectional deflection according to the drive waveform of the deflection circuit. That is, when driving with a sine wave, set n = 1, and when driving with a rectangular wave, n = 1, 3,
5 ... (Odd number), which can be expressed by the following equation.

[0097]

[Equation 9]

On the other hand, in the deflection current I _L flowing through the horizontal deflection coil L,

[Equation 10] By (3), (8), (9), (1
By substituting equation (0) and setting τ = π, the following relational equation can be obtained.

[0099]

[Equation 11]

Here, the first term on the right side represented by 0.5 · a ₀ t represents a DC component flowing in the deflection coil L, and can be easily removed by a coupling capacitor.

On the other hand, the second term on the right-hand side that follows is an even function, and therefore exhibits excellent symmetry on the forward and backward paths,
It can be seen that the display images can be prevented from being inconsistent on the outward path and the return path.

That is, when the horizontal deflection coil L is driven under the condition of the duty ratio of 50%, the display image can be formed in synchronization with the horizontal synchronizing signal and the display image can be prevented from being inconsistent in the forward and backward passes. I understand.

However, in the actual bidirectional deflection, the deflection current slightly changes in the forward and return paths due to variations in electronic components used for the forward and return deflections, non-linear operation of circuit components, and the like. As a result, in the display image, the display position and the like change in the forward and backward passes.

Therefore, the case where the phase of the periodic function f (t) is changed from the duty ratio of 50% will be considered.

In this case, in the equation (11), by adding the term a _{n in} the equation (3), it is a problem how the term a _n changes with respect to the change of the duty ratio. become.

That is, ωτ is

[Equation 12] Therefore, a _n in the equation (3) can be expressed by the following equation from the equation (5).

[0107]

[Equation 13]

In the equation (13), since positive and negative values are taken from the value 0 centering on κ = 0.5, a unique deflection control circuit is provided for the forward path and the backward path as in this embodiment, and the duty ratio is set. By variably controlling, even if the symmetrical control of the deflection current is disturbed due to variations in circuit components, this can be corrected.

On the other hand, when the horizontal synchronizing frequency or the like changes, the entire horizontal deflection circuit 18 operates in synchronization with the video signal within the lock range of the reference signal generating circuit 20.

Therefore, the period T of the horizontal synchronizing signal HD is the period K.
When T (for example, K is about 0.9 to 1.1) is changed, a feedback loop is formed as a whole so that the outward and backward deflections start at an intermediate point during the period TH when the horizontal synchronizing signal HD rises. .

As a result, even when the horizontal synchronizing frequency changes, it is possible to prevent the occurrence of a steady phase error with respect to the change of the horizontal synchronizing frequency, whereby the forward and backward display images can be displayed at correct display positions. .

Further, not only when the horizontal synchronizing frequency changes but also when the temperature of the entire horizontal deflection circuit changes, the forward and backward display images can be displayed at the correct display positions.

(5) Effects of the Embodiments According to the above configuration, the deflection of the forward path and the return path respectively
By controlling the timing of the forward and backward deflections so that the phase relationship between the video signal and the deflection becomes a constant value based on the horizontal synchronization signal, it is possible to prevent the occurrence of steady phase error in the phase comparison circuit. As a result, even when the frequency of the horizontal synchronizing signal changes, the horizontal movement of the display image can be prevented.

(6) Other Embodiments In the above-described embodiments, the case where the forward and backward deflections are switched in a cycle shorter than 1/2 cycle of the resonance frequency has been described, but the present invention is not limited to this. For example, a predetermined rest period may be provided to switch the deflection between the forward pass and the return pass, and at this time, the length of the rest period may be controlled to prevent inconsistencies in display images.

Further, in the above-described embodiment, the field effect transistors Q1 and Q2 are switched to the OFF state, so that the two resonance circuits are alternately connected and the forward and backward deflection currents are supplied to the horizontal deflection coil L. Although the case has been described, the present invention is not limited to this.
It can be widely applied to the bidirectional deflection circuit disclosed in Japanese Patent No. 0369.

[0116]

As described above, according to the present invention, the forward and backward deflection timings are corrected so that the phase relationship between the video signal and the deflection becomes a constant value based on the horizontal synchronizing signal. Even when the frequency of the horizontal synchronizing signal changes, the occurrence of a stationary phase error can be prevented in advance, and thus the horizontal movement of the display image can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the horizontal deflection drive circuit.

FIG. 3 is a connection diagram for explaining the operation.

FIG. 4 is a signal waveform diagram for explaining the operation.

FIG. 5 is a block diagram showing a deflection control circuit.

FIG. 6 is a connection diagram showing a specific configuration thereof.

FIG. 7 is a signal waveform diagram for explaining the operation.

FIG. 8 is a signal waveform diagram for explaining bidirectional deflection.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Display device, 18 ... Horizontal deflection circuit, 20 ... Reference signal generation circuit, 22, 24 ... Deflection control circuit, 26 ... Horizontal deflection drive circuit, 44A, 44B ... Phase comparison circuit, 46A, 46B ... ... Filter circuit, 48A, 48B
…… Comparison circuit, C to CS2 …… Capacitor, L …… Horizontal deflection coil, Q1 to Q10 …… Transistor.

Claims (4)

[Claims] 1. A bidirectional deflection circuit for supplying a deflection current for the forward path and a return path to a horizontal deflection coil so that a display image is formed by the deflection of the forward path and the backward path, respectively. For controlling the deflection timing of the forward path and holding the video signal forming the display image of the forward path and the phase of the forward path deflection in a constant phase relationship.
And a phase control circuit for controlling the deflection timing of the return path on the basis of the horizontal synchronizing signal, and holding a constant relationship between the video signal forming the display image of the return path and the phase of the deflection of the return path, And a second phase control circuit that holds the display image on the return path so that the display image on the return path matches the display image on the return path. 2. The first and second phase control circuits take in a terminal voltage of the horizontal deflection coil for a predetermined period with the horizontal synchronizing signal as a reference to obtain an integration result, and with the horizontal synchronizing signal as a reference. The deflection circuit according to claim 1, wherein the deflection start timing of the forward path and the backward path is controlled based on a comparison result between the generated sawtooth wave signal and the integration result. 3. A first resonance circuit which supplies the deflection current of the forward path, and a second resonance circuit which supplies the deflection current of the return path, wherein the first and second phase control circuits include: The first and second resonance circuits are switched to be connected to the horizontal deflection coil to supply the forward and backward deflection currents to the horizontal deflection coil, and the timing for switching the first and second resonance circuits is switched. 3. The deflection circuit according to claim 1, wherein the deflection timing of the forward path and the return path is controlled. 4. The first resonance circuit comprises a first switch circuit, a resonance capacitor, the horizontal deflection coil and a first S.
The second resonance circuit is formed by a series resonance circuit of a second correction circuit, the resonance capacitor, the horizontal deflection coil, and a second S-shape correction capacitor. The first and second phase control circuits include the first and second phase control circuits.
4. The deflection circuit according to claim 1, wherein the switch circuit is switched complementarily and the switching timing is controlled to control the deflection timing of the forward and return paths. .