JPH066620Y2 - Digital tuning circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital tuning circuit.

[Prior art and its problems]

In recent years, a small-sized television receiver using a liquid crystal display panel for a display unit has been put into practical use. This type of conventional television receiver is generally provided with an auto-tuning device so that the tuning operation is automatically performed by operating an up key or a down key for tuning. Then, there is a voltage tuning method as one of the auto tuning methods. In this voltage tuning method, the tuning voltage applied to the tuner is sequentially changed, and the channel is generally detected by the change of the AFT signal and the synchronizing signal at that time. As a method of scanning the tuning voltage, either up / down the counter and D / A convert the counter output, or output a PWM (pulse width modulation) signal and demodulate it. I am taking it.

However, in the above voltage tuning method, at the moment when the output of the tuning counter changes from all "1" to all "0",
On the contrary, at the moment when all “0” changes to all “1”, the voltage applied to the tuner changes abruptly, so that the AFT signal changes irregularly. Therefore, the desired channel cannot be fixed and the user may go to the previous channel or the search may take a long time. For example, when the channel is increased, it is set to 1 → 3 → 12 channels, and when it is further increased, it is set to return to 1 channel, but it does not easily reach 1 channel or jumps to 1 channel It becomes 3 channels. The same phenomenon occurs when the channel is downed.

[Purpose of device]

The present invention has been made in view of the above points, and a digital tuning capable of reliably selecting and designating a desired channel even in the vicinity of both ends of a predetermined frequency region where the tuning voltage applied to the tuner changes rapidly. The purpose is to provide a circuit.

[Key points of device]

The present invention detects the reception frequency by an up / down key, a circulation type counting means for counting up / down according to the operation of the up / down key, and a tuning operation by converting the count value of the counting means into a voltage value. Tuning means, means for outputting a maximum value signal indicating a predetermined maximum value of the counting means, means for outputting a minimum value signal indicating a predetermined minimum value of the counting means, and the counting means up-counts. Is set by the maximum value signal and reset by the minimum value signal, and when the counting means is down-counting, it is set by the minimum value signal and set by the maximum value signal. Depending on the set resetting means to be in the reset state and the set time signal of the set resetting means. A tuning means for stopping the reception frequency detection operation of the tuning means, and a cancellation means for canceling the stop of the reception frequency detection operation of the tuning means by a reset signal of the set reset means. It is a thing.

[Example of device]

 An embodiment of the present invention will be described below with reference to the drawings.

First, the external structure of the present invention will be described with reference to FIG. In FIG. 1, reference numeral 11 denotes a case, and a video display section 12, a channel display section 13, and a volume display section 14 are provided on the front surface thereof.
Is provided. The video display unit 12, the channel display unit 13, and the volume display unit 14 are integrally formed on, for example, one display panel 15, but are separately displayed by a display window formed on the front surface of the case 11. It has become so. Then, on the channel display section 13, numerical values indicating the VHF and UHF channels are displayed on both sides of the case 11 by printing or the like. Further, on the front surface of the case 11, an up key 16a and a down key 16b for tuning are provided, and an up key 17a and a down key 17b for volume adjustment are provided. Further, the case 11 is provided with an auto / manual switch 18, a VHF / UHF switch 19, and a power switch 20, and a rod antenna 21 is provided above the case 11.

Next, the configuration of the electronic circuit provided in the case 11 will be described with reference to FIG. The radio wave received by the antenna 21 is supplied to the electronic tuning tuner 22. The electronic tuning tuner 22 selects a desired radio wave from the received radio waves, converts it into an intermediate frequency A, and outputs it to the television linear circuit 23. The television linear circuit 23 is composed of an intermediate frequency amplification circuit, a video detection circuit, a sync separation circuit, etc., and outputs an audio signal to an audio circuit (not shown), and also a video signal B, an intermediate frequency signal D, and a synchronization signal E. Is output. The video signal B output from the television linear circuit 23 is A /
It is sent to the D conversion circuit 24. The A / D conversion circuit 24 converts the video signal B from the television linear circuit 23 into a 4-bit digital signal C and sends it to the liquid crystal drive circuit 25 to drive the video display unit 12 in the liquid crystal display panel 15.
The intermediate frequency signal D output from the television linear circuit 23 is sent to the frequency detection circuit 26, and the synchronization signal E is sent to the control circuit 27. The frequency detection circuit 26 is
The intermediate frequency signal input from the television linear circuit 23 is discriminated, and two kinds of pulse signals of H (High) or L (Low) are output and given to the control circuit 27. The control circuit 27 receives the 4-bit digital signal C from the A / D conversion circuit 24 and the key data from the key input unit 28. The key input section 28 includes the up / down key 16a for tuning, the down key 16b for tuning, the up key 17a for volume adjustment, and the down key 17b in FIG.
8, a VHF / UHF selector switch 19 and a power switch 20 are provided. Then, the control circuit 27 outputs a tuning control signal to the tuner tuning voltage control circuit 29 to the electronic tuning tuner 22 according to the operation of the tuning up key 16a and the down key 16b from the key input unit 28, and the tuner tuning voltage control circuit 29 outputs the tuning control signal. The tuning voltage control circuit 29 outputs the tuning voltage V _t to the electronic tuning tuner 22. In this case, the control circuit 27 outputs a mute signal to the audio circuit to inhibit the audio output while the tuning operation is being performed, that is, until the next station is selected. Further, the control circuit 27 outputs a volume adjustment signal to the audio circuit according to the operation of the volume adjusting up key 17a and the down key 17b from the key input unit 28. Further, the control circuit 27 outputs a volume display signal and a channel display signal F to the liquid crystal drive circuit 25 in accordance with each key operation in the key input unit 28, and at the same time the liquid crystal drive circuit 25 in accordance with the synchronizing signal E from the television linear circuit 23.
The display timing signal is output to. This liquid crystal drive circuit 2
Reference numeral 5 drives the image display unit 12, the channel display unit 13, and the volume display unit 14 of the liquid crystal display panel 15 for display in accordance with signals from the A / D conversion circuit 24 and the control circuit 27.

Next, details of each part in FIG. 2 will be described.
FIG. 3 shows the details of the frequency detection circuit 26, which comprises a frequency discriminator 261, comparators 262 and 263, and an intermediate frequency signal D sent from the television linear circuit 23 is inputted to the frequency discriminator 261. . And
The output of the frequency discriminator 261 is “+” of the comparator 262.
It is input to the terminal and is also input to the “−” terminal of the comparator 263. The reference power supply 26 is connected to the “−” terminal of the comparator 262 and the “+” terminal of the comparator 263.
4, 265 are respectively connected. Then, the outputs of the comparators 262 and 263 are output as the auto tuning control signals L and H and sent to the control circuit 27. As shown in FIG. 4, the frequency discriminator 261 outputs a positive discrimination signal when the input frequency is lower than the set frequency _p, and outputs a negative discrimination signal when the input frequency becomes higher. Then, when this discrimination signal becomes higher than the reference voltage V ₁ , the comparator 26
2 outputs a signal L, and the discrimination signal is the reference voltage V ₂
When it becomes lower, the signal H is output from the comparator 263 during that time. Then, the comparators 262 and 263 are
Output signals L and H are sent to the control circuit 27 for auto-tuning processing.

FIG. 5 shows the details of the control circuit 27.
The power-on-clear circuit outputs the power-on-clear signal POC to each circuit when the power is turned on. Reference numeral 271 is a reference clock generation circuit including a crystal oscillator 271a, which generates reference clock pulses φ1, φ2, φ3, and φ4. The clock pulses φ1, φ2, and φ3 are horizontal synchronization signals φh.
Is a three-phase clock having a frequency twice that of the clock pulse φ4, and the clock pulse φ4 is a clock pulse φ1 divided by four. A key control circuit 272a determines a key input from the key input unit 28 and outputs it to the digital tuning control circuit 273. The digital tuning control circuit 273 has an AFT (Auto Freq
uency Tuning) signals L and H are input. The digital tuning control circuit 273 operates according to the AFT signals L and H, and outputs a channel coincidence signal CH to a synchronization detection circuit 274 whose details will be described later. Further, the digital tuning control circuit 273 has the tuning voltage counter 27.
5, the load pulse φC, the control pulse φB, and the up / down command U / D are output. This tuning voltage counter 2
The counter 75 counts according to a signal from the digital tuning control circuit 273, and writes the count data in the memory 276 and outputs it to the tuning voltage pulse width modulation wave generation circuit 277 and the volume display circuit / channel display circuit 278. That is, the tuning voltage counter 2
As shown in detail in FIG. 6, 75 is provided with a counter CT each having an input / output terminal of 12 bits. The counter CT has a load pulse φC, a control pulse φB, an up / down pulse from the digital tuning control circuit 273. A command U / D is given and its input terminals I1 to I12
The 12-bit data read from the memory 276 is input to. The counter CT reads the data stored in the memory 276 by the load pulse φC given at power-on, and then counts up or down the control pulse φB according to the up / down command U / D. The output terminals O1 to O of the counter CT are
The count content output from 12 is sent to the memory 276, the pulse width modulation wave generation circuit 277, and the volume display circuit / channel display circuit 278. Of the output terminals O1 to O12 of the counter CT, the outputs of O1 to O3 are input to the NAND circuit NA1 and the NOR circuit NOR2, and O4 to O12.
Is output to the NOR circuit NOR1 and the NAND circuit NA2. The output of the NAND circuit NA1 is the NOR circuit NO.
It is input to R1 and the output of this NOR circuit NOR1 is an inverter.
It is sent to the digital tuning control circuit 273 as an AFT control signal ▲ ▼ via INV. The output of the NOR circuit NOR2 is input to the NAND circuit NA2, and the output of the NAND circuit NA2 is used as the AFT control signal ▲ ▼ in the digital tuning control circuit 27.
Sent to 3. Above AFT control signal ▲ ▼
Indicates that the outputs of the output terminals O1 to O3 of the counter CT are “1” and the outputs of the other output terminals O4 to O12 are all “0”.
It becomes "0" only when, and AFT control signal ▲
▼ is “0” only when the outputs of O1 to O3 are “0” and the outputs of O4 to O12 are all “1”.

Then, the tuning voltage pulse width modulation wave generation circuit 277
Generates a tuning voltage pulse width modulated wave according to the count value of the tuning voltage counter 275 and outputs it to the tuner tuning voltage control circuit 29. The synchronization detection circuit 274 operates according to the control signal from the digital tuning control circuit 273 and the vertical synchronization signal φv and the horizontal synchronization signal φh from the television linear circuit 23, and outputs the synchronization signal to the display control circuit 27.
9. The reset signal R and the synchronization presence / absence signal M are output to the digital tuning control circuit 273. The display control circuit 279 outputs the common control timing signal to the liquid crystal drive circuit 25 and outputs the segment control timing signal to the liquid crystal drive circuit 25 and the volume display circuit / channel display circuit 278. Also, 272b is a key control circuit, which is an up key 17a and a down key 17b for volume adjustment.
When a key is operated, the key input is
Output to 10. The 4-bit counter 2710 counts up or down according to the operation of the up key 17a and the down key 17b, and the count value is counted by the volume display circuit / channel display circuit 278 and D / D.
Output to the A conversion circuit 2711. This D / A conversion circuit 2711 has 4
The count value of the bit counter 2710 is converted into an analog signal and output to a volume control circuit (not shown) as a volume level setting signal. Then, the volume display circuit / channel display circuit 278 causes the liquid crystal drive circuit 25 to respond to the count outputs of the 4-bit counter 2710 and the tuning voltage counter 275 so that the channel display section 13 and the volume display section 14 are displayed.
The segment drive signal of is output. Also, 2712 is an auto level control circuit, which is used for A / D conversion circuits 24 to 4
A frame signal φf is input from the display control circuit 279 as well as bit data is input, and a level control signal is output according to 4-bit data. The level control signal output from the D / A conversion circuit 2712 is D / A
The signal is converted into an analog signal by the A conversion circuit 2713 and sent to a reference voltage generation circuit (not shown), and the reference voltage generation circuit controls the level of the A / D conversion circuit 24 shown in FIG.

Next, details of the digital tuning control circuit 273 in FIG. 5 will be described with reference to FIG. The operation signal UP of the tuning up key 16a from the key control circuit 272a is input to the set terminal S of the flip-flop 61, and the operation signal DOWN of the down key 16b is input to the reset terminal R of the flip-flop 61. The output of the flip-flop 61 is sent to the tuning voltage counter 275 as the up / down signal U / D via the EX OR circuit 62. The tuning up key input UP and the down key input DOWN are input to the flip-flop 65 via the NOR circuit 63 and the NAND circuit 64. Further, a signal indicating that the manual key has been operated is input from the digital tuning control circuit 273 to the flip-flop 65 via the NAND circuit 64. The flip-flop 65 reads an input signal in synchronization with the vertical synchronizing signal φv, and its output is input to a reset terminal R of a quaternary AFT counter 67 via an OR circuit 66 and further It is input to the AND circuit 69 via the circuit 68. Further, the reset signal R from the synchronization detection circuit 274 is input to the reset terminal R of the AFT counter 67 via the OR circuit 66. Then, the signals H and L from the frequency detection circuit 26 are
Is input to the OR circuits 51 and 52, and the OR circuits 51 and 52
The outputs of 52 are clocked inverters 71 and 72, respectively.
Is inputted to the AND circuits 73 and 74 via the clocked inverters and to the other AND circuits 72 and 71 via the clocked inverters 75 and 76. The clocked inverters 71 and 72 are gate-controlled by the output of 61, and the clocked inverters 75 and 76 are gate-controlled by the output of the flip-flop 61 input through the inverter 77. Also, the OR circuit 51,
The output of the flip-flop 53 is input to 52, and mask control is performed on the AFT signals H and L sent from the frequency detection circuit 26 to the OR circuits 51 and 52. Then, the flip-flop 53 has the AFT control signal ▲ ▼ from the tuning voltage counter 275,
It is set or reset in accordance with (5) and the up / down command U / D output from the EX OR circuit 62. That is, the AFT from the tuning voltage counter 275
The control signal ▲ ▼ is input to the OR circuits 54 and 55, and the AFT control signal ▲ ▼ is input to the OR circuit 5.
6 and 57 are input. In addition, the above up / down command
The U / D is input to the OR circuits 54 and 57 and also input to the OR circuits 55 and 56 via the inverter 58. The outputs of the OR circuits 54 and 56 are input to the set terminal S of the flip-flop 53 via the NAND circuit 59,
The outputs of the OR circuits 55 and 57 are input to the reset terminal R of the flip-flop 53 via the NAND circuit 60. Then, the output of the flip-flop 53 is input to the OR circuits 51 and 52 as described above, and the OR circuit 5
The outputs of 1, 52 are input to the AND circuits 73, 74 via the inverters 71, 72, respectively, as described above.

The outputs of the AND circuits 73 and 74 are input to the clock terminal of the quaternary counter 67 via the OR circuit 78. The count content of the quaternary counter 67 is decoded by the decoder 79, the output at the time of “0” count is input to the AND circuit 74 via the OR circuit 80, and the output at the time of “1” count is input to the AND circuit 73. To be done. further,
The output of the decoder 79 at the time of counting "2" is the NOR circuit 6
2, input to the AND circuit 81 and the OR circuits 80 and 82,
The "3" count output is input to the OR circuit 68 via the NOR circuit 83 together with the manual mode signal MANU from the key control circuit 272a. The output of the decoder 79 at the time of counting “3” is input to the reset terminal R of the 64-bit counter 84, the flip-flop 86, and the AND circuit 87. Then, the NOR circuit 82 includes the synchronization detection circuit 27.
The sync presence / absence signal M from No. 4 is input via the AND circuit 88, and the manual key presence signal from the key control circuit 272a is input via the inverter 89 and the AND circuit 88. The output of the OR circuit 82 is input to the gate terminal of the clocked inverter 90 and the gate terminal of the clock inverter 91 via the inverter 92. A clock pulse φ4 and a clock pulse φ3 are input to the inverters 90 and 91, respectively, and their outputs are input to the clock terminal of the 64-bit counter 84. Then, it is input to the AND circuits 69 and 81 of the 64-bit counter 84, the output of the AND circuit 69 is used as the clock pulse φB, and the AND circuit 8
The output of 1 is sent to the tuning voltage counter 275 as the latch timing signal φA. Further, the flip-flop 86 reads the input signal in synchronization with the horizontal synchronization signal φh and outputs the held data to the synchronization detection circuit 274 via the AND circuit 87 as the channel coincidence signal CH. In addition, the digital tuning control circuit 27
3 outputs the timing signal φC as a load signal to the tuning voltage counter 275 in response to the power-on-clear signal POC from the power-on-clear circuit 270.

Next, the operation of the above embodiment will be described. In FIG. 2, the television signal induced in the antenna 21 is tuned and frequency-converted by the electronic tuning tuner 22, then band-amplified and video-detected by the television linear circuit 23, and taken out as a video signal B. This video signal is A / D conversion circuit 2
At 4, the signal is converted into a 4-bit digital signal C, sent to the liquid crystal drive circuit 25, and displayed on the video display unit 12.
An audio signal is output from the television linear circuit 23 and sent to the audio circuit. This audio circuit amplifies the audio signal from the television linear circuit 23 and outputs it from the speaker.

Further, the television linear circuit 23 outputs the intermediate frequency signal D amplified by the internal intermediate frequency amplifying circuit 231 to the frequency detecting circuit 26, and also outputs the vertical synchronizing signal φv and the horizontal synchronizing signal φh separated by the synchronizing separating circuit 234. Output to the control circuit 27. Then, the frequency detection circuit 26
As shown in FIG. 3, the intermediate frequency signal D from the television linear circuit 23 is input to the frequency discriminator 261 to convert the frequency change into a voltage change, and the comparators 262 and 263 convert the AFT signal H for automatic tuning, Create L. At present, in Japan, the upper heterodyne method, in which the local oscillation frequency is higher than that of the received radio wave signal, is used. Therefore, the local oscillation frequency is always higher than the image carrier of the reception channel by the intermediate frequency. Then, as the tuner tuning voltage is increased, the local oscillation frequency also gradually increases. As a result, the intermediate frequency, which is the difference between the local oscillation frequency and the received video frequency, also gradually increases. Frequency discriminator 2 with the intermediate frequency at this time as the horizontal axis
FIG. 4 shows a change in the output voltage of 61. When the output of the frequency discriminator 261 is equal to or higher than the reference voltage V _{1, the} AFT signal L which gives a “1” level is supplied to the comparator 262.
Create with. Similarly, when the output of the frequency discriminator 261 is equal to or lower than the reference voltage V _{2, the} AFT signal H which gives a “1” level is generated by the comparator 263. And the frequency detection circuit 2
If the tuner tuning voltage is fixed when the above AFT signal is output from L-H in order from 6, it is possible to correctly set the intermediate frequency to a predetermined frequency, for example, 58.75 MHz.

On the other hand, if the tuner tuning voltage is lowered, the intermediate frequency gradually lowers. Therefore, if the tuner tuning voltage is fixed when the AFT signal is output from the frequency detection circuit 26 in the order of H-L, As in the above case, the intermediate frequency can be set correctly. Then, the AFT signals L and H output from the frequency detection circuit 26 are sent to the control circuit 27, and the control circuit 27 controls the tuner tuning voltage as described above.

Next, the auto tuning operation of the control circuit 27 will be described. When the tuning up key 16a is pressed in the auto mode, as described above, the frequency detection circuit 26 starts in the order of L-H and the down key 16a.
When b is pressed, AFT signals are output in the order of HL,
It is input to the OR circuits 51 and 52 of the digital tuning control circuit 273 shown in FIG. This OR circuit 51, 52
The AFT signals H and L input to the signal are significant levels on the low level side and are masked by the set output of the flip-flop 53 when the channel selection returns from 12 channels to 1 channel or from 1 channel to 12 channels. That is, when the flip-flop 53 is reset and its output is "0", the AFT signals H and L are directly output from the OR circuits 51 and 52.
However, when the flip-flop 53 is set and its output is "1", the outputs of the OR circuits 51, 52 are held at the "1" signal level regardless of the AFT signals H, L, and the AFT
The signals H and L are masked by the OR circuits 51 and 52. When the tuning voltage counter 275 is turned up / down by the up key 16a or the down key 16b, the tuning voltage V _t applied from the tuner tuning voltage control circuit 29 to the tuner 22 is shown in FIGS. 8 (a) (b). It changes as shown. That is, the tuning voltage V _t is shown in FIG. 8 (a) when the tuning voltage counter 275 is turned up.
When the tuning voltage counter 275 is turned down as shown in Fig. 8 when the tuning voltage counter 275 is down, it changes to 1 as shown in Fig. 8 (b).
It changes abruptly between td2 and td3 when transitioning from channel to channel 12. In the period in which the tuning voltage V _t changes abruptly as described above, H and L of the AFT signal output from the frequency detection circuit 26 are irregular, and therefore, in the vicinity of that period, that is, tu1-tu4, td1- At td4, the flip-flop 53 is set to mask the AFT signal.

Therefore, the flip-flop 53 is set and reset by the AFT control signals ▲ ▼ and ▲ ▼ from the tuning voltage counter 275 and the up / down command U /.
Performed by D. Now, for example, up / down command U
6th when / D is "1", that is, when it is an up command
The tuning voltage counter 275 in the figure goes up,
Immediately before the outputs O1 to O12 of the counter CT are all "1", that is, when the output of O1 to O3 is "0" and the count is further increased from the time when 12 channels are selected, O4 to O4.
When the output of O12 becomes "1", the AFT control signal ▲ ▼ outputted from the NAND circuit NA2 becomes "0". When the AFT control signal ▲ ▼ becomes “0”, the output of the NOR circuit 56 in FIG. 7 becomes “0”,
The output of the NAND circuit 59 becomes "1" and the flip-flop 53 is set. This makes the flip-flop 5
The output of 3 becomes "1", the outputs of the OR circuits 51 and 52 are held at the "1" signal level, and the AFT signals H and L sent from the frequency detection circuit 26 are masked. And
The tuning voltage counter 275 in FIG. 6 continues to count up, and after the outputs of O1 to O12 all return to “0”, the outputs of O1 to O3 are “1” and O4 to before the selection of one channel. When the output of O12 becomes "0",
AFT control signal output from the inverter INV ▲
▼ becomes “0”. This AFT control signal ▲
When ▼ becomes "0", the output of the OR circuit 55 and the output of the NAND circuit 60 in the digital tuning control circuit 273 of FIG. 7 become "0", and the flip-flop 53 is reset. As a result, the output of the flip-flop 53 returns to "0", and the frequency detection circuit 2
The AFT signals H and L sent from 6 are OR circuits 51,
The data is output as it is from 52. Further, when the up / down command U / D is “0” and the down command is given, the flip-flop 53 operates the tuning voltage counter 27.
It is set by AFT control signal ▲ ▼ from 5 and then set by ▲ ▼. As described above, in the vicinity of the output of the tuning voltage counter 275 switching from all "1" to all "0" or vice versa, that is, in the period of tu1 to tu4, td1 to td4 in FIG. AFT signals H and L from 26
Are masked by the OR circuits 51 and 52.

Then, the control circuit 27 always determines whether or not the tuning key is operated, and if there is no key input, it waits as it is. In the digital tuning control circuit 273 shown in FIG. 7, the count value of the AFT counter 67 is “3” when the predetermined channel is selected and the television signal is normally received, and the output of the decoder 79 is output. The "1" signal is output from the terminal "3" and the 64-base counter 84 is held in the reset state. When the "1" signal is output from the output terminal "3" of the decoder 79, the output of the NOR circuit 83 is "0" and the gate of the AND circuit 69 is closed. When the tuning key is operated in this state, the AFT counter 67 is reset, then it is determined whether the operation key is the up key 16a. If the up key 16a is operated, the control unit 273 is operated. Sends a count-up signal from the tuning voltage counter 275 to "+8" the contents of the tuning voltage counter 275. This is to ensure that the current channel is exited. That is, when the up key 16a is operated, the one-shot up key signal UP from the key control circuit 272a.
(High level) is output and the flip-flop 61 is set. The set output of the flip-flop 61 is sent from the EX OR circuit 62 to the tuning voltage counter 275 as an up count command. Further, the output of the flip-flop 61 causes the clocked inverters 71 and 7 to operate.
2 is selected, the AFT signal H from the frequency detection circuit 26,
L is ready to be input to the AND circuits 73 and 74. The up key signal UP is input to the flip-flop 65 via the NOR circuit 63 and the NAND circuit 64.
The flip-flop 65 reads the input signal in synchronization with the vertical synchronizing signal φv, holds it for one cycle (about 16 ms) of the vertical synchronizing signal φv, opens the gate of the AND circuit 69, and resets the AFT counter 67. Hold. This AFT
When the counter 67 is reset, the output from the output terminal "3" of the decoder 79 becomes "0", and the 64-base counter 8
The reset state of 4 is released. At this time, the clock pulse φ3 (φh) is input to the 64-bit counter 84 via the clocked inverter 91. Therefore, the 64-ary counter 84 counts up with the clock pulse φ3, and outputs eight pulse signals while the output of the flip-flop 65 is “1”, that is, in one cycle of the vertical synchronizing signal φv. Output. This 64-base counter 84
Of the clock pulse signal φ via the AND circuit 69.
B is sent to the tuning voltage counter 275. As a result, the content of the tuning voltage counter 275 is incremented by "+8", and the count value is sent to the modulated wave creating circuit 277. The modulated wave generation circuit 277 modulates the count value of the tuning voltage counter 275 into a pulse width and outputs it to the tuner tuning voltage control circuit 29 shown in FIG. The tuner tuning voltage control circuit 29 integrates the modulated wave from the modulated wave creating circuit 277 by an integrator circuit, then amplifies and converts it into a tuner tuning voltage, and supplies it to the electronic tuning tuner 22 to change the local oscillation frequency. Let After that, when the next vertical synchronizing signal φv is applied, “0” is read into the flip-flop 65 and the reset state of the AFT counter 67 is released. Also, at this time, the signal output from the output terminal "3" of the decoder 79 is "0" as described above,
The output of the NOR circuit 83 becomes "1", and the gate of the AND circuit 69 is held open. Then, in this state, it is determined whether or not the AFT signal L is output from the frequency detection circuit 26. That is, when the AFT counter 67 is reset, a “1” signal is output from the output terminal “0” of the decoder 79 and input to the AND circuit 74 via the OR circuit 80. Therefore, the gate of the AND circuit 74 is opened, and the AFT signal L is received. At this time, if the AFT signal L has not been sent, the count-up operation of the 64-base counter 84 is continued, and the tuning voltage counter 275 is incremented by "+1" by the output, and the reception frequency of the electronic tuning tuner 22 is increased. . The count-up operation of the tuning voltage counter 275 is repeated until the AFT signal L is output from the frequency detection circuit 26. When the AFT signal L is sent from the frequency detection circuit 26, this signal L is input to the AFT counter 67 via the inverter 72, the AND circuit 74, and the OR circuit 78. As a result, the contents of the AFT counter 67 are counted up to "1", and the "1" signal is output from the output terminal "1" of the decoder 79. Further, during this time, the counting operation of the 64-base counter 84 is continued, and the output thereof outputs the tuning voltage counter 275.
Is incremented by "+1". The “1” signal output from the output terminal “1” of the decoder 79 is the AND circuit 73.
Is input to open the gate, and the AFT signal H is ready to be received. As a result, the output of the AND circuit 73 can determine whether the AFT signal H is output from the frequency detection circuit 26. If the signal H is not output, the tuning voltage counter 275 is set to "+1" by the output of the 64-base counter 84. To The count-up operation of the tuning voltage counter 275 is repeated until the AFT signal H is output from the frequency detection circuit 26. Then, from the frequency detection circuit 26 to the AF
When the T signal H is sent, this signal H is sent to the inverter 7
1, is output through the AND circuit 73 and the OR circuit 78,
The AFT counter 67 is incremented to "2". As a result, a "1" signal is output from the output terminal "2" of the decoder 79, and the gates of the AND circuits 74 and 81 are opened. Also,
When a "1" signal is output from the output terminal "2" of the decoder 79, the gate of the clocked inverter 91 is closed and the gate of the clocked inverter 90 is opened, and the frequency is low instead of the clock pulse φ3 (φh). The clock pulse φ4 (1 / 4φh) is input to the 64-base counter 84, and the count-up operation of the 64-base counter 84 is delayed. Further, when a "1" signal is output from the output terminal "2" of the decoder 79, the output of the EX OR circuit 62 becomes "0" and a down command is sent to the tuning voltage counter 275. Therefore, after that, the output of the 64-base counter 84 is output via the AND circuit 69 to the tuning voltage counter 275.
The content of "-1" is added. In addition, the 64 base counter 84
Of the tuning voltage counter 27 is sent to the memory 276 as the latch timing φA via the AND circuit 81.
When sent to 5, the contents of tuning voltage counter 275 are latched in memory 276. Further, as described above, when the "1" signal is output from the output terminal "2" of the decoder 79, the gate of the AND circuit 74 is opened and the presence or absence of the AFT signal L is determined. If the AFT signal L has not been sent, the tuning voltage counter 275 is decremented by "-1". When the AFT signal L is sent from the frequency detection circuit 26 by the countdown operation of the tuning voltage counter 275, the AFT counter 67 is incremented by "1" and the count value is "3".
become. Therefore, a "1" signal is output from the output terminal "3" of the decoder 79, the output of the NOR circuit 83 becomes "0", the gate of the AND circuit 69 is closed, and the clock pulse φB is output to the tuning voltage counter 275. Prohibit When the "1" signal is output from the output terminal "3" of the decoder 79, the 64-base counter 84 is reset and the flip-flop 86 and the AND circuit 87 output a one-shot pulse. This one-shot pulse is used as the channel coincidence signal CH to detect the synchronization detection circuit 2
It is output to 74. At this time, the output of the AND circuit 81 becomes "0", and the data written from the tuning voltage counter 275 to the memory 276 is fixed and held as it is. This memory 276 is supplied with an operating voltage even when the power is turned off, and the stored contents are protected. Then, the stored contents of the memory 276 are loaded into the tuning voltage counter 275 by the timing signal φC when the power is next turned on, and the count value of the tuning voltage counter 275 is held at the same value as before the power was turned off. As a result, when the power is turned on, the same channel as when the power is turned off is selected.

Although the case where the up key 16a is operated has been described above, when the down key 16b is operated, the operation of the down key 16b is detected, and the down process is performed in the same manner as the case of the above-mentioned up process.

At that time, the relationship between the AFT signals H and L output from the frequency detection circuit 26 and the up / down relationship of the tuning voltage counter 275 are just opposite to those in the up processing.

Although the auto tuning operation is performed as described above, the period during which the tuning voltage changes rapidly, that is,
In tu1 to tu4 and td1 to td4 in FIGS. 8 (a) and 8 (b),
Since the flip-flop 53 is set and the AFT signals H and L from the frequency detection circuit 26 are masked as described above, the count content of the AFT counter 67 is held as it is. After that, when the above-mentioned period in which the tuning voltage changes abruptly has passed, the flip-flop 53 is reset and the mask state for the AFT signals H and L is released. Therefore, after that, when the count value of the tuning voltage counter 275 reaches the vicinity of channel 1 or channel 12, the AFT signals H and L output from the frequency detection circuit 26 are output as they are via the OR circuits 51 and 52. Then, the auto-tuning operation is restarted, and the desired channel is surely selected and designated.

[Effect of device]

As described above in detail, according to the present invention, in the tuning operation, when the channel selection is changed from 12 channels to 1 channel or from 1 channel to 12 channels, the tuning voltage is drastically changed in the vicinity of both ends of a predetermined frequency range. Since the AFT signal to the digital tuning control circuit is masked, it is possible to provide a digital tuning circuit that can reliably perform channel selection operation without being affected by the irregular changes in the AFT signal. it can.

[Brief description of drawings]

1 shows an embodiment of the present invention. FIG. 1 is an external view of a panel type television receiver, FIG. 2 is a block diagram showing the entire circuit configuration of the television receiver, and FIG. FIG. 4 is a block diagram showing the configuration of the frequency detection circuit, FIG. 4 is a timing chart for explaining the operation of the frequency detection circuit of FIG. 3, FIG. 5 is a block diagram showing the details of the control circuit, and FIG. FIG. 7 is a circuit configuration diagram showing details of a tuning voltage counter in the figure, FIG. 7 is a block diagram showing details of a digital tuning control circuit portion in FIG. 5, and FIG.
(a) (b) is a figure which shows the change of tuning voltage when a tuning voltage counter is raised / lowered. 11 ... Case, 12 ... Image display part, 13 ... Channel display part, 14 ... Volume display part, 15 ... Display panel, 16a ...
Tuning up key, 16b ... Down key, 1
7a ... Up key for volume adjustment, 17b ... Down key,
18 ... Auto / manual switch, 19 ... VHF / UH
F changeover switch, 20 ... power switch, 21 ... antenna, 22 ... electronic tuning tuner, 23 ... TV linear circuit, 24 ... A / D conversion circuit, 25 ... liquid crystal drive circuit, 26 ...
Frequency detection circuit, 27 ... control circuit, 28 ... key input section,
29 ... Tuner tuning voltage control circuit, 261 ... Frequency discriminator, 262, 263 ... Comparator, 264, 265 ... Reference power supply, 271 ... Reference clock generation circuit, 272 ... Key control circuit, 273 ... Digital tuning control circuit, 2
74 ... Synchronous detection circuit, 275 ... Tuning voltage counter, 27
6 ... Memory, 277 ... Modulation wave creating circuit, 278 ... Volume display circuit / channel display circuit, 279 ... Display control circuit, 2710 ... 4-bit counter, 2711 ... D / A conversion circuit, 6
7 ... AFT counter, 79 ... decoder, 84 ... 64 base counter.

Front Page Continuation Chief Judge Masanori Hirano Judge Kazuo Kutana Judge Mitsutake Fujiuchi (56) Reference JP-A-55-118216 (JP, A)

Claims (1)

[Scope of utility model registration request] 1. An up / down key, a circulation type counting means for counting up / down according to an operation of the up / down key, a count value of the counting means is converted into a voltage value, and a tuning operation is performed to determine a reception frequency. The tuning means for detecting, the means for outputting the maximum value signal indicating the predetermined maximum value of the counting means, the means for outputting the minimum value signal indicating the predetermined minimum value of the counting means, and the counting means counting up. The maximum value signal is set and the minimum value signal is reset, and when the counting means is down-counting, the minimum value signal is set and the maximum value signal is set. Set reset means that is reset by the The stop means for stopping the reception frequency detection operation of the tuning means, and the release means for canceling the stop of the reception frequency detection operation of the tuning means by the reset time signal of the set reset means. And a digital tuning circuit.