JP3271637B2 - Tuning control circuit and television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tuning control circuit for a television receiver.

[0002]

2. Description of the Related Art In a television receiver, there is a method in which tuning (tuning) of a tuner circuit is controlled by a voltage synthesizer circuit.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to provide an IC of a channel selection control circuit for performing an AFT operation by digital processing, so that the IC can be used in various television receivers, and can be used in any television receiver. , The AFT operation can be converged in the shortest time.

[0004]

Therefore, in the present invention, if the reference numerals of the respective parts correspond to the embodiments described later, the IC 10 for controlling the tuning of the tuner circuit 1 of the electronic tuning system has an increased number. A down counter 12,
The count output D12 of the up / down counter 12 is D
A D / A converter 13 for performing an A / A conversion to form a tuning voltage VT of the tuner circuit 1, an AFT voltage forming circuit 6 for forming an AFT voltage V6 from the received signal selected by the tuner circuit 1, and an AFT voltage V6. An AFT loop is formed by the control circuit 14 that controls the count of the up / down counter 12 according to the polarity and the magnitude, and the up / down counter 12 and the D / A converter
3 and the control circuit 14 are integrated into a one-chip IC, and read the polarity and magnitude of the AFT voltage V6 to control the count of the up / down counter 12. It is set to be longer than TDL.

[0005]

The AFT operation is executed by digital processing.
The period τ when the digital processing is performed is specified from the outside.

[0006]

FIG. 1 shows a television broadcast receiving system 1 to 5 and an electronic tuning system tuner circuit 1.
The tuner circuit 1 adjusts the tuning voltage VT supplied thereto.
And selects a broadcast wave signal of a frequency (channel) corresponding to the size of the broadcast signal, and converts the frequency into an intermediate frequency signal and outputs it.

The intermediate frequency signal from the tuner circuit 1 is passed through a video intermediate frequency circuit 2 to a video detection circuit 3
To output a color composite video signal, and this signal is supplied to a video signal processing circuit 4, where processing such as color demodulation is performed to obtain three primary color signals. It is supplied to the display 5 and a color image is displayed.

[0010] Reference numeral 10 denotes a one-chip IC for channel selection control composed of standard cells.
Is a circuit 11 for performing the channel selection and the AFT operation after the channel selection.
~ 16.

That is, in the clock forming circuit 11, various timing signals and clock signals are formed and supplied to each circuit.
One clock signal is supplied to the up / down counter 12 as its count input. The count output D12 of the counter 12 is supplied to the D / A converter 13 and converted from a digital value to an analog voltage. This voltage is supplied to the tuner circuit 1 as the tuning voltage VT. Thus, in the tuner circuit 1, the channel (frequency) corresponding to the count value D12 of the counter 12
Is selected.

Reference numeral 14 denotes a counter control circuit.
The control circuit 14 controls the count value of the tuning voltage VT by controlling the count value D12 by controlling the count of the counter 12, and as a result, selects a reception channel.

Therefore, the signal from the detection circuit 3 is AFT
The voltage is supplied to the voltage forming circuit 6, for example, as shown in FIG.
AFT in which the value changes in an S-shape around the normal tuning point f0
A voltage V6 is formed, and the AFT voltage V6 is supplied to the AFT signal conversion circuit 15. V0: AFT voltage V6 at positive tuning point f0 Δf: allowable error of reception frequency with respect to positive tuning point f0 ΔV: change in AFT voltage V6 corresponding to allowable error Δf
Is converted to a digital signal S15 indicating to which of V6> V0 + .DELTA.V V0 + .DELTA.V.gtoreq.V6> V0 V0.gtoreq.V6>V6> V0-.DELTA.V6.ltoreq.V0-.DELTA.V, and this signal S15 is supplied to the control circuit 14 as an AFT signal. Is done.

An output signal of a synchronization separation circuit (not shown) of the processing circuit 4 is supplied to a synchronization pulse detection circuit 16 to form a detection signal S16 indicating the presence or absence of a synchronization pulse. 14. Further, the control circuit 14 is connected to an up key KUP and a down key KDOWN of a channel.

Then, the control circuit 14 sends the counter 12
Is supplied with a count mode signal SU / D indicating the direction of the up-count / down-count.
2 is in the up-count mode when SU / D = “H”, and is in the down-count mode when SU / D = “L”.

Further, an up key KUP and a down key K
When DOWN is pressed, as shown in FIG. 3C, the count enable signal SENB which is at the “H” level for one clock period is output from the control circuit 14 and is supplied to the counter 12 every predetermined period τ. The counter 12 has S
Each time ENB = “H”, counting by one clock is permitted. The control circuit 14 is supplied with, for example, a 2-bit control signal STAU through the external terminals T1 and T2, so that the period τ can be changed in four stages according to the value of the signal STAU.

Then, for example, when the up key KUP is pressed,
When SU / D = “H”, the counter 12 is set to the up-count mode, and the count enable signal SEN is set.
B is supplied to the counter 12.

Therefore, the counter 12 sets the SENB =
Since the clock signal is counted up by one cycle every time it becomes "H", the tuning voltage VT gradually increases in accordance with this up-counting, whereby the reception frequency of the tuner circuit 1 gradually increases. Go.
Thus, the broadcast band is scanned in the direction in which the channel number increases.

When a broadcast wave signal of a television broadcast is received at a certain frequency, a video signal is output from the detection circuit 3, and a synchronization pulse is obtained in the processing circuit 4. Then, the control circuit 14 is notified that the synchronization pulse is obtained by the detection signal S16 from the synchronization pulse detection circuit 16. The output signal S15 of the AFT signal conversion circuit 15 also changes from the above, and the signal S15 is supplied to the control circuit 14.

As a result, the control circuit 14 outputs these signals S
15, it is determined that the broadcast wave signal has been received based on S16,
Scanning is stopped at the channel (frequency) at this time, and the AFT operation is started thereafter.

This AFT operation is realized by controlling the counting direction of the counter 12 so that the above-mentioned state or the above state is maintained. That is, FIGS.
As shown in the figure, at time t1 when SENB = "H", AFT
When the voltage V6 has the magnitude of the region shown in FIG. 2, the AFT signal S15 supplied to the control circuit 14 indicates this state.

Then, according to the AFT signal S15, the control circuit 14 sets SU / D = "H" at least at the time point t1, as shown in FIG. 3B, and the counter 12 is in the up-count mode. Therefore, when SENB = “H” at time t 1, the counter 12 counts up the clock signal by one cycle, and as shown in FIG. 3D, the count value D 12 becomes the previous value “N” at time t 1. To the value “N + 1”.

As a result, as shown in FIG. 3E, the tuning voltage VT gradually increases from time t1, and then SENB =
By the time t3 when it becomes "H", it is stabilized at a level corresponding to D12 = N + 1.

When the tuning voltage VT rises in this way, the local oscillation frequency of the tuner circuit 1 rises and the intermediate frequency rises, so that the AFT voltage V6
Decreases from the area to the area, and V6 = V0 at time t2 in the course of the decrease.

Further, since the AFT voltage V6 enters the region from the time point t2, the AFT signal S15 shows the state from the time point t2. As a result, from the time point t2, the count mode signal SU / D becomes SU / D is set to "L", and the counter 12 is set to the down-count mode from time t2.

Then, when SENB becomes "H" at time t3, the counter 12 counts down the clock signal, so that the count value D12 changes from the previous value "N + 1" to the value "N" at time t3. Decrease. As a result, the tuning voltage VT gradually decreases from the time t3, and then the SENB
By the time t5 when H = "H", the level is stabilized at a level corresponding to D12 = N.

When the tuning voltage VT falls in this manner, the local oscillation frequency of the tuner circuit 1 becomes lower and the intermediate frequency becomes lower, so that the AFT voltage V6
Rises from the area to the area, and V6 = V0 at time t4 during the ascent.

Further, since the AFT voltage V6 enters the region from the time point t4, the AFT signal S15 shows the state from the time point t4. As a result, the count mode signal SU / D starts from the time point t4. SU / D is set to "H", and the counter 12 is set to the up-count mode from time t4.

Then, when SENB becomes "H" at time t5, the state of each part at this time is the same as that at time t1, and thereafter, as shown in FIG. 3, every time SENB becomes "H", The operation after time t1 is repeated.

In this way, when a channel on which broadcasting is being performed is selected by scanning, the scanning is stopped there. Thereafter, the state and the state are alternately repeated with a period of time τ, and the AFT operation is performed. .

Similarly, when the down key KDOWN is pressed, a down count is performed in the counter 12, a scan is performed in a direction in which the channel number decreases, and when a channel on which broadcasting is being performed is received, Scanning stops on that channel, and the reception state of that channel is thereafter maintained by the AFT operation.

Therefore, an arbitrary channel can be selected by pressing the keys KUP and KDOWN, and after the selection, the selected state is maintained by the AFT operation.

In this case, the AFT loop formed by the circuits 11 to 15 and the like forms the AFT signal S15 every time τ.
Is read, and according to the read result, A
Although the FT processing is being performed, # 1 the AFT signal S15 is read, for example, at time t1. # 2 Change the count value D12 according to the reading result. # 3 The tuning voltage VT changes according to the value D12. # 4 The local oscillation frequency of the tuner circuit 1 changes according to the voltage VT. # 5 As a result of the change in the local oscillation frequency, the AFT voltage V6 changes. In each stage, there is a time delay until each becomes stable.

Therefore, for example, at time t1, the control circuit 1
4, a time delay TDL occurs between the time when the AFT signal S15 is read and the time when the AFT voltage V6 is stabilized, as shown in FIG. That is, this AFT loop requires a response time of the period TDL.

At this time, if τ <TDL is set, the control circuit 14 determines that the AFT voltage V6 is still changing while the AFT voltage V6 is still changing due to the previous change in the count value D12. V6 Therefore, the next count value D1
Since the change of 2 is instructed, the AFT operation is not performed correctly, and the overshoot increases, so that the AFT operation hardly converges or does not converge at all.

When τ≫TDL is set, the AFT operation converges, but the convergence slows down. As a result, the scanning slows down and the operability deteriorates.

However, according to the present invention, the control signal STA
By U, the period τ can be set as τ> TDL and τ ≒ TDL, so that the AFT operation can be converged in the shortest time and operability is improved.

Further, since the time period τ can be selected, even if the time delay TDL differs depending on the model, it can be dealt with.
Even if it is converted to C, its use is not restricted.

[0037]

According to the present invention, when the AFT operation is performed, the period τ for reading the AFT signal S15 can be set longer than the response time TDL of the AFT loop and can be selected. The convergence can be achieved in the shortest time, and the operability is improved. Further, even if the response time TDL differs depending on the model, the response time TDL can be dealt with, and even if an IC is used, the use destination is not limited.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an example of the present invention.

FIG. 2 is a diagram for explaining the operation of the circuit of FIG . 1;

FIG. 3 is a diagram for explaining the operation of the circuit of FIG. 1;

[Explanation of symbols]

 Reference Signs List 1 Tuner circuit of electronic tuning system 2 Video intermediate frequency circuit 3 Video detection circuit 4 Video signal processing circuit 5 Display 10 IC 11 Clock formation circuit 12 Up / down counter 13 D / A converter 14 Counter control circuit 15 AFT signal conversion circuit 16 Synchronization pulse Detection circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-180111 (JP, A) JP-A-57-10523 (JP, A) JP-A-1-177213 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H03J 7/18 H03J 5/02 H04N 5/44

Claims (1)

(57) [Claims] 1. An IC for controlling channel selection of an electronic tuning type tuner circuit, comprising: a clock forming circuit for forming a clock of a fixed frequency; an up / down counter for counting the clock; A D / A converter for D / A converting the count output to form a tuning voltage for the tuner circuit, and an AFT based on a reception signal selected by the tuner circuit.
An AFT voltage forming circuit for forming a voltage; a converting circuit for converting the AFT voltage into a digital AFT signal that changes according to the polarity and magnitude of the AFT voltage; From above A
A control circuit that determines the polarity and magnitude of the FT voltage and controls the count of the up / down counter is used for AFT.
A loop is formed, and the clock forming circuit, the up / down counter, the D / A converter, the conversion circuit, and the control circuit are integrated into a one-chip IC, and the control circuit controls the polarity and magnitude of the AFT voltage. An external terminal for setting a cycle for controlling the count of the up / down counter by reading the length of the AFT loop substantially equal to and longer than the response time of the AFT loop is provided in the IC. Tuning control circuit.