JPH0448020Y2 - - Google Patents

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Publication number
JPH0448020Y2
JPH0448020Y2 JP1983043192U JP4319283U JPH0448020Y2 JP H0448020 Y2 JPH0448020 Y2 JP H0448020Y2 JP 1983043192 U JP1983043192 U JP 1983043192U JP 4319283 U JP4319283 U JP 4319283U JP H0448020 Y2 JPH0448020 Y2 JP H0448020Y2
Authority
JP
Japan
Prior art keywords
tuning
signal
digital
channel selection
aft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1983043192U
Other languages
Japanese (ja)
Other versions
JPS59149718U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4319283U priority Critical patent/JPS59149718U/en
Publication of JPS59149718U publication Critical patent/JPS59149718U/en
Application granted granted Critical
Publication of JPH0448020Y2 publication Critical patent/JPH0448020Y2/ja
Granted legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Description

【考案の詳細な説明】 〔考案の属する技術分野〕 本考案は、例えばテレビ、ラジオ、無線機等の
選局装置に関し、特にデイジタル制御手段を用い
た選局装置の改良に関するものである。
[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a channel selection device for, for example, a television, radio, wireless device, etc., and particularly relates to an improvement of a channel selection device using digital control means.

〔従来技術の説明〕[Description of prior art]

デイジタル制御により選局動作を行うものとし
て、ボルテージ・シンセサイザやPLLシンセサ
イザが一般に知られている。このうち、ボルテー
ジ・シンセサイザにおいては、特定の受信周波数
を得るために必要な選局電圧を発生する場合、使
用者が該選局電圧を徐々に変化させ、最適同調点
を目や耳によつて判断することにより行つてい
る。また、使用者のわずらわしさを減らすため、
選局装置自身が特定の放送局を探し出し、最適同
調点を判断するものであり、この場合はAFT
(Automatic Fine Tuning:自動微同調)信号を
選局装置が判断して行つている。
Voltage synthesizers and PLL synthesizers are generally known as devices that perform channel selection operations through digital control. Among these, when using a voltage synthesizer to generate the tuning voltage necessary to obtain a specific reception frequency, the user gradually changes the tuning voltage and determines the optimal tuning point by sight or ear. This is done by making judgments. In addition, in order to reduce the annoyance of the user,
The tuning device itself searches for a specific broadcasting station and determines the optimal tuning point; in this case, AFT
(Automatic Fine Tuning) The tuning device judges the signal and performs this.

一方、PLLシンセサイザにおいては、あらか
じめ受信周波数を正確に規定できるため、ボルテ
ージ・シンセサイザのようなわずらわしさはな
い。しかしながら、送信周波数が規定値からずれ
ていたりした場合には、受信側でそれに合わせて
受信周波数を細かく変化させる必要があり、これ
を選局装置の判断で行う場合、やはりAFT信号
が必要になる。
On the other hand, with a PLL synthesizer, the receiving frequency can be accurately specified in advance, so there is no need for the troubles that occur with a voltage synthesizer. However, if the transmission frequency deviates from the specified value, the reception side must finely change the reception frequency accordingly, and if this is done by the tuning device, an AFT signal is still required. .

上述のようにデイジタル制御の選局装置が
AFT信号を利用する場合は、本来、AFT信号は
アナログ信号であるため、これをデイジタル信号
に変換する必要がある。この構成を第1図に示
す。
As mentioned above, the digitally controlled channel selection device
When using an AFT signal, since the AFT signal is originally an analog signal, it is necessary to convert it into a digital signal. This configuration is shown in FIG.

第1図において、1は電子チユーナ、2は電子
チユーナ1を制御するデイジタル選局回路、3は
AFT信号7を2値化し、デイジタル選局回路2
へ加えるためのウインドコンパレータである。
AFT信号7はコンパレータによつて2値化され、
アツプ信号5とダウン信号6となつてデイジタル
選局回路2へ入力される。例えば、受信周波数が
最適同調点より低い方へずれていればアツプ信号
5が、高い方へずれていればダウン信号6が出力
されている。また、受信周波数が最適同調点と等
しければどちらの信号も出力されない。選局回路
2はこれらの信号を受け取つて電子チユーナ1に
選局電圧信号4を印加し、オートサーチ時の放送
信号検出や微調動作を行うわけである。
In FIG. 1, 1 is an electronic tuner, 2 is a digital tuning circuit that controls the electronic tuner 1, and 3 is a digital tuning circuit that controls the electronic tuner 1.
AFT signal 7 is binarized and digital tuning circuit 2
It is a window comparator for adding to.
AFT signal 7 is binarized by a comparator,
The signal becomes an up signal 5 and a down signal 6 and is input to the digital channel selection circuit 2. For example, if the received frequency is shifted lower than the optimum tuning point, an up signal 5 is output, and if it is shifted higher than the optimal tuning point, a down signal 6 is output. Furthermore, if the receiving frequency is equal to the optimum tuning point, neither signal is output. The tuning circuit 2 receives these signals, applies a tuning voltage signal 4 to the electronic tuner 1, and performs broadcast signal detection and fine tuning operations during auto search.

しかしながら、上記のようにAFT信号を2値
化して処理を行う場合には、最適同調点からのズ
レの度合を選局回路が判断できないという欠点が
あつた。このため、例えば、微調動作においても
ズレが大きい場合は速く、小さい場合は同調ズレ
のないよう遅くするといつたようなきめの細かい
処理を行うには難点があつた。
However, when the AFT signal is binarized and processed as described above, there is a drawback that the tuning circuit cannot judge the degree of deviation from the optimum tuning point. For this reason, it is difficult to perform fine-grained processing such as, for example, in a fine adjustment operation, if the deviation is large, the adjustment is made fast, and if the deviation is small, the adjustment is made slow to avoid synchronization deviation.

〔考案の目的〕[Purpose of invention]

本考案の目的は、上記のような欠点をなくし、
信号処理をより容易かつ確実にしたデイジタル選
局装置を提供するものである。
The purpose of this invention is to eliminate the above-mentioned drawbacks,
The present invention provides a digital channel selection device that makes signal processing easier and more reliable.

〔考案の要点〕[Key points of the idea]

本考案は、バラクタダイオードに印加する電圧
を変化させることにより受信周波数を制御する電
子チユーナを使用し、デイジタル制御により受信
動作を行う選局装置において、選局動作をより容
易かつ確実に行うためにAFT信号を利用する際
に、該AFT信号をA/Dコンバータによつてデ
イジタル信号に変換して処理することを特徴とす
る。
This invention uses an electronic tuner that controls the reception frequency by changing the voltage applied to a varactor diode, and is designed to make the tuning operation easier and more reliable in a tuning device that performs the reception operation by digital control. The present invention is characterized in that when an AFT signal is used, the AFT signal is converted into a digital signal by an A/D converter and processed.

〔実施例による説明〕[Explanation based on examples]

以下、本考案を図面に基づいて説明する。 Hereinafter, the present invention will be explained based on the drawings.

第2図は本考案実施例装置のブロツク構成図で
ある。
FIG. 2 is a block diagram of an apparatus according to an embodiment of the present invention.

第2図において、1は電子チユーナ、2はデイ
ジタル選局回路である。8はA/Dコンバータで
あり、変換ステツプが3以上のものである。
AFT信号はA/Dコンバータ8によつてデイジ
タルデータ信号9に変換され、デイジタル選局回
路2へ出力される。デイジタル選局回路2は受け
取つたデイジタルデータ信号9をもとにして処理
を行い、電子チユーナ1に選局電圧信号4を印加
し、選局を行う。
In FIG. 2, 1 is an electronic tuner, and 2 is a digital tuning circuit. 8 is an A/D converter, which has three or more conversion steps.
The AFT signal is converted into a digital data signal 9 by the A/D converter 8 and output to the digital tuning circuit 2. The digital tuning circuit 2 processes the received digital data signal 9, applies a tuning voltage signal 4 to the electronic tuner 1, and performs tuning.

次に、この処理について詳しく説明する。一例
として4ビツトのA/Dコンバータを使用した場
合の動作について述べる。
Next, this process will be explained in detail. As an example, the operation when a 4-bit A/D converter is used will be described.

AFT信号は第3図に示すグラフのようになつ
ている。これをA/D変換したものが第3図の右
側に示すデータであり、最適受信周波数cで
“1000”、上限周波数uで“0001”、下限周波数L
で“1110”であるとする。選局回路2が受信動作
を行う場合、一例として、第4図のような動作が
考えられる。第4図において、t1−t2間は速く選
局周波数を変えている。t2−t3間は少し動作を遅
くし、t3−t4間はさらに遅くして慎重な選局動作
を行う。そして最適同調点が得られたt4の時点で
選局動作を終了する。以上の動作の切り替えは
A/Dコンバータ8から出力されるデイジタルデ
ータ信号9をもとにして行う。このデイジタルデ
ータ信号9によれば最適受信周波数cからの偏移
の度合いが容易にかつ正確に分るので、上記のよ
うなきめ細かい選局が可能となる。
The AFT signal looks like the graph shown in Figure 3. The A/D conversion of this is the data shown on the right side of Figure 3, where the optimal reception frequency c is "1000", the upper limit frequency u is "0001", and the lower limit frequency L
Suppose that it is “1110”. When the channel selection circuit 2 performs a receiving operation, an operation as shown in FIG. 4 can be considered as an example. In FIG. 4, the selected frequency is rapidly changed between t 1 and t 2 . The operation is slightly slowed down between t 2 and t 3 , and further slowed down between t 3 and t 4 to perform careful channel selection. Then, the channel selection operation ends at time t4 when the optimum tuning point is obtained. The above switching of operations is performed based on the digital data signal 9 output from the A/D converter 8. According to this digital data signal 9, the degree of deviation from the optimum receiving frequency c can be easily and accurately determined, so that detailed tuning as described above becomes possible.

なお、上記の例はあくまで一例であり、選局装
置もボルテージ・シンセサイザとPLLシンセサ
イザの2種に限定されるものではないことは無論
である。
Note that the above example is just an example, and it goes without saying that the channel selection device is not limited to the two types of voltage synthesizer and PLL synthesizer.

〔考案の効果〕[Effect of idea]

以上に説明したように、本考案は、コンパレー
タのかわりにA/Dコンバータを使用することに
より、最適同調点からのズレの度合を判断し、そ
れにより一層きめ細かい確実な選局動作を実現で
きる。また、A/Dコンバータをデイジタル選局
装置と一つにしてLSI化することにより、高度な
機能を持つデイジタル選局用ICを実現できる。
As explained above, the present invention uses an A/D converter instead of a comparator to determine the degree of deviation from the optimum tuning point, thereby realizing a more precise and reliable tuning operation. Furthermore, by integrating the A/D converter with the digital channel selection device into an LSI, a digital channel selection IC with advanced functions can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例装置のブロツク構成図。第2図
は本考案実施例装置のブロツク構成図。第3図は
AFT信号の一例を示す図。第4図は選局動作を
説明する図。 1……電子チユーナ、2……デイジタル選局回
路、4……選局電圧信号、7……AFT信号、8
……A/Dコンバータ、9……デイジタルデータ
信号。
FIG. 1 is a block diagram of a conventional device. FIG. 2 is a block diagram of an apparatus according to an embodiment of the present invention. Figure 3 is
A diagram showing an example of an AFT signal. FIG. 4 is a diagram explaining the channel selection operation. 1...Electronic tuner, 2...Digital tuning circuit, 4...Tuning selection voltage signal, 7...AFT signal, 8
...A/D converter, 9...Digital data signal.

Claims (1)

【実用新案登録請求の範囲】 入力されたAFT(自動微同調)信号に応じてデ
イジタル選局回路から電子チユーナに印加する選
局電圧を変えて受信周波数の制御を行うデイジタ
ル選局装置において、 アナログ量からデイジタル量への変換を行う
A/D変換器を備え、このA/D変換器で上記
AFT信号をデイジタル化して上記デイジタル選
局回路に与え、上記AFT信号の最適受信周波数
からの偏移が大きい時には選局周波数の変化速度
を大きくし、前記偏移が小さい時に選局周波数の
変化速度を小さくするように前記デイジタル化さ
れたAFT信号によつて上記選局電圧を変えるよ
うに構成されたことを特徴とするデイジタル選局
装置。
[Scope of claim for utility model registration] In a digital tuning device that controls the receiving frequency by changing the tuning voltage applied from a digital tuning circuit to an electronic tuner according to an input AFT (automatic fine tuning) signal, Equipped with an A/D converter that converts a quantity into a digital quantity, this A/D converter can perform the above
The AFT signal is digitized and fed to the digital tuning circuit, and when the deviation from the optimum receiving frequency of the AFT signal is large, the speed of change of the tuning frequency is increased, and when the deviation is small, the speed of change of the tuning frequency is increased. 1. A digital channel selection device characterized in that the channel selection voltage is changed by the digitized AFT signal so as to reduce the channel selection voltage.
JP4319283U 1983-03-24 1983-03-24 Digital channel selection device Granted JPS59149718U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4319283U JPS59149718U (en) 1983-03-24 1983-03-24 Digital channel selection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4319283U JPS59149718U (en) 1983-03-24 1983-03-24 Digital channel selection device

Publications (2)

Publication Number Publication Date
JPS59149718U JPS59149718U (en) 1984-10-06
JPH0448020Y2 true JPH0448020Y2 (en) 1992-11-12

Family

ID=30173713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4319283U Granted JPS59149718U (en) 1983-03-24 1983-03-24 Digital channel selection device

Country Status (1)

Country Link
JP (1) JPS59149718U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5282101A (en) * 1975-12-29 1977-07-09 Matsushita Electric Ind Co Ltd Voltage generator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5282101A (en) * 1975-12-29 1977-07-09 Matsushita Electric Ind Co Ltd Voltage generator

Also Published As

Publication number Publication date
JPS59149718U (en) 1984-10-06

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