JPH0537806A - Synchronization control circuit - Google Patents

Abstract

PURPOSE:To minimize the disturbance of display even when the state of a radio wave is excellent or wrong. CONSTITUTION:The control circuit is provided with a synchronizing separator circuit separating a synchronizing signal from a television signal, a counter 33 generating an internal synchronizing signal of the same frequency as the synchronizing signal based on a reference clock signal, a coincidence counter 32 counting number of times of coincidence of a synchronizing signal between the synchronizing signal and the internal synchronizing signal, a dissidence counter 31 counting number of times of dissidence between the synchronizing signal and the internal synchronizing signal, a latch circuit 41 set when the coincidence counter 32 counts coincidence for a prescribed number of times and reset when the dissidence counter 31 counts dissidence for a prescribed number of times, and a display control means implementing the display control operation according to the internal synchronizing signal when the latch circuit 41 is set and implementing the display control operation according to an OR sum signal between the synchronizing signal and the internal synchronizing signal when the latch circuit 41 is reset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous control circuit used in a liquid crystal television receiver or the like.

[0002]

2. Description of the Related Art In recent years, a liquid crystal television receiver using a liquid crystal display panel has been put into practical use. In this type of liquid crystal television receiver, in order to synchronize the drive timing of the liquid crystal display panel with the sync signal of the video signal, display drive control is performed from the sync separation circuit based on the vertical sync signal.
Since the liquid crystal television receiver is often carried around, the radio wave condition is likely to be unstable. It can be said that there is no help even if the screen is disturbed as long as the image signal is disturbed on a general television, but when the channel, volume, etc. are displayed on the screen, the channel and volume are disturbed if the radio wave condition is bad. I will end up. Therefore, a pseudo sync signal is internally generated, and when the radio wave condition is bad, display drive control is performed based on this internal sync signal.

[0003]

However, when the display drive control is performed based on the internal synchronizing signal when the radio wave condition is bad, the phase of the actual video signal and the synchronizing signal may gradually shift. Also, when the display drive control is performed based on the sync signal of the video signal when the radio wave condition is good, in the case of a portable type such as a liquid crystal television receiver, the sync signal is frequently missing and the screen is easily disturbed. ..

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a synchronization control circuit capable of minimizing display disturbance even when the radio wave condition is good or bad.

[0005]

In order to achieve the above object, the present invention provides a sync separation means for separating a sync signal from a television signal and an internal sync signal having the same frequency as the sync signal based on a reference clock signal. An internal synchronization signal generating means for generating, a coincidence detecting means for counting the number of coincidences of the coincidence synchronizing signal of the synchronizing signal and the internal synchronizing signal, and a disagreement detecting means for counting the number of disagreements of the synchronizing signal and the internal synchronizing signal. Set reset means reset when the match detection means counts a predetermined number of matches and reset when the mismatch detection means counts a mismatch for a predetermined number of times, and internal synchronization when the set reset means is set Perform display control operation according to the signal,
The present invention is characterized by comprising display control means for performing display control operation in accordance with the OR addition signal of the synchronizing signal and the internal synchronizing signal when the set resetting means is reset.

[0006]

With the above configuration, when the number of coincidences between the synchronization signal and the internal synchronization signal is counted a predetermined number of times or more and it is determined that the radio wave condition is good, the synchronization signal and the internal synchronization signal almost coincide with each other. Since the display drive control is performed only based on the internal sync signal, the sync signal and the internal sync signal are equivalent when it is determined that the radio wave condition is bad by counting the number of times of mismatch between the sync signal and the internal sync signal a predetermined number of times or more. Since they are deviated, the display drive control is performed based on the OR addition signal of the sync signal and the internal sync signal, so that the phase of the internal sync signal and the sync signal can be prevented from being shifted, and a stable image can be obtained. ..

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, the external structure of the present invention will be described with reference to FIG. In FIG. 1, reference numeral 11 denotes a case, and a video display unit 12, a channel display unit 13, and a volume display unit 14 are provided on the front surface thereof.
Is provided. The video display unit 12, the channel display unit 13, and the volume display unit 14 are integrally formed on, for example, one display panel 15, but are separately displayed by a display window formed on the front surface of the case 11. It has become so. Then, on the channel display section 13, numerical values indicating channels of VHF and UHF are displayed by printing or the like on both sides of the case 11.

On the front surface of the case 11, there are provided an up key 16a and a down key 16b for tuning, and an up key 17a and a down key 17b for volume adjustment. Further, the case 11 is provided with an auto / manual switch 18, a VHF / UHF switch 19, and a power switch 20, and a rod antenna 21 is provided on the upper part of the case 11.

Next, the structure of the electronic circuit provided in the case 11 will be described with reference to FIG. The radio wave received by the antenna 21 is supplied to the electronic tuning tuner 22. The electronic tuning tuner 22 selects a desired radio wave from the received radio waves, converts it into an intermediate frequency A, and outputs it to the television linear circuit 23. This television linear circuit 23,
It is composed of an intermediate frequency amplifier circuit, a video circuit, a sync separation circuit, etc., and outputs an audio signal to an audio circuit (not shown), and also outputs a video signal B, an intermediate frequency signal D, and a synchronization signal E. The video signal B output from the television linear circuit 23 is sent to the A / D converter 24. The A / D converter 24 converts the video signal B from the television linear circuit 23 into a 4-bit digital signal C and sends it to the liquid crystal drive circuit 25 to drive the video display unit 12 in the display panel 15 for display.

The intermediate frequency signal D output from the television linear circuit 23 is sent to the frequency detection circuit 26,
The synchronization signal E is sent to the control circuit 27. The frequency detection circuit 26 discriminates the intermediate frequency signal input from the television linear circuit 23, outputs two kinds of pulse signals of H (High) or L (Low), and supplies them to the control circuit 27. The control circuit 27 receives the 4-bit digital signal C from the A / D converter 24 and the key data from the key input unit 28. The key input section 28 includes an up / down key 16a for tuning, a down key 16b for tuning, an up key 17a for volume adjustment, and a down key 17b in FIG. 1, an auto / manual switch 18, a VHF / UHF switch 19,
A power switch 20 is provided.

Therefore, the control circuit 27 outputs a tuning control signal to the tuner tuning voltage control circuit 29 to the electronic tuning tuner 22 according to the operation of the tuning up key 16a and the down key 16b from the key input section 28. Then, the tuner tuning voltage control circuit 29 outputs the tuning signal Vt to the electronic tuning tuner 22. In this case, the control circuit 27 maintains the tuning operation, that is, until the next station is selected.
A mute signal is output to the audio circuit to prohibit audio output.

The control circuit 27 has a key input unit 2
Up key 17a and down key 1 for volume adjustment from 8
According to the operation of 7b, a volume adjustment signal is output to the audio circuit. Further, a volume display signal and a channel display signal F are output to the control circuit 27 in accordance with each key operation in the key input unit 28, and a display timing signal is output from the television linear circuit 23 to the liquid crystal drive circuit 25 in accordance with a synchronization signal E. Output. This liquid crystal drive circuit 25
In accordance with signals from the A / D converter 24 and the control circuit 27, the image display section 12, the channel display section 13, and the volume display section 14 in the display panel 15 are driven to display.

Next, details of each part in FIG. 2 will be described. FIG. 3 shows details of the electronic tuning tuner 22. The antenna coupling circuit 221 and the high frequency coupling circuit 22 are shown in FIG.
2, a mixing circuit 223, and a local oscillation circuit 224. Then, the antenna 2 is connected to the antenna coupling circuit 221.
1 is input, and the tuning signal V from the tuner tuning voltage control circuit 29 is input to the local oscillation circuit 224.
t is input. The local oscillation frequency of the local oscillation circuit 224 changes according to the tuning signal Vt from the tuner tuning voltage control circuit 29. In accordance with the change in the local oscillation frequency, the mixer circuit 223 outputs the intermediate frequency signal A to and from the receiving station and sends it to the television linear circuit 23.

FIG. 4 shows details of the television linear circuit 23, which includes an intermediate frequency amplifier circuit 231, a detection circuit 232.
The video amplifier circuit 233 and the sync separation circuit 234 are provided, and the intermediate frequency signal A is input from the electronic tuning tuner 22 to the intermediate frequency amplifier circuit 231. The intermediate frequency amplifier circuit 231
Amplifies the input intermediate frequency signal A and outputs the amplified intermediate frequency signal A to the audio circuit.
Output to 33. The video signal B output from the video amplifier circuit 233 is sent to the A / D converter 24 and the sync separation circuit 234. The sync separation circuit 234 separates the horizontal sync signal φh and the vertical sync signal φv included in the video signal from the video amplifier circuit 233, and outputs them to the control circuit 27.

FIG. 5 shows the details of the frequency detection circuit 26. The frequency discriminator 261 and the comparators 262 and 26 are shown in FIG.
3, the intermediate frequency signal D sent from the television linear circuit 23 is input to the frequency discriminator 261.
The output of the frequency discriminator 261 is the comparator 26
2 is input to the “+” terminal and the comparator 26
3 is input to the "-" terminal. In addition, the comparator 26
The reference power sources 264 and 265 are connected to the “−” terminal of 2 and the “+” terminal of the comparator 263, respectively. Then, the outputs of the comparators 262 and 263 are output as the auto tuning control signals L and H and sent to the control circuit 27.

As shown in FIG. 6, the frequency discriminator 261 outputs a positive discrimination signal when the input frequency is lower than the set frequency fp, and outputs a negative discrimination signal when the input frequency becomes higher than the set frequency fp. When this discrimination signal becomes higher than the reference voltage V1, the comparator 2
A signal L is output from 62, and the discrimination signal is the reference voltage V
_When it becomes lower than _{2, the} signal H is output from the comparator 263 during that time. Then, the comparators 262 and 2
Output signals L and H of 63 are sent to the control circuit 27, and an auto tuning process is performed.

FIG. 7 shows the details of the control circuit 27.
A power-on clear circuit 270 outputs a power-on clear signal POC to each circuit when the power is turned on. Also, 27
Reference numeral 1 is a reference clock generation circuit having a crystal oscillation element 271a, and generates reference clock pulses φ1, φ2, φ3, φ4. The clock pulses .phi.1, .phi.2, .phi.3 are three-phase clocks having a frequency twice that of the horizontal synchronizing signal .phi.h, and the clock pulse .phi.4 is a clock pulse .phi.1 divided by four.

A key control circuit 272a determines a key input from the key input unit 28 and outputs it to the digital tuning control circuit 273. AFT (AUTO Frequency Tuning) signals L and H from the frequency detection circuit 26 are input to the digital tuning control circuit 273. The digital tuning control circuit 2
73 operates according to the AFT signals L and H, and outputs a channel coincidence signal CH to a synchronization detection circuit 274 whose details will be described later. In addition, the digital tuning control circuit 2
A control pulse φB and an up / down command U / D are output to the tuning voltage counter 275 at 73. The tuning voltage counter 275 counts up according to a signal from the digital tuning control circuit 273. The count data is written in the memory 276, and the tuning voltage pulse modulated wave creating circuit 277 and the volume display circuit / channel display circuit 278 are also provided. Output to.

The tuning voltage pulse modulated wave generation circuit 277.
Generates a tuning voltage pulse width modulated wave according to the count value of the tuning voltage counter 275 and outputs it to the tuner tuning voltage control circuit 29. The sync detection circuit 274 operates according to the control signal from the digital tuning control circuit 273 and the vertical sync signal φv and the horizontal sync signal φh from the television linear circuit 23, and outputs the sync signal to the display control circuit 2.
79, and outputs the reset signal R and the synchronization presence / absence signal M to the digital tuning control circuit 273. The display control circuit 279 outputs the common control timing signal to the liquid crystal drive circuit 25 and outputs the segment control timing signal to the liquid crystal drive circuit 25 and the volume display circuit / channel display circuit 278.

A key control circuit 272b outputs a key input to a 4-bit counter 2710 when the volume adjusting up key 17a or down key 17b is operated. The 4-bit counter 2710 counts up or down according to the operation of the up key 17a and the down key 17b, and outputs the count value to the volume display circuit / channel display circuit 278 and the D / A converter 2711. .. This D / A converter 2711
Converts the count value of the 4-bit counter 2710 into an analog signal and outputs it to a volume control circuit (not shown) as a volume level setting signal. Then, the volume display circuit /
The channel display circuit 278 is a 4-bit counter 271.
The segment drive signals of the channel display unit 13 and the volume display unit 14 are output to the liquid crystal drive circuit 25 according to the count output of 0 and the tuning voltage counter 275.

Reference numeral 2712 denotes an auto level control circuit, which receives 4 bits from the A / D converter 24 and a frame signal φf from the display control circuit 279 and outputs a level control signal according to 4 bits data. Output. The level control signal output from the D / A conversion circuit 2712 is the D / A conversion circuit 271.
An analog signal is converted by 3 and sent to a reference voltage generating circuit (not shown), and the reference voltage generating circuit controls the level of the A / D converter 24 shown in FIG.

Next, details of the synchronization detection circuit 274 are shown in FIG.
Will be explained. In FIG. 8, reference numeral 31 is a mismatch counter, which outputs a "1" signal from the output terminal when the count value becomes "64". 32 is a coincidence counter, which has output terminals 0 ₁ and 0 ₂ and outputs a “1” signal from the output terminal 0 ₁ when the count value is “2” and from the output terminal 0 ₂ when the count value is “4” Output a "1" signal. 33 is 5
25 binary counter, an output terminal 0 _1, 0 _2, and outputs the count contents from the output terminal 0 _1, from the output terminal 0 ₂ count value and outputs "1" signal when it is "525" .. 34 is a sync detection counter, which has output terminals 0 ₁ , 0
₂ , the output terminal 0 ₁ outputs a “1” signal when the count value is “7”, and the output terminal 0 ₂ outputs a “1” signal when the count value is “8”.

The vertical sync signal φv sent from the sync separation circuit 234 shown in FIG. 3 receives the match counter 31 via the OR circuit 35 and the latch circuit 36 and the clock terminal CK of the mismatch counter 31 and the AND circuit 37. It is input to the clock terminal CK of 32, the reset terminal R of the mismatch counter 31, and the clock terminal CK of the synchronization detection counter 34 via the NOR circuit 38. In addition, the above 525
A reference clock pulse φ1 having a frequency twice the horizontal synchronizing signal φh is input to the clock terminal CK of the advance counter 33. The latch circuit 36 is composed of a NOR circuit 361, an AND circuit 362 and an inverter 363. The latch circuit 36 is set by a clock pulse ~ φ1 (an inverted signal of φ1) input to the AND circuit 362 and reset by the output of the OR circuit 35. ..

The output of the counter 31 is input to the reset terminal R of the coincidence counter 32 via the OR circuit 39 and the reset signal to the latch circuit 41. The output of the latch circuit 41 is used as the presence / absence signal M of the synchronization signal, and the digital tuning control circuit 2
Along with being sent to 73, it is inputted to the NAND circuit 43 via the NOR circuit 42. The latch circuit 41 includes a NAND circuit 411, an AND circuit 412 and an inverter 413, and is reset by a signal input from the coincidence counter 32 to the AND circuit 412 via the inverter 44.

Further, the vertical synchronizing signal φv sent from the sync separating circuit 234 is inputted to the NAND circuit 43 via the OR circuit 45 and the NAND circuit 46. Further, the output of the inverter 413 is input to the NAND circuit 46. Then, the display control circuit 279 is output as the output signal φV of the synchronization detection circuit 274 of the NAND circuit 43.
And is input to the reset terminal R of the 525-ary counter 33. Signal output from the output terminal 0 ₂ of the 525-ary counter 33 is sent to the flip-flop 47. The flip-flop 47 reads the output of the 525-ary counter 33 in synchronization with the clock pulse φ 2 and inputs it to the NAND circuit 42, the OR circuit 45, and the AND circuit 37, and at the same time, via the inverter 48, the OR circuit 35.
To enter.

The output terminal 0 of the 525-ary counter 33
_The count content output from ₁ is decoded by the decoder 49 and then read into the flip-flop 50 in synchronization with the clock pulse φ _n2 . This clock pulse φ
_n2 is a clock for latching 1H display data in the liquid crystal drive circuit 25. Then, the data held in the flip-flop 50 is sent to the display control circuit 279 as a signal for starting vertical scanning.

On the other hand, the channel coincidence signal CH sent from the digital tuning control circuit 273 is
It is input to the flip-flop 51. The flip-flop 51 reads the input data in synchronization with the clock pulse φ1 and inputs it to the flip-flop 52 and the AND circuit 53. The flip-flop 52 reads the input data in synchronization with the clock pulse φ2 and outputs it in synchronization with the clock pulse φ1. The output of the flip-flop 52 is input to the reset terminal R of the coincidence counter 32 via the AND circuit 53 and the OR circuit 39.

The channel coincidence signal CH is input to the reset terminal R of the synchronization detection counter 34 via the inverter 54. The carry output of the synchronization detection counter 34 is input to its own clock terminal CK via the NOR circuit 38, and the count output is supplied as a reset signal R to the digital tuning control circuit 273 in FIG. 7 via the inverter 55 and the NOR circuit 56. Sent. Further, the channel coincidence signal CH is input to the reset terminal of the flip-flop 57 and the AND circuit 58. Further, the signal output from the output terminal 0 ₁ of the coincidence counter 32 is input to the set terminal of the flip-flop 57 via the inverter 59. And
The output of the flip-flop 57 is taken out via the AND circuit 58, input to the NOR circuit 56, and sent to the audio circuit as a mute signal MU.

Next, details of the digital tuning control circuit 273 in FIG. 7 will be described with reference to FIG. The operation signal UP of the tuning up key 16a from the key control circuit 272a is input to the set terminal S of the flip-flop 61, and the operation signal DOWN of the down key 16b is input to the reset terminal R of the flip-flop 61. The output of the flip-flop 61 is supplied to the up / down signal U /
D is sent to the tuning voltage counter 275.

The tuning up key input UP and the down key input DOWN are input to the flip-flop 65 via the NOR circuit 63 and the NAND circuit 64. Further, a signal indicating that the manual key has been operated is input from the digital tuning control circuit 273 to the flip-flop 65 via the NAND circuit 64. The flip-flop 65 reads the input signal in synchronization with the vertical synchronizing signal φv, and the output thereof is the reset terminal R of the quaternary counter via the OR circuit 66.
To the AND circuit 69 via the OR circuit 68.

Further, the reset signal R from the synchronization detection circuit 274 is input to the reset terminal R of the quaternary counter 67 via the OR circuit 66. The signals H and L from the frequency detection circuit 26 are input to the AND circuits 73 and 74 via the clocked inverters 71 and 72, respectively, and the other AND circuit via the clocked inverters 75 and 76. 72 and 71. The clocked inverters 71 and 72 are
The gated inverters 75 and 76 are gate-controlled by the output of the flip-flop 61 and the output of the flip-flop 61 input via the inverter 77.

The outputs of the AND circuits 73 and 74 are input to the clock terminal of the quaternary counter 67 via the OR circuit 78. The count content of the quaternary counter 67 is decoded by the decoder 79, the output at the time of "0" count is input to the AND circuit 74 via the OR circuit 80, and the output at the time of "1" count is input to the AND circuit 73. To be done.

Further, the output of the decoder 79 at the time of counting "2" is the NOR circuit 62, the AND circuit 81, and the OR circuit 8.
The count output of "3" is input to the OR circuit 68 from the key control circuit 272a through the NOR circuit 83 together with the manual mode signal MANU. The output of the decoder 79 at the time of counting “3” is the reset terminal R of the 64-bit counter 84 and the flip-flop 8
6, input to the AND circuit 87. Then, the NOR circuit 82 is provided with a synchronization presence signal M from the synchronization detection circuit 274.
Is input via the AND circuit 88, and the manual key presence signal from the key control circuit 272a is input via the inverter 89 and the AND circuit 88.

The output of the OR circuit 82 is input to the gate terminal of the clocked inverter 90 and the gate terminal of the clocked inverter 91 via the inverter 92. The inverters 90 and 91
A clock pulse φ4 and a clock pulse φ3 are inputted to the respective terminals, and the outputs thereof are inputted to the clock terminal of the 64-ary counter 84. Then, it is input to the AND circuits 69 and 81 of the 64-ary counter 84, the output of the AND circuit 69 is sent to the tuning voltage counter 275 as the clock pulse φB, and the output of the AND circuit 81 is sent to the tuning voltage counter 275, respectively. ..

The flip-flop 86 reads the input private language in synchronization with the horizontal synchronizing signal φh, and outputs the held data to the synchronization detecting circuit 274 via the AND circuit 87 as the channel coincidence signal CH. The digital tuning control circuit 273 outputs the timing signal φC as a load signal to the tuning voltage counter 275 in response to the power-on-clear signal POC from the power-on-clear circuit 270.

Next, the operation of the above embodiment will be described. In FIG. 2, the television signal induced in the antenna 21 is tuned and frequency-converted by the electronic tuning tuner 22,
Bandwidth amplification and video detection are performed by the television linear circuit 23, and the video signal B is extracted. This video signal is A
The signal is converted into a 4-bit digital signal C in the / D converter 24 and sent to the liquid crystal drive circuit 25 to be transmitted to the video display unit 12.
Displayed in. Also, an audio signal is output from the television linear circuit 23 and sent to the audio circuit. This audio circuit amplifies the audio signal from the television linear circuit 23,
Output from the speaker.

Further, the television linear circuit 23 has the intermediate frequency signal D amplified by the internal intermediate frequency amplifier circuit 231.
Is output to the frequency detection circuit 26, and the vertical synchronization signal φv and the horizontal synchronization signal φ separated by the synchronization separation circuit 234 are output.
It outputs h to the control circuit 27. Then, the frequency detection circuit 26 inputs the intermediate frequency signal D from the television linear circuit 23 to the frequency discriminator 261 to convert the frequency change into a voltage change, and the comparators 262 and 263 use the AFT signal H for auto tuning. , L are created. At present, in Japan, the upper heterodyne method, in which the local oscillation frequency is higher than that of the received radio wave signal, is used. Therefore, the local oscillation frequency is always higher than the video carrier of the receiving channel by the intermediate frequency.

Then, as the tuner tuning voltage is increased, the local oscillation frequency also gradually increases. As a result, the intermediate frequency, which is the difference between the local oscillation frequency and the received video frequency, also gradually increases. FIG. 6 shows changes in the output voltage of the frequency discriminator 261 with the horizontal axis representing the intermediate frequency at this time. When the output of the frequency discriminator 261 is equal to or higher than the reference voltage V1, the AFT signal L which gives a "1" level is generated by the comparator 262.

Similarly, the AFT signal H which gives a "1" level when the output of the frequency discriminator 261 is equal to or lower than the reference voltage V ₂ is generated by the comparator 263. Then, by fixing the tuner tuning voltage output from the frequency detection circuit 26 in the order of the AFT signal LH, the intermediate frequency can be correctly set to a predetermined frequency, for example, 58.57 MHz.

On the contrary, when the tuner tuning voltage is lowered, the intermediate frequency is gradually lowered.
If the tuner tuning voltage is fixed when the signals are output from the frequency detection circuit 26 in the order of H-L, the intermediate frequency can be set correctly as in the above case. Then, the AFT signals L and H output from the frequency detection circuit 26 are sent to the control circuit 27, which controls the tuner tuning voltage as described above. The details will be described later. ..

On the other hand, the control circuit 27 detects the synchronizing signals φv and φh from the television linear circuit 23 and controls the scanning of the image display section 12.

First, the synchronization detection circuit 27 in the control circuit 27.
The synchronization signal detection processing in No. 4 will be described with reference to the flowchart of FIG. 10 and the timing chart of FIG. In the synchronization detection circuit 274, when the power switch 20 is turned on, the mismatch counter 31, the match counter 32, and the latch circuit 41 are set as shown in step A1 of FIG. When the latch circuit 41 is reset, the output of the inverter 413 becomes “1” and the NAND circuit 46 is output.
Entered in.

In this state, the sync separation circuit 234 is operated as shown in FIG.
When the vertical synchronizing signal φv shown in FIG.
The output of 6 becomes "0", the "1" signal is output from the NAND circuit 43, and the 525-ary counter 33 is reset as shown in step A2. This 525-base counter 33
After that, it counts clock pulses φ 1 having a frequency twice that of the horizontal synchronizing signal φh, and when the count value becomes “525”, it outputs a “1” signal from the output terminal 0 ₂ . The output of the 525-ary counter 33 is read into the flip-flop 47 in synchronization with the clock pulse φ2. As a result, the output of the flip-flop 47 becomes "1", which is input to the AND circuit 37, and is inverted by the inverter 48 into a "0" signal, so that the OR circuit 3
5 is input to determine whether or not the vertical synchronizing signal φv is present, as shown in step A3. That is, if the next vertical synchronizing signal .phi.v is normally received, the output of the AND circuit 37 becomes "1", the coincidence counter 32 is incremented by "+1" as shown in step A4, and step A
As shown in 5, the mismatch counter 31 is reset.

[0044] Thereafter, in step A6, the match count value of the counter 32 determines whether it is "4" is performed, "4" in case when the output terminal 0 ₂ from "1" signal is output. As a result, the latch circuit 41 is set as shown in step A7, and then the process proceeds to step A8. In step A6, the match counter 3
If the count value of 2 is not "4", the process proceeds to step A8, and it is determined whether the latch circuit 41 is set or reset. When the latch circuit 41 is set, its output becomes "1" and is input to the NAND circuit 42. Therefore, as shown in step A9, it is held in the flip-flop 47 and the 525-ary counter 3
The output of No. 3 is output from the NAND circuit 42. As a result,
The output of the NAND circuit 42 becomes “0”, the output of the NAND circuit 43 becomes “1”, and the output of the NAND circuit 43 is sent to the liquid crystal drive circuit 25 as the vertical synchronizing signal φv.

The vertical synchronizing signal φv causes the frame signal φf in the liquid crystal drive circuit 25 as shown in FIG.
Is created. When the latch circuit 41 is reset, the output of the inverter 413 becomes "1" and is input to the NAND circuit 46. Therefore, step A
As shown in FIG. 10, the vertical sync signal φv from the sync separation circuit 234 and 52 held in the flip-flop 47.
The OR circuit 45 with the quinary counter 33 is output from the NAND circuit 46. As a result, the output of the NAND circuit 46 becomes "0" and the output of the NAND circuit 43 becomes "1", and the output of this NAND circuit 43 is sent to the liquid crystal drive circuit 25 as the vertical synchronizing signal φv. Thereafter, the process returns to step A2, the 525-base counter 33 is reset by the output of the NAND circuit 43, and the above-described operation is repeated.

In step A3, 5
When the output of the 25-ary counter 33 is read into the flip-flop 47, for example, when the next vertical synchronizing signal φv is not given due to deterioration of the reception state, the output of the OR circuit 35 becomes “0” and latches. Circuit 36 is set.
As a result, the output of the latch circuit 36 becomes "1", and the content of the mismatch counter 31 is incremented by "1" as shown in step A11.

Next, as shown in step A12, it is judged whether or not the count value of the non-coincidence counter 31 has reached "64". If the count value has not reached "64", the output of the non-coincidence counter 31 is "0". So immediately step A
As shown in FIG. 8, the latched state of the latch circuit 41 is judged and the operation proceeds to the next step. If the count value of the non-coincidence counter 31 reaches "64", the non-coincidence counter 31 outputs a "1" signal, the coincidence counter 32 is reset as shown in step A13, and the step A
As shown in 14, the latch circuit 41 is reset.

Thereafter, as shown in step A8, it is determined whether the latch circuit 41 is set or reset. When the latch circuit 41 is set, the output of the 525-base counter 33 held in the flip-flop 47 is set as the vertical synchronizing signal φv via the NAND circuits 42 and 43 as the liquid crystal drive circuit 25 as shown in step A9. Output to. When the latch circuit 41 is reset, the vertical sync signal φv from the sync separation circuit 234 and the OR output of the output signal of the 525-ary counter 33 are supplied to the liquid crystal through the NAND circuits 46 and 43 as shown in step A10. Output to the drive circuit 25.

If the vertical synchronizing signal φv is given from the sync separation circuit 234 before the count value of the non-coincidence counter 31 reaches "64", the coincidence counter 32 is set to "+".
"1", the mismatch counter 31 is cleared, and the normal state operation is resumed. On the other hand, the mismatch counter 31
Each time the count value reaches “525”, the decoder 49
Is decoded by and is read by the flip-flop 50 in synchronization with the clock φ _n2 . The output of the flip-flop 50 is sent to the liquid crystal drive circuit 25 as a vertical scanning start signal Dout as shown in FIG.

Next, the auto-tuning operation of the control circuit 27 shown in FIGS. 7, 8 and 9 will be described. There are two types of auto tuning: auto mode and manual mode. In the auto mode, the frequency detection circuit 26 is used to automatically select a channel. In manual mode, the tuner tuning voltage is swept by key operation. First, the tuning operation in the auto mode will be described with reference to the flowcharts of FIGS. In the auto mode, as described above, when the tuning up key 16a is pressed, the frequency detection circuit 26 performs L-H order, and when the down key 16b is pressed, H-L order. To output the AFT signal. Then, the control circuit 27 determines whether or not the tuning key has been operated as shown in step B1 of FIG. 12, and if there is no key input, it waits as it is.

In the digital tuning control circuit 273 shown in FIG. 9, when the predetermined channel is selected and the television signal is normally received, the count value of the quaternary counter 67 is "3", and the decoder The “1” signal is output from the output terminal “3” of 79, and the 64-base counter 84 is held in the reset state. When the "1" signal is output from the output terminal "3" of the decoder 79, the output of the NOR circuit 83 is "0", and the gate of the AND circuit 69 is closed.

When the tuning key is operated in this state, the quaternary counter 67 is reset as shown in step B2. Then, in step B3, it is determined whether or not the operation key is the up key 16a. 16a
If is operated, a count-up signal is sent from the control circuit 273 to the tuning voltage counter 275 as shown in step B4, and the content of the tuning voltage counter 275 is "+8". This is to ensure that the current channel is exited. That is, when the up-key 16a is operated, the one-shot up-key signal UP (high level) is output from the key control circuit 272a, and the flip-flop 61 is set. The set output of the flip-flop 61 is sent from the EX OR circuit 62 to the tuning voltage counter 275 as a count-up command. Further, the clocked inverters 71 and 72 are selected by the output of the flip-flop 61, and the frequency detection circuit 26 outputs the AF signal.
The T signals H and L are ready to be input to the AND circuits 73 and 74.

Further, the up-key signal UP passes through a NOR circuit 63 and a NAND circuit 64, and a flip-flop 65.
Entered in. The flip-flop 65 reads the input signal in synchronization with the vertical synchronizing signal φv and outputs the vertical synchronizing signal φv.
Hold for 1 cycle of v (about 16 ms) and AND circuit 6
The gate 9 is opened and the quaternary counter 67 is held in the reset state. When the quaternary counter 67 is reset, the output from the output terminal "3" of the decoder 79 is "0".
Then, the reset state of the 64-base counter 84 is released. At this time, the clock pulse φ 3 is input to the 64-ary counter 84 via the clocked inverter 91.

Therefore, the 64-base counter 84 counts up by the clock pulse φ3, and then descends and descends 65.
8 is output, that is, eight pulse signals are output during one cycle of the vertical synchronizing signal φv. The output of the 64-ary counter 84 is sent to the tuning voltage counter 275 as a clock pulse signal φB via the AND circuit 69. As a result, the content of the tuning voltage counter 275 is "+8", and the count value is the modulated wave creating circuit 277.
Sent to.

The modulated wave creating circuit 277 modulates the count value of the tuning voltage counter 275 into a pulse width and outputs it to the tuner tuning voltage control circuit 29 shown in FIG. The tuner tuning voltage control circuit 29 uses the modulated wave generation circuit 2 described above.
The modulated wave from 77 is integrated by an integrating circuit, then amplified and converted into a tuner tuning voltage, and the electronic tuning tuner 2
2 to change the local oscillation frequency.

Thereafter, when the next vertical synchronizing signal φv is applied, "0" is read into the flip-flop 65 and the reset state of the quaternary counter 67 is released. Also, at this time, as described above, the output terminal "3" of the decoder 79 is set.
Since the signal output from the AND circuit is "0", the output of the NOR circuit 83 is "1" and the gate of the AND circuit 69 is held open. Then, in this state, as shown in step B5, it is determined whether or not the signal L is output from the frequency detection circuit 26. That is, when the quaternary counter 67 is reset, a “1” signal is output from the output terminal “0” of the decoder 79 and the OR circuit 80.
Is input to the AND circuit 74 via. Therefore, the gate of the AND circuit 74 is opened, and the AFT signal L is received.

At this time, if the AFT signal L has not been sent, the count-up operation of the 64-base counter 84 is continued, and the output thereof outputs "+1" to the tuning voltage counter 275 as shown in step B6 to perform electronic tuning. Tuner 2
Increase the reception frequency of 2. The processes of steps B5 and B6 are repeated until the AFT signal L is output from the frequency detection circuit 26. Then, the frequency detection circuit 26
When the AFT signal L is sent from the AFT signal L, the signal L is sent to the inverter 4 through the inverter 72, the AND circuit 74 and the OR circuit 78
It is input to the decimal counter 67. As a result, the content of the quaternary counter 67 is incremented by "1" as shown in step B7, and the output terminal "1" of the decoder 79 is changed to "1".
The signal is output. During this time, the counting operation of the 64-base counter 84 is continued, and the output thereof causes step B8.
The tuning voltage counter 275 is incremented by "+1" as shown in FIG.

The "1" signal output from the output terminal "1" of the decoder 79 is the AND circuit 7.
3, the gate is opened to receive the AFT signal H. As a result, from the output of the AND circuit 73, the frequency detection circuit 26 outputs the AF signal as shown in step B9.
It is possible to determine whether or not the T signal H is output. If the signal H is not output, the tuning voltage counter 275 is set to "+" by the output of the 64-base counter 84 as shown in step B8.
1 ”.

The processes of steps B6 and B9 are repeated until the AFT signal H is output from the frequency detection circuit 26. When the AFT signal H is sent from the frequency detection circuit 26, this signal H is output through the inverter 71, the AND circuit 73, and the OR circuit 78, and the quaternary counter 67 is set to "2" as shown in step B10. To count up. As a result, the decoder 79
The "1" signal is output from the output terminal "2" of the AND circuit, and the gates of the AND circuits 74 and 81 are opened. When a "1" signal is output from the output terminal "2" of the decoder 79,
The gate of the clocked inverter 91 is closed and the gate of the clocked inverter 90 is opened, and Step B11
As shown in (4), the clock pulse φ4 having a low frequency is input to the 64-bit counter 84 instead of the clock pulse φ3, and the count-up operation of the 64-bit counter 84 is delayed.

Further, when a "1" signal is output from the output terminal "2" of the decoder 79, the EX OR circuit 6
The output of 2 becomes "0", and a down command is sent to the tuning voltage counter 275 as shown in step B12. Therefore, thereafter, the output of the 64-base counter 84 is the AND circuit 6
When it is sent to the tuning voltage counter 275 via 9, the content of the tuning voltage counter 275 is decremented by "-1" as shown in step B13. Further, the output of the 64-base counter 84 is sent to the memory 276 at the latch timing φB via the AND circuit 81, and the content of the tuning voltage counter 275 is latched in the memory 276.

When the "1" signal is output from the output terminal "2" of the decoder 79 as described above, the gate of the AND circuit 74 is opened, and it is determined whether or not the AFT signal L is present as shown in step B14. To be done. If the AFT signal L has not been sent, the process returns to step B13 and the tuning voltage counter 275 is decremented by "-1". When the AFT signal L is sent from the frequency detection circuit 26 by the counting up process of the tuning voltage counter 275, the quaternary counter 67 is incremented by "+1" as shown in step B15, and the count value is "3". become. Therefore, a "1" signal is output from the output terminal "3" of the decoder 79, the output of the NOR circuit 83 becomes "0", the gate of the AND circuit 69 is closed, and the clock pulse φB is output to the tuning voltage counter 275. Prohibit

The output terminal "3" of the decoder 79
When the "1" signal is output from, the 64-base counter 84 is reset, and the one-shot pulse is output by the flip-flop 86 and the AND circuit 87.
This one-shot pulse is output to the synchronization detection circuit 274 as the channel coincidence signal CH as shown in step B16. At this time, the output of the AND circuit 81 becomes "0", and the data written from the tuning voltage counter 275 to the memory 276 is fixed and held as it is, as shown in step B17. The memory 276 is supplied with an operating voltage even when the power is turned off, and the stored contents are protected.

The contents stored in the memory 276 are as follows.
Next, when the power is turned on, the tuning voltage counter 275 is loaded with the timing signal φC, and the tuning voltage counter 2 is loaded.
The count value of 75 is held at the same value as before the power was turned off. As a result, when the power is turned on, the same channel as when the power is turned off is selected.

On the other hand, the synchronization detection circuit 274 shown in FIG.
When the channel matching signal CH is sent from the digital tuning control circuit 273, the synchronization detection counter 34 is reset as shown in step B18, and the matching counter 32 is reset as shown in step B19. That is, the channel coincidence signal CH is input to the reset terminal R of the synchronization detection counter 34 via the inverter 54, and the flip-flops 51, 5 are connected.
2. The waveform is shaped into a pulse signal having a constant width by the AND circuit 53, and is input to the reset terminal R of the coincidence counter 32 via the OR circuit 39. As a result, the synchronization detection counter 34 and the coincidence counter 32 are reset.

After that, as shown in step B21 of FIG. 13, it is judged whether or not the vertical synchronizing signal φv is sent from the sync separation circuit 234, and the 525-base counter 33 is operated until the vertical synchronizing signal φv is sent. Count up. When the vertical synchronization signal φv is sent, the vertical synchronization signal φv is input to the synchronization detection counter 34 via the NOR circuit 38, and the synchronization detection counter 34 is incremented by “+1” as shown in step B22.

Next, as shown in step B23, it is determined whether or not the count value of the coincidence counter 32 is "2", that is, whether or not the vertical synchronization signal φv sent from the synchronization separation circuit 234 has a correct cycle. To judge. If the vertical synchronizing signal φv has a correct cycle, the coincidence counter 32
Is counted up, the count value is "2"
Then, a "1" signal is output from its output terminal 01 and sent to the flip-flop 57 via the inverter 59, and the latch with synchronization, that is, the flip-flop 57 is set as shown in step B24. afterwards,
As shown in step B25, it is determined whether or not the content of the synchronization detection counter 34 is "7".

If the content of the coincidence counter 32 has not reached "2" in step B23, the process immediately goes to step B25 to determine whether or not the content of the synchronization detection counter 34 has become "7". .. If the content of the synchronization detection counter 34 has not reached "7", step B
Returning to step 21, the same processing is repeated. Then, when the content of the synchronization detection counter 34 becomes "7", it is determined whether or not the flip-flop 57 is set as shown in Step B26, that is, the count value of the synchronization detection counter 34 becomes "7". It is determined whether or not the count value of the counter 32 has become "2".

When the count value of the synchronization detection counter 34 becomes "7", a "1" signal is output from the output terminal 0 ₁ , and "0" is inverted by the inverter 55 and input to the NOR circuit 56. At this time, if the flip-flop 57 is set, the output signal "1" of the flip-flop 57 is set to the AND circuit 58.
Is input to the NOR circuit 56 via
The reset signal output from is held in the "0" state. At this time, the synchronous output of the AND circuit 58 is
As shown in step B27, the mute signal MU is sent to the audio circuit. The audio circuit prohibits audio output when the mute signal MU is "0", and resumes the audio output operation when the mute signal MU becomes "1".

[0069] Thereafter, when the count value of the synchronous detection counter 34 becomes "8", the output from the terminal 0 ₂ "1" signal is outputted is inputted to the NOR circuit 38, the synchronization detection counter 3
4 clock input is prohibited. The above is the vertical synchronization signal φ
When it is determined that v is normally received, the digital tuning control circuit 273 stops the clock of the tuning voltage counter 275 at this time, fixes the count value, and ends the tuning operation.

If the reception state does not become normal and the count value of the coincidence counter 32 does not reach "2" before the count value of the synchronization detection counter 34 reaches "7", the flip-flop 57 is set. Therefore, the output of the AND circuit 58 is held in the "0" state. In this state, when the count value of the synchronization detection counter 34 becomes "7" and the "1" signal is output from the output terminal 0 ₁ , the inverter 55 inverts it to "0" and inputs it to the NOR circuit 56. At this time, as described above, since the "0" signal is input from the AND circuit 58 to the NOR circuit 56, the NOR circuit 5
The reset signal R output from 6 becomes "1", and the quaternary counter 67 in the digital tuning control circuit 273 is reset. Therefore, the digital tuning control circuit 273 returns to step B5 and restarts the tuning operation.

Although the case where the up key 16a is operated has been described above, when the down key 16b is operated, the operation of the down key 16b is detected in step B2, and the down processing is performed in the same manner as the case of the up processing. Done.

At this time, the relationship between H and L output from the frequency detection circuit 26 and the tuning voltage counter 275 up,
The down relationship is just the opposite of the up processing.

Next, the tuning operation in the manual mode will be described with reference to the digital tuning control circuit 273 shown in FIG. 9 and the flowchart of FIG.

When selecting a desired channel in the manual mode, the up key 1 for tuning
Press and hold 6a or the down key 16b until the desired channel is received. When the manual mode is specified, the digital tuning control circuit 273
As shown in step C1 of FIG. 14, it is constantly checked whether or not the tuning key is operated, and if there is a key input, the up key 16a is displayed as shown in step C2.
Or not. If it is the up key 16a, as shown in step C8, a count-up signal is sent from the digital tuning control circuit 273 to the tuning voltage counter 275 to increment the content by "+8", and then the process proceeds to step C4 and the up key 16a is pressed. Judge whether it is continued or not. If the up key 16a is not pressed continuously, the process returns to step C1, but if it is pressed continuously, the process proceeds to step C5 to count 0.5 seconds.

That is, in the digital tuning control circuit 273 shown in FIG. 9, in the manual mode, the "1" signal is input to the NOR circuit 83 as the manual mode signal MANU, and the input from the decoder 79 to the AND circuit 69 is prohibited. There is. When the up key 16a is operated in this state, the one-shot up key signal UP (high level) is output from the key control circuit 272a, and the flip-flop 61 is set. This flip-flop 6
The set output of 1 is sent from the EX OR circuit 62 to the tuning voltage counter 275 as an up count command.

Further, the up-key signal UP is sent to the flip-flop 65 via the NOR circuit 63 and the NAND circuit 64.
Entered in. The flip-flop 65 reads the input signal in synchronization with the vertical synchronizing signal φv and outputs the vertical synchronizing signal φv.
Hold for 1 cycle of v (about 16 ms) and AND circuit 69
And the quaternary counter 67 is held in the reset state. When the quaternary counter 67 is reset, the output from the output terminal "3" of the decoder 79 becomes "0", and the reset state of the 64-ary counter 84 is released.
At this time, the clock pulse φ 3 is input to the 64-ary counter 84 via the clocked inverter 91.

Therefore, the 64-base counter 84 counts up at high speed by the clock pulse φ3, and while the output of the counter 65 is "1", that is, 8 times in one cycle of the vertical synchronizing signal φv. The pulse signal of is output. The output of the 64-base counter 84 is the AND circuit 69.
Tuning voltage counter 2 as a timing signal φB via
Sent to 75. As a result, the content of the tuning voltage counter 275 is incremented by "+8", and the count value is sent to the modulated wave creating circuit 277. The modulated wave generation circuit 277 modulates the count value of the tuning voltage counter 275 into a pulse width,
Output to the tuner tuning voltage control circuit 29 shown in FIG.

Then, as described above, the key control circuit 27
In 2a, it is determined whether or not the key is continuously pressed. If the key is not pressed continuously, the process returns to step C1. If the key is pressed continuously, the key control circuit 272a counts 0.5 seconds as shown in step C5. Output a signal.

This manual key presence signal is output while the key is pressed and is read into the flip-flop 65 via the NAND circuit 64. This flip-flop 65
Outputs the gate of the AND circuit 69, and the output of the 64-bit counter 84 is sent to the tuning voltage counter 275 as a clock pulse φB. As a result, step C6
The tuning voltage counter 275 is counted up as shown in FIG. Next, as shown in step C7, it is determined whether or not the key operation is continuously performed. If the key operation is performed, the process returns to step C6 and the 64-base counter 8
With the output of 4, the count-up operation of the tuning voltage counter 275 is continued.

Therefore, the AND circuit 88 is supplied with the signal M from the latch circuit 41 shown in FIG. This signal M has a high level when there is synchronization, and has a low level when there is no synchronization. When the synchronization signal present signal M is sent as the tuning voltage counter 275 counts up, the AND circuit The threshold of 88 becomes "1", the gate of the clocked inverter 90 is opened, and the clock pulse .phi.4 having a low frequency is input to the 64-bit counter 84. This makes the 64-bit counter 8
The count-up operation of 4 becomes slow, and the sweep speed of the tuner tuning voltage is switched to low speed. That is, since the sync signal is detected when the channels match, the signal M
Becomes a high level, the sweep speed of the tuner tuning voltage becomes slow, and when the channel is separated from the channel, the synchronizing signal is no longer detected. Therefore, the signal M becomes a low level and the sweep speed of the tuner tuning voltage becomes faster.

When the desired channel is selected by the sweep of the tuner tuning voltage, the up key 16a
When the hand is released from, the counting operation of the tuning voltage counter 275 is stopped as shown in step C8. That is, when the up key 16a is released, the key signal is "0".
Then, "0" is read into the flip-flop 65.
As a result, the threshold of the flip-flop 65 becomes "0" and the gate of the AND circuit 69 is closed, and the tuning voltage counter 2
The output of the clock pulse φB to 75 is prohibited. As a result, the count-up operation of the tuning voltage counter 275 stops, and the tuning operation ends.

When the down key 16b is operated, the operation of the down key 16b is detected in step C2, and the process proceeds to step C9. In this step C9,
The EX OR circuit 62 outputs a down count command to set the tuning voltage counter 275 to "-8".

Then, as shown in step C10, it is determined whether or not the down key 16b is continuously pressed. If the key is not continuously pressed, the process returns to step C1. If the down key 16b is continuously pressed, the key control circuit 272a counts 0.5 seconds as shown in step C11, and then the tuning voltage counter 275 is counted down as shown in step C12. Next, as shown in step C13, it is determined whether or not the key operation has been completed, and if the key has not been pressed, the process returns to step C12 to continue the countdown operation of the tuning voltage counter 275.

Then, when the end of the key operation is detected in step C13, the counting operation of the tuning voltage counter 275 is stopped and the tuning operation is ended, as shown in step C8.

The set values of the counters in the tuning voltage counter 275 are not limited to those in the above embodiment, and may be set to other values.

Further, the present invention can be applied not only to the television but also to a radio or the like.

[0087]

As described above, according to the present invention,
When the number of coincidences between the sync signal and the internal sync signal is counted more than a predetermined number of times and it is determined that the radio wave condition is good, the sync signal and the internal sync signal are almost in agreement, so display drive control is performed based on only the internal sync signal. When the number of mismatches between the sync signal and the internal sync signal is counted more than a predetermined number of times and it is determined that the radio wave condition is bad, the sync signal and the internal sync signal are significantly out of sync. By performing display drive control based on the addition signal, it is possible to prevent the phases of the internal synchronizing signal and the synchronizing signal from deviating from each other and obtain a stable image.

[Brief description of drawings]

FIG. 1 is an external configuration diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of an electronic circuit showing an embodiment of the present invention.

FIG. 3 is a block diagram showing details of an electronic tuning tuner according to an embodiment of the present invention.

FIG. 4 is a block diagram showing details of a television linear circuit showing an embodiment of the present invention.

FIG. 5 is a block diagram showing details of a frequency detection circuit according to an embodiment of the present invention.

6 is a timing chart for explaining the operation of the frequency detection circuit of FIG.

FIG. 7 is a block diagram showing details of a control circuit.

8 is a block diagram showing details of a frequency detection circuit portion in FIG.

9 is a block diagram showing details of a digital tuning control circuit portion in FIG.

FIG. 10 is a flowchart showing a synchronization detection operation.

FIG. 11 is a timing chart for explaining a synchronization detection circuit.

FIG. 12 is a flowchart showing an auto tuning operation in the auto mode.

FIG. 13 is a flowchart showing an auto tuning operation in the auto mode.

FIG. 14 is a flowchart showing an auto tuning operation in a manual mode.

[Explanation of symbols]

11 ... Case, 12 ... Image display part, 13 ... Channel display part, 14 ... Volume display part, 15 ... Display panel, 16a ...
Tuning up key, 16b ... Down key, 1
7a ... Up key for volume adjustment, 17b ... Down key,
18 ... Auto / manual switch, 19 ... VHF
/ UHF selector switch, 20 ... power switch, 21 ... antenna, 22 ... electronic tuning tuner, 23 ... television linear circuit, 24 ... A / D converter, 25 ... liquid crystal drive circuit, 26
... Frequency detection circuit, 27 ... Control circuit, 28 ... Key input section, 29 ... Tuner tuning voltage control circuit, 221 ... Antenna coupling circuit, 222 ... High frequency coupling circuit, 223 ... Mixing circuit, 224 ... Local oscillation circuit, 231 ... Intermediate Frequency amplification circuit, 232 ... Detection circuit, 233 ... Video amplification circuit, 234
... Synchronous separation circuit, 261, ... Frequency discriminator, 262,26
3 ... Comparator, 264, 265 ... Reference power supply, 271
... reference clock generation circuit, 272 ... key control circuit, 27
3 ... Digital tuning control circuit, 274 ... Synchronous detection circuit, 275 ... Tuning voltage counter, 276 ... Memory,
277 ... Modulation wave creating circuit, 278 ... Volume display circuit / channel display circuit, 279 ... Display control circuit, 2710 ...
4-bit counter, 2711 ... D / A converter, 31 ... Mismatch counter, 32 ... Match counter, 33 ... 525-ary counter, 34 ... Sync detection counter, 36, 41 ... Latch circuit, 67 ... 4-ary counter, 79 ... Decoder , 84 ... 6
Quaternary counter.

Front Page Continuation (72) Inventor Koji Yamagishi 3-2-1 Sakaemachi, Hamura-cho, Nishitama-gun, Tokyo Casio Computer Co., Ltd. Hamura Technical Center

Claims (1)

Claim: What is claimed is: 1. A sync separating means for separating a sync signal from a television signal, and an internal sync signal generating means for generating an internal sync signal of the same frequency as the sync signal based on a reference clock signal. When the coincidence detection unit that counts the number of times the synchronization signal matches the internal synchronization signal, the mismatch detection unit that counts the number of times the synchronization signal and the internal synchronization signal do not match, Set reset means that is set and is reset when the mismatch detection means counts a mismatch for a predetermined number of times, and when the set reset means is set, a display control operation is performed according to the internal synchronization signal, and the set reset means When reset, the display control operation is performed according to the OR addition signal of the sync signal and the internal sync signal. Synchronization control circuit, characterized in that was provided and Nau display control means.