JPH0661985A - Redundant system switching control system - Google Patents

Abstract

PURPOSE:To omit a system switching control unit or the like, and to attain a simple and economical constitution concerning the redundant system switching control system of a redundant system for improving a reliability. CONSTITUTION:A redundant system equipped with a 0 system device 0 and a 1 system device 1 for a single or plural devices 2, which executes a processing by using clock signals CLK obtained by selecting and outputting clock signals CLK0 and CLK1 by selectors 5 of each device 2, is provided with switching settlement control parts 3 and 4. The switching settlement control parts 3 and 4 mutually transfer state information such as switching control states, receive the state information such as an alarm signal from the device 2, output a switching control signal based on both the state information of its own system and the other system, and the state information such as the alarm signal of the device 2, and add it through switching control signal lines 6 and 7 to the selector 5 of the device 2. The selector 5 operates the system switching of the 0 system device 0 and the 1 system device 1 according to the switching signals of both the systems.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant system switching control system in a redundant system for improving reliability.
In a system that requires high reliability, a redundant configuration is generally used. In that case, for example, only the important devices such as the clock supply unit and the main signal processing unit in the communication system are made into a redundant configuration to achieve economic efficiency, and the redundant system is switched at high speed when a failure occurs to minimize the spread of the failure. It is requested to stop as much as possible.

[0002]

2. Description of the Related Art A clock supply system in a communication system has, for example, the configuration shown in FIG.
Is a 0-system clock supply unit, 41 is a 1-system clock supply unit, 42-1 to 42-n are devices for receiving a clock signal and performing communication processing, 43 is a system switching control unit, 44-0, 44-1 Is a clock generator, 45-0,
45-1 is a gate circuit, 46-1 to 46-n are selectors (SEL), 47 and 48 are clock signal lines, and 49 and 50.
Is an alarm signal line, and 51 and 52 are switching control signal lines.

For example, assuming that the 0-system clock supply unit 40 is the active system and the 1-system clock supply unit 41 is the standby system, the system switching control unit 43 has the switching control signal line 5
1 to open the gate circuit 45-0,
-1 is controlled to be closed, and each device 42-1 to 42-2
The -n selectors 46-1 to 46-n are controlled to select the clock signal from the 0-system clock supply unit 40 via the switching control signal line 52. Accordingly, each of the devices 42-1 to 42-n has the 0-system clock supply unit 4
Communication processing will be performed based on the clock signal from 0.

In such a state, when the system switching control unit 43 receives an alarm signal indicating that the clock signal from the 0 system clock supply unit 40 is disconnected via the alarm signal line 49, the switching control is performed. The gate circuit 45-0 is closed via the signal line 51, and the gate circuit 45-1 is closed.
Is controlled so that the selectors 46-1 to 46-n select the clock signal from the 1-system clock supply unit 41 via the switching control signal line 52.
That is, the redundant system is switched with the 0 system as the standby system and the 1 system as the active system.

[0005]

In the above-mentioned conventional example, the 0-system clock supply unit 40, the 1-system clock supply unit 41 and the other device 42 are used for the redundant system switching control.
In addition to -1 to 42-n, a system switching control unit 43 is required, and alarm signal lines 49, 5 are provided between this system switching control unit 43 and each device 42-1 to 42-n.
The 0 and the switching control signal line 52 must be installed, and the switching control signal line 51 must be installed between the 0-system clock supply unit 40 and the 1-system clock supply unit 41. Therefore, there is a drawback that the system becomes large in size, and that the number of wirings increases and the structure becomes complicated. It is an object of the present invention to omit a system switching control unit and the like to provide a simple and economical structure.

[0006]

A redundant system switching control system according to the present invention will be described with reference to FIG. 1. The redundant system switching control system is provided with a 0-system device 0 and a 1-system device 1 for a single or a plurality of devices 2. In the redundant system, switching system control units 3 and 4 are provided in the 0 system device 1 and the 1 system device 1, and the state information of the own system device is mutually transferred between the switching system control units 3 and 4. Based on the status information of the own system, the status information transferred from the other system device, and the status information from one or a plurality of devices 2, the switching agreement control units 3 and 4 are set to 0. A system switching control signal is sent between the system devices 0 and 1 to perform system switching.

[0007]

A 0-system device 0 and a 1-system device 1 constitute a redundant system, and, for example, a clock signal CLK0 from the 0-system device 0 and a clock signal CLK1 from the 1-system device 1 are supplied to each device 2
Add to selector 5. The selector 5 is controlled via the switching control signal lines 6 and 7 from the switching agreement control units 3 and 4, and the state information is mutually transferred between the switching agreement control units 3 and 4. Further, the switching agreement control units 3 and 4 receive status information such as an alarm signal due to detection of a clock signal disconnection from each device 2. When the switching talk control units 3 and 4 receive such an alarm signal, the state information is transferred between the switching talk control units 3 and 4 to switch to either the 0-system or the 1-system, or to maintain the current state. Is determined and the selector 5 is controlled to switch the system.

[0008]

FIG. 2 is an explanatory view of an embodiment of the present invention.
Reference numerals 0 and 11 denote a 0-system clock supply unit and a 1-system clock supply unit, 12-1 to 12-n denote devices that perform processing in accordance with a clock signal, 13 and 14 denote a switching agreement control unit, 1
5-1 to 15-n are selectors (SEL), 16-1 to 1
6-n is a disconnection detector, 17-1 to 17-n are flip-flops, 18-1 to 18-n are decode circuits, 19-0,
Reference numeral 19-1 is a clock generator, 20-0 and 20-1 are failure state decoding circuits, 21-0 and 21-1 are self-selection request decoding circuits, 22 and 23 are clock signal lines, and 24 and 2
5 is an outreach signal line, 26 and 27 are alarm signal lines, 28,
Reference numeral 29 is a switching control signal line, 30-0 and 30-1 are power-on reset signal lines in the unit, and 31-0 and 31-1 are self-monitoring signal lines.

The 0-system clock supply unit 10 and the 1-system clock supply unit 11 correspond to the redundant system composed of the 0-system device 0 and the 1-system device 1 of FIG.
Reference numeral 4 corresponds to the switching agreement control units 3 and 4 in FIG. The switching agreement control units 13 and 14 include the failure state decoding circuit 20.
-0, 20-1 and self-selection request decoding circuit 21-0,
21-1 and 21-1 are connected to each other by the outreach signal lines 24 and 25, and the state information is transferred.

The clock signal from the clock generator 19-0 of the 0-system clock supply unit 10 and the clock signal from the clock generator 19-1 of the 1-system clock supply unit 11 are transmitted via the clock signal lines 22 and 23. Are added to the selectors 15-1 to 15-n of the respective devices 12-1 to 12-n, and the selectors 15-1 to 15-n are controlled by the output signals of the terminals Q of the flip-flops 17-1 to 17-n. The clock signal from either one is selectively output.

The decoding circuits 18-1 to 18-n are composed of AND circuits and inverters, and decode the switching control signals from the switching agreement control units 13 and 14 via the switching control signal lines 28 and 29. Flip-flop 17-1 to
17-n. For example, if the switching control signal from the switching agreement control unit 13 is "1" and the switching control signal from the switching agreement control unit 14 is "0", the decoding circuit 18-
1 to 18-n to flip-flops 17-1 to 17-n
"0" for the set terminal S and "1" for the reset terminal R
Of the flip-flops 17-1 to 17-n from the terminals Q of the selector 1
A control signal of "0" is added to 5-1 to 15-n, and the selectors 15-1 to 15-n are in the 1-system clock supply unit 1
The clock signal from 1 is selectively output. When the set output S of the flip-flops 17-1 to 17-n is set by adding the decode output signal of "1", the control signal of "1" is sent from the terminal Q to the selectors 15-1 to 15-n. In addition, the clock signal from the 0-system clock supply unit 10 is selectively output.

The disconnection detectors 16-1 to 16-n are composed of a 0-system clock supply unit 10 and a 1-system clock supply unit 1.
1 to monitor the clock signal supplied via the clock signal lines 22 and 23 and switch the alarm signal via the alarm signal lines 26 and 27 by detecting the disconnection.
It is added to the failure state decoding circuits 20-0 and 20-1 of 3,14. This failure state decoding circuit 20-
0 and 20-1 include self-monitoring signal lines 31-0 and 31-1.
An alarm signal in the own system clock supply unit is added via.

FIG. 3 is an explanatory view of the control logic of the embodiment of the present invention, in which (A) shows the control logic of the switching notice control units 13 and 14, * PONR is a power-on reset signal, and * DWN.
Y is an alarm signal due to the disconnection of the clock signal of other system, * DW
NM is an alarm signal due to the disconnection of its own clock signal, * S
ELY is a switching control signal of another system, and * SELM is a switching control signal of its own system. Further, (B) shows the switching control logic of the clock signal on the side of the devices 12-1 to 12-n, and * SEL1 is 1
Switching control signal from the system clock supply unit 11, * S
EL0 indicates a switching control signal from the 0-system clock supply unit 10. The holding of the selection system indicates that the current state is held, and the 0 system and the 1 system are switched to the 0 system and the 1 system, respectively.

The power-on reset signal * RONR in the 0-system clock supply unit 10 and the 1-system clock supply unit 11 is the power-on reset signal line 30-0,
30-1 through the self-selection request decoding circuit 21-0,
20-1 and this power-on reset signal * R
When ONR is low level L, the switching control signal * SELM of high level H is unconditionally transmitted via the switching control signal lines 28 and 29. The power-on reset signal * PONR in each of the devices 12-1 to 12-n is not shown in FIG.

When the 0-system clock supply unit 10 or the 1-system clock supply unit 11 is powered on,
The power-on reset signal * PONR becomes low level L, and the self-selection request decoding circuits 21-0 and 21-1 of the switching agreement control units 13 and 14 output the high level H own switching control signal * SELM. For example, when the 0-system clock supply unit 10 is powered on, a high-level H signal is output from the self-selection request decoding circuit 21-0 of the switching notice control unit 13, and each device 12 is output via the switching control signal line 28. Switching control signal * SE for -1 to 12-n
L0 is added, and the switching notice control unit 14 of the 1-system clock supply unit 11 is transmitted via the notice signal line 24.
Is added to the self-selection request decoding circuit 21-1 as a switching control signal * SELY of another system. After power-on reset, power-on reset signal * PONR is high level H
Becomes In addition, the 0-system clock supply unit 10 and the 1-system clock supply unit 11 are packaged to enable hot plugging and unplugging by selecting the shape of the connector pin, etc., and when the plug is inserted, the power supply pin comes into final contact and automatically powers It is also possible to adopt a configuration in which on-reset is performed.

Each of the devices 12-1 to 12-n has a switching control signal * SEL1 applied via the switching control signal line 29 when the switching control signal * SEL0 of high level H is applied.
Is high level H, the state immediately before that is maintained, and if low level L, the clock signal from the 1-system clock supply unit 11 is selected. That is, in the decoding circuits 18-1 to 18-n, the switching control signal * SEL0 applied via the switching control signal line 28 is “1”,
Switching control signal * applied via the switching control signal line 29
When SEL1 is "1", the flip-flop 17-1
A signal of "0" is applied to both the set terminal S and the reset terminal R of 17 to 17-n, and the flip-flop 17-1
Since the state of the terminal Q of ~ 17-n does not change, the selected state of the selectors 15-1 to 15-n is held. Similarly,
If the switching control signals * SEL0 and * SEL1 are both "0" (low level L), the decoding circuits 18-1 to 18-
Since the signal "0" is applied to both the set terminal S and the reset terminal R of the flip-flops 17-1 to 17-n from n, the states of the flip-flops 17-1 to 17-n do not change.

When the switching control signal * SEL1 applied via the switching control signal line 29 is "0", the decoding circuits 18-1 to 18-n to the flip-flops 17-1 to 17-1.
The signal "1" is applied to the reset terminal R of 17-n, and the flip-flops 17-1 to 17-n are reset. Therefore, the signals of "0" are output from the terminals Q of the flip-flops 17-1 to 17-n to the selectors 15-1 to 15-n.
Therefore, the selectors 15-1 to 15-n selectively output the clock signal of the 1-system clock supply unit 11 added via the clock signal line 23. If the switching control signal * SEL0 is "0" and the switching control signal * SEL1 is "1", the decoding circuits 18-1 to 18-1.
The signal "1" is applied to the set terminals S of the flip-flops 17-1 to 17-n from 18-n to be set, and the terminal Q becomes "1".

When the terminals Q of the flip-flops 17-1 to 17-n are "0", the selectors 15-1 to 15-n have 1s.
The clock signal of the system clock supply unit 11 is selectively output. In this state, the switching negotiation control unit 13 of the 0 system clock supply unit 10 outputs * PONR.
= H, * DWNY = H, * DWNM = H, * SELY =
L, * SELM = H, and in the switching agreement control unit 14 of the 1-system clock supply unit 11, * PONR = H, *
DWNY = H, * DWNM = H, * SELY = H, * S
ELM = L. 0 system clock supply unit 1
The switching control signal * SELM of 0 is the switching control signal * SE of the 1-system clock supply unit 11 via the negotiation signal line 24.
LY, and the switching control signal * SELM of the 1-system clock supply unit 11 becomes the switching control signal * SELY of the 0-system clock supply unit 10 via the negotiation signal line 25.

In this state, the disconnection detectors 16-1 to 16-1
When the disconnection of the clock signal applied via the clock signal line 22 is detected at 6-n, the alarm signal is sent out via the alarm signal line 26. 0 system clock supply unit 1
At 0, this alarm signal is used as the alarm signal * DWNM for detecting the clock signal disconnection of the own system and the failure state decoding circuit 2
0-2, and in the 1-system clock supply unit 11, it is added to the failure state decoding circuit 20-1 as the alarm signal * DWNY for detecting the clock signal disconnection of the other system. Therefore, the 0-system clock supply unit 10
Then, * PONR = H, * DWNY = H, * DWNM =
Since L and * SELY = L, it means that * SELM = H, and in the 1-system clock supply unit 11, *
PONR = H, * DWNY = L, * DWNM = H, * S
Since ELY = H, * SELM = L. Therefore, in each of the devices 12-1 to 12-n, *
PONR = H, * SEL1 = L, * SEL0 = H, and the state of switching to the 1-system continues. That is, since the unselected clock signal is disconnected, the previous state is retained.

When the disconnection detectors 16-1 to 16-n detect disconnection of the clock signal applied via the clock signal line 23, the 0-system clock supply unit 10 has * PONR = H, *. DWNY = L, * DWNM =
Since H and * SELY = L, * SELM = L, and in the 1-system clock supply unit 11, * SELM = L
PONR = H, * DWNY = H, * DWNM = L, * S
Since ELY = H, * SELM = L. However, since the switching control signal * SELM = L from the switching negotiation control unit 13 of the 0-system clock supply unit 10, the negotiation signal line 2
4 is transferred to the switching agreement control unit 14 of the 1-system clock supply unit 11, and * PONR = H, * DWNY =
H, * DWNM = L, * SELY = L, so that * SELM = H. The switching control signal * SELM = H is also transferred to the switching negotiation control unit 13 of the 0-system clock supply unit 10 via the negotiation signal line 25.
Therefore, in each of the devices 12-1 to 12-n, * PO
NR = H, * SEL1 = H, * SEL0 = L, 0
It will be switched to the system.

When the disconnection detectors 16-1 to 16-n detect disconnection of the clock signal applied via the clock signal lines 22 and 23, * DWNY = L, * DWNM =
It becomes L, and in that case, * SELM = $. That is,
0 system clock supply unit 10 so that 0 system can be selected
Then, * SELM = L, and 1-system clock supply unit 1
In the case of 1, * SELM = H. This is to prevent the system switching control in each of the devices 12-1 to 12-n from becoming unstable due to the disconnection of the clock signal between the 0 system and the 1 system. The alarm signals in the 0-system clock supply unit 10 and the 1-system clock supply unit 11 are the same as the own system clock signal disconnection detection signal in the failure state decoding circuit 2.
In addition to 0-0, 20-1, the above-mentioned alarm signal *
The determination is made according to the logic of the DWNM.

As described above, the switching agreement control units 13 and 14 according to the control logic of FIG. 3A are provided and the status information is mutually transferred to judge the status of the system switching. A switching control signal can be output. Further, in each of the devices 12-1 to 12-n, simple decoding circuits 18-1 to 18-n according to the control logic shown in FIG.
It is possible to switch between the 0-system and the 1-system simply by providing. Therefore, the switching agreement control units 13 and 14 and the decoding circuits 18-1 to 18-n are not limited to the above-described embodiments, and various logical configurations can be adopted, and high speed operation is possible. It is possible to switch the system.

[0023]

As described above, according to the present invention, the 0-system device 0 such as the 0-system clock supply unit 10 and the 1-system device 1 such as the 1-system clock supply unit 11 are provided with the switching agreement control unit 3, 3. 4 are provided to mutually transfer the status information such as the switching control status, the status information of the own system apparatus and the status information of the other system apparatus,
A system switching control signal is sent to another device 2 based on status information such as an alarm signal from another device 2 connected to the system device 0 and the system device 1, as in the conventional example. Does not require a dedicated system switching control unit and is 0
Since it is only necessary to provide a small amount of signal lines between the system devices 0 and 1 and the system device 1, there is an advantage that the configuration is simple and economical.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of an example of the present invention.

FIG. 3 is a control logic explanatory diagram of the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 0 0 system device 1 1 system device 2 device 3,4 switching agreement control unit 5 selector 6,7 switching control signal line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H04L 12/48 (72) Inventor Hiroshi Yamazaki 1015 Uedodaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (72) Inventor Nobuaki Ouchi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (1)

[Claims] 1. A redundant system comprising a 0-system device (0) and a 1-system device (1) for a single or a plurality of devices (2), wherein the 0-system device (0) and the 0-system device (0) A switching talk control unit (3, 4) is provided in the 1-system device (1), and the switching talk control unit (3, 4)
The state information of the own system device is mutually transferred between the two devices, and the switching agreement control unit (3, 4) uses the single or the state information of the own system device and the state information transferred from the other system device. Redundancy characterized by transmitting a control signal for system switching between the 0-system device (0) and the 1-system device (1) to the device (2) based on the status information from the plurality of devices (2) Switching control method.