JPH0661856A - A/d converter - Google Patents

Abstract

PURPOSE:To calculate accurate phase data always by using an A/D converter circuit to sample an analog signal for a period of a data sampling clock and A/D-converting the sampled analog signal for a period of a data output clock so as to obtain a digital signal. CONSTITUTION:When an analog interference wave (frequency f0 is 2v/lambda) is outputted from a photodetector 1a of a laser interferrometer 1, the interference wave is outputted to an A/D conversion circuit 2 and a comparator 3. Then an analog interference wave from the comparator 3 and a reference clock signal being a rectangular wave whose phase is synchronously with the interference wave are inputted to a PLL circuit 4 and its output is fed to NAND gates 5, 6, from which a data output clock (e.g. f=2f0) and a data sample pulse (e.g. f=2f0) are respectively fed to the A/D conversion circuit 2. Then the circuit 2 converts the analog interference wave into a digital signal for each prescribed phase. Thus, the accurate phase data are always calculated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter for converting an analog interference wave output from a laser interferometer into a digital interference wave.

[0002]

2. Description of the Related Art Conventionally, an interferometer for detecting a distance to an object without contact has been known. In this interferometer, a part of the laser light is applied to the object as object light, the remaining laser light is used as reference light, and the position of the object is determined from the phase difference between the object light reflected by the object and the reference light. ing. In order to detect this phase difference, a reference surface composed of a mirror called a corner cube, which reflects the object light and the reference light, respectively, and guides them to the photodetector is used, and the reference surface is vibrated or translated. By modulating the optical signal, the phase of the object light is detected from the modulated signal. However, such an interferometer has a drawback that a correct modulation signal cannot be obtained when the moving speed and the position of the reference surface change, and the position cannot be accurately measured.

Therefore, the applicant of the present invention has applied for an interferometer capable of detecting a correct position without being affected by fluctuations in the moving speed or the position of the reference surface, even if the moving speed or position changes. The interferometer of this prior application splits laser light into object light and reference light, irradiates a corner cube fixed to an object to be measured with the object light, and creates two reflected object light reflected waves by the corner cube. The reference light is applied to two corner cubes of the optical block which are separated into the optical paths and which are vibrated by driving an actuator, and two reference light reflected waves are obtained from the reflected light from the two corner cubes to obtain one object. The light reflected wave and the reference light reflected wave are combined together, the other object light reflected wave and the reference light reflected wave are combined together, and the respective combined lights are photoelectrically converted to calculate the output.

At this time, the reference light reflected wave is frequency-shifted in proportion to the vibration speed of the actuator due to the Doppler effect (Δf = 2v / λ, v is the vibration speed of the actuator, and λ is the wavelength of the laser light). Therefore, interference fringes are formed in the combined light obtained by combining the reflected lights of the corner cube and the optical block, and the photoelectric conversion of the interference fringes produces an interference wave (f ₀ = Δf = 2v / λ) due to the heterodyne phenomenon. Becomes

[0005]

The frequency of this interference wave is proportional to the vibration speed of the actuator, but in A / D converting this interference wave, a data sampling clock of an arbitrary cycle oscillated from a crystal oscillator or the like and When A / D conversion is performed with the data output clock, the interference wave is sampled for each asynchronous random phase and digitized. When the digital signal sampled for each random phase is input to the computer, accurate phase data cannot be calculated, and it becomes difficult to realize a highly accurate laser interferometer.

The present invention has been made in view of the above-mentioned problems. Even if the vibration speed of the actuator changes and the frequency of the interference wave changes, accurate phase data can always be calculated. For example, a laser interferometer. An object of the present invention is to provide an A / D converter that can realize a highly accurate laser interferometer when applied to.

[0007]

In order to achieve the above-mentioned object, the present invention is an A / D converter for converting an analog signal into a digital signal, wherein the frequency of the analog signal is based on the analog signal. Reference clock generation means for generating a reference clock signal of the same frequency, PLL means for generating a data sampling clock and a data output clock based on the reference clock signal, and sampling the analog signal based on the data sampling clock And an A / D conversion circuit for converting the sampled analog signal into a digital signal based on the data output clock.

In the present invention, the PLL means includes a phase detector, a DC filter for extracting a DC component from an output signal of the phase detector, and an output signal of the phase detector extracted by the DC filter. An integrator that integrates a DC component, a voltage-controlled oscillator that oscillates according to the output voltage of the integrator, and a frequency-divided N that outputs a plurality of signals with different frequencies that are 1 / M times the output signal of the voltage-controlled oscillator. Vessel (M ≦ N,
M and N are integers), and the phase detector outputs the reference clock signal and a feedback clock signal that is one of the output signals of the N frequency divider and has the same frequency as the reference clock signal. It was decided to detect by comparison. Further, the present invention provides
The N is 16, and the output signal of the N frequency divider has a frequency that is 1, 2, 4, or 8 times the frequency of the reference clock signal.

[0009]

According to the present invention, sampling of an analog signal by the A / D conversion circuit or conversion into a digital signal is generated by the PLL means based on the analog signal or the reference clock generating means of the same frequency as the analog signal. Since it is performed based on the clock cycle of the sampling clock and the data output clock, even if the frequency of the analog signal fluctuates, A / D conversion of the analog signal can always be performed in synchronization with the cycle of the analog signal. it can.
Therefore, for example, when applied to a laser interferometer, a highly accurate laser interferometer can be realized.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an A / D converter according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a laser interferometer. It is provided. Photo detector 1
The combined light detected in a is, for example, as follows.

First, a laser beam output from a light source is separated into an object light and a reference light by a polarization beam splitter, and the object light is radiated to a corner cube fixed to an object to be measured, and the corner cube is radiated. The object light reflected wave reflected by is obtained. On the other hand, the reference light is applied to the optical block that is vibrated by driving the actuator, and the reference light reflected wave reflected by the optical block is obtained. And
The object light reflected wave and the reference light reflected wave are combined to obtain combined light, and the combined light is detected by the photodetector 1 a of the laser interferometer 1.

Since the reflected wave of the reference light is the light reflected by the optical block which is vibrated by driving the actuator, the Doppler effect acts and the frequency shifts in proportion to the vibration speed of the actuator (Δf = 2v /
(λ, v are the vibration speed of the actuator, and λ is the wavelength of the laser beam). Therefore, when the photodetector 1a of the laser interferometer 1 receives the combined light and converts it into an electric signal, an analog interference wave (frequency f ₀ = 2v / λ) is obtained.

This analog interference wave is input to the A / D conversion circuit 2 and also to the comparator 3, as shown in FIG. In the comparator 3, the level of the input analog interference wave is compared with a predetermined level, and a signal corresponding to the comparison result is a reference clock signal (frequency f = f ₀ ).
Is output as. The reference clock signal is PLL (Ph
ase Lock Loop) is input to one input terminal R of the phase detector 4a provided in the circuit 4, and the other input terminal V of the phase detector 4a is supplied from an N divider 4b (N is an integer) described later. The output feedback clock signal (frequency f = f ₀ ) is input. The phase detector 4a compares the phases of the reference clock signal and the feedback clock signal, and outputs a signal indicating the deviation thereof to the DC filter 4c.

In the DC filter 4c, the DC component of the deviation signal output from the phase detector 4a is extracted, and the DC component of the extracted deviation signal is subjected to voltage control via the operational amplifier 4d and the integrating circuit 4f by the capacitor 4e. It is applied to an oscillator (hereinafter referred to as VCO) 4g. Accordingly, the frequency f = where the output voltage of the integrating circuit 4f is controlled is f =
The VCO 4g oscillates at Nf ₀ , and this oscillation signal is output to the N frequency divider 4b.

The N frequency divider 4b divides the oscillation signal output from the VCO 4g by N / M times (M≤N, M is an integer). It should be noted that in the present embodiment, the VCO 4 is divided by the N frequency divider 4b.
The oscillation signal output by g is divided by 2, 4, 8 and 16 times. Therefore, f = (N / 2) f ₀ from the N frequency divider 4b.
(Divided output by 2), f = (N / 4) f ₀ (divided output by 4),
f = (N / 8) f ₀ (8 frequency division output), f = (N / 16)
Clocks of four frequencies of f ₀ (16 frequency division output) are output. Further, for convenience of the following description, the value of N is set to N = 16 from here on. However, this value is merely an example, and the actual value of N can be set to an arbitrary natural number.

Now, of the clocks output from the N frequency divider 4b, the frequencies are f = (N / 8) f ₀ = 2f ₀ , f =
(N / 4) f ₀ = 4f ₀ , f = (N / 2) f ₀ = 8f ₀
Is a 3-input NAND gate 5
Is input to the first to third input terminals of
It is input to the first to third input terminals of the input NAND gate 6. Further, among the clocks output from the N frequency divider 4b, the clock whose frequency is f = (N / 16) f ₀ = f ₀ is fed back to the other input terminal V of the phase detector 4a as a feedback clock signal. To be done.

The second input terminal of the NAND gate 6 is supplied with the clock after the clock having the frequency f = (N / 4) f ₀ = 4f ₀ is inverted by the inverter 7. Therefore, from the NAND gate 5, the frequencies f = 2f ₀ and f =
A data output clock having a frequency f = 2f ₀ obtained by NANDing each clock of 4f ₀ and f = 8f ₀ is output and input to the output clock terminal A / D of the A / D conversion circuit 2. From the NAND gate 6, the frequency f = 2
A data sampling clock of frequency f = 2f ₀ obtained by NANDing the inverted clocks of f ₀ and f = 4f ₀ and each clock of f = 8f ₀ is output, and the A / D conversion circuit 2
Of the sampling clock terminal S / H.

In the A / D conversion circuit 2, the frequency f = of the data sampling clock output from the NAND gate 6
At a cycle of 2f ₀ , an analog interference wave (frequency f ₀ = 2v / λ) output from the photodetector 1a of the laser interferometer 1 is sampled, and the sampled digital signal is
The data output clock output from the NAND gate 5 is A / D converted in a cycle of frequency f = 2f ₀ and output to a computer (not shown).

Next, the operation will be described with reference to the timing chart of FIG. Photodetector 1 of laser interferometer 1
When an analog interference wave (frequency f ₀ = 2v / λ) having a waveform as shown in FIG. 2A is output from a, the interference wave is output to the A / D conversion circuit 2 and the comparator 3. To be done. In the comparator 3, the interference wave from the photodetector 1a is compared with a predetermined level, and the comparator 3 compares the interference wave with the analog interference wave in FIG. 2A with a phase as shown in FIG. 2B. The synchronized rectangular wave reference clock signal is input to one input terminal R of the phase detector 4 a of the PLL circuit 4. In contrast,
The other input terminal V of the phase detector 4a is connected to the N frequency divider 4b.
A feedback clock signal as shown in FIG. The waveform of this feedback clock signal will be described in detail later.

The phase detector 4a detects the phase difference between the reference clock signal and the feedback clock signal, and among the signals indicating the deviation between the reference clock signal and the feedback clock signal output from the phase detector 4a. The DC component is extracted by the DC filter 4c, and is further integrated by the integrating circuit 4f including the operational amplifier 4d and the capacitor 4e to obtain the VCO4.
applied to g. The VCO 4g oscillates at the frequency of the integrated voltage of the integrating circuit 4f, and its oscillation signal is output to the N frequency divider 4b.

Since the frequencies of the reference clock signal and the feedback clock signal are both f = f ₀ , PL
The L circuit 4 is phase-locked with a constant phase difference. Further, the oscillation signal of the VCO 4g is divided by N / 16 times (where N = 16) by the N divider 4b to become a feedback clock signal of frequency f = f ₀ , and the other input terminal of the phase detector 4a. Since it is applied to V, the frequency of the oscillation signal of the VCO 4g is f = 16f ₀ , and f = Nf ₀ in the general formula.

In the N frequency divider 4b, the signal of the frequency f = Nf ₀ output from the VCO 4g is divided by 8 and divided by 2 and divided into the signals of FIGS. 2 (d), 2 (e) and 2 (f). As shown in FIG. 4, a digital waveform divided by 8 output f = 2f ₀ , 4 divided output f = 4f
₀ , the frequency-divided output f = 8f ₀ is output. These divided-by-8 outputs f = 2f ₀ , divided-by-4 outputs f = 4f ₀ , divided-by-2 outputs f
The digital signal of = 8f ₀ is input to the first to third input terminals of the NAND gate 5, and by taking the NANDs thereof, the output terminal of the NAND gate 5 outputs the signal shown in FIG.
Data output clock as shown in (frequency f = 2f ₀ ).
Is output.

The digital signals of the divide-by-8 output f = 2f ₀ and the divide-by-2 output f = 8f ₀ output from the N divider 4b are input to the first and third input terminals of the NAND gate 6, The divide-by-4 output f = 4f ₀ is inverted by the inverter 7 and input to the second input terminal of the NAND gate 6. Therefore, the NAND gate 6 outputs those divided by 8 and 2
By taking the NAND of the inverted signal of the frequency-divided output and the frequency-divided output, the data sample pulse (frequency f = 2f ₀ ) as shown in FIG. 2G is output from the output terminal.

Between the data output pulse and the data sample pulse f = 2f ₀ , as shown in FIGS.
As is apparent from the comparison of the waveforms of, the phase difference of 90 degrees exists, and the phase of the data output clock is delayed by 90 degrees from the phase of the data sample pulse.

The data output clock, the data sampling clock, and the frequency-divided output f = 8f ₀ ,
Both the divided-by-4 output f = 4f ₀ and the divided-by-8 output f = 2f ₀ are analog interference waves (frequency f ₀ =
2 v / λ). Then, the data output clock and the data sampling clock are sent to the A / D conversion circuit 2, and the analog interference wave f ₀ is generated in the A / D conversion circuit 2.
= 2v / λ is digitally converted for each constant phase.

That is, the A / D conversion circuit 2 is a NAND
According to the frequency of the data sampling clock output from the gate 6, the analog interference wave is always sampled at a constant phase (π / 4 + nπ, 180 degrees in the example of FIG. 2G). Similarly, the A / D conversion circuit 2 sets the NA
According to the frequency of the data output clock output from the ND gate 5, the analog interference wave previously sampled is always at a constant period (2f ₀ ) as shown in FIG. 2 (i).
A / D conversion is performed for each unit, and the converted digital signal is output to a computer (not shown). In this way, the A / D conversion circuit 2
Digitizes analog interference waves.

The sampling phase interval when N is arbitrary is 2π / (N / 8). This is because the data sampling clock is f = (N / 8) f ₀ . By substituting N = 16 used in the above example for this N, 2π / (N / 8) = 2π / 2 = π = 180 °, and the relationship of FIG. 2 (a) and FIG. 2 (i) is obtained. It becomes a street.

In the present embodiment, the signal digitized by the A / D conversion circuit 2 in FIG. 1 is output to a computer (not shown), but the output digital signal is stored in a RAM (random access memory). Can be stored in. At this time, if the address output of the RAM is made to count the clock output of the PLL circuit 4 and the writing of the data to the RAM is synchronized with the analog interference wave, the digital output signal of the A / D conversion circuit 2 and the RAM. The data acquisition rates can be matched.

In this embodiment, the analog interference wave output from the laser interferometer 1 is described as similar to the A / D converter, but the A / D converter of the present invention is not limited to this. The present invention is not limited to the above, and can be applied to those that perform conversion in synchronization with other various analog signals.

[0030]

As described above, according to the present invention, the reference clock signal having the same frequency as the frequency of the analog signal is generated by the reference clock generating means based on the analog signal converted into the digital signal. The reference clock signal is phase-locked by the PLL means to generate a data sampling clock and a data output clock synchronized with the analog signal, and the analog signal is sampled by the A / D conversion circuit at the cycle of the data sampling clock, Since the sampled analog signal is converted into a digital signal by the A / D conversion circuit in the cycle of the data output clock, even if the frequency of the analog signal fluctuates, it is always synchronized with the cycle of the analog signal. A / D conversion of the analog signal can be performed. Therefore, for example, when applied to a laser interferometer, even if the frequency of the analog interference wave output from the laser interferometer changes, accurate phase data can always be calculated, and a highly accurate laser interferometer can be calculated. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of an A / D converter according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG.

[Explanation of symbols]

 2 A / D conversion circuit 3 Comparator (reference clock generation means) 4 PLL circuit (PLL means) 4a Phase detector 4b N frequency divider 4c DC filter 4f Integration circuit (integrator) 4g Voltage controlled oscillator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03L 7/06

Claims (3)

[Claims] 1. An A / D converter for converting an analog signal into a digital signal, wherein the reference clock generating means generates a reference clock signal having the same frequency as the frequency of the analog signal based on the analog signal. PLL means for generating a data sampling clock and a data output clock based on the reference clock signal; sampling the analog signal based on the data sampling clock; and the sampled analog signal based on the data output clock An A / D converter for converting into a digital signal, and an A / D converter. 2. The PLL means includes a phase detector, a DC filter for extracting a DC component from the output signal of the phase detector, and a DC component of the output signal of the phase detector extracted by the DC filter. An integrator that integrates, a voltage-controlled oscillator that oscillates according to the output voltage of the integrator, and an N frequency divider (M that outputs a plurality of signals having different frequencies, which are obtained by multiplying the output signal of the voltage-controlled oscillator by 1 / M. ≦ N, M, N are integers)
2. The phase detector compares and detects the reference clock signal and a feedback clock signal that is one of the output signals of the N frequency divider and has the same frequency as the reference clock signal. The described A / D converter. 3. The N is 16, and the output signal of the N frequency divider is 1 times the frequency of the reference clock signal and 2 times the frequency of the reference clock signal.
The frequency according to claim 2, wherein the frequency is four times, four times, and eight times.
/ D converter.