JPH066149A - Voltage controlled circuit - Google Patents

Abstract

PURPOSE:To improve the response speed by forming a voltage limit circuit for a collector-emitter voltage of a high current gain transistor(TR) with a base earth circuit whose gain is the unity so as to reduce the parasitic capacitance of the collector. CONSTITUTION:Upon the receipt of an input voltage VIN with a waveform of a fast rising by a voltage limit circuit 50a, the reply of the circuit 50a is controlled by a time constant depending on a resistor 11 and a parasitic capacitance of a collector of a Tr 12 due to the absence of a current Miller circuit. For example, the parasitic capacitance of a PNPTr is nearly 0.8pF, while the parasitic capacitance of an NPNTr is nearly 0.3pF. Since an NPNTr is employed for the Tr 12, the collector parasitic capacitance is smaller than that of the PNPTr and since a base earth circuit is adopted, the deterioration in the response due to the feedback resistance is not caused.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage limiting circuit for limiting a collector-emitter voltage of a high current gain transistor, and more particularly to a voltage limiting circuit having a high response speed.

[0002]

2. Description of the Related Art Although a high current gain transistor has a current gain of about 10 times that of a normal transistor, the collector-emitter breakdown voltage of the normal transistor is "14".
While the collector-emitter withstand voltage of the high current gain transistor is very small, about 6 V, while it is about V ", the voltage limit is set so that the collector-emitter voltage does not exceed the withstand voltage when using the high current gain transistor. It is necessary to add a circuit.

FIG. 5 is a circuit diagram showing an example of a buffer amplifier using a conventional voltage limiting circuit for a high current gain transistor. In FIG. 5, 1 is a high current gain transistor,
Reference numeral 2 is a constant current source, 3, 6 and 7 are normal PNP transistors, 9 is a normal NPN transistor, 4 and 5 are diodes, 8 is a resistor, and 10 is a parasitic capacitance of the transistor 6. Here, the transistors 3, 6, 7 and 9, the diodes 4 and 5, the resistor 8 and the parasitic capacitance 10 are the voltage limiting circuit 50.
Further, the transistor 3 constitutes an emitter follower circuit which detects the output voltage, the transistor 9 constitutes an emitter follower circuit which limits the collector voltage of the high current gain transistor 1, and the transistors 6 and 7 constitute a current mirror circuit. There is.

The base of the high current gain transistor 1 is connected to the input terminal 100, and the input voltage is applied to the input terminal 100.
V _IN ″ is applied. The emitter of the high current gain transistor 1 is connected to one end of the constant current source 2, the base of the transistor 3 and the output terminal 101, and the output voltage “V _OUT ” from the output terminal 101. Is output. The collector of the high current gain transistor 1 is connected to the emitter of the transistor 9, and the other end of the constant current source 2 and the collector of the transistor 3 are connected to the negative voltage source "V _EE ".

The base of the transistor 9 is the transistor 6
Is connected to one end of the parasitic capacitance 10 and the anode of the diode 5. The cathode of the diode 5 is connected to the anode of the diode 4, and the cathode of the diode 4 is connected to the emitter of the transistor 3. on the other hand,
The base of the transistor 6 is connected to the base and collector of the transistor 7 and one end of the resistor 8, and the other end of the parasitic capacitance 10 and the other end of the resistor 8 are grounded. Further, the collector of the transistor 9, the emitter of the transistor 6 and 7 are connected to a positive voltage source "V _CC".

The conventional example shown in FIG. 5 is a high current gain transistor.
The current gain of the transistor 1 is 1 of that of a normal transistor.
Bias current is reduced by utilizing the fact that it is about 0 times.
This is an example of using as a buffer amplifier. This buffer
Amplifier output voltage "V_OUT” High current gain transition
Star 1 emitter voltage "V_E1"Is the base of transistor 3
Voltage between source and emitter "V"_BE3"And diodes 4, 5
Voltage drop "V_Four"," V_Five"Only minutes are added
"V on the base of_B9Is applied as ".
Current gain transistor 1 collector has transistor 9
Base voltage "V _B9"From base Emi of transistor 9
Voltage between terminals "V"_BE9"Subtracted" V _C1Is applied
It As a result, the collector of the high current gain transistor 1
Emitter voltage "V_CE1"Is V_CE1= V_C1-V_E1 = V_BE3+ V_Four+ V_Five-V_BE9 (1) and the output voltage of the buffer amplifier "V"_OUTInvolved in
Not limited to a constant voltage.

[0007]

[Problems to be Solved by the Invention] However, "a" in FIG.
Input voltage “V _IN ” with a fast rising waveform as shown in
Is applied, the emitter voltage “V _E1 ” of the high current gain transistor 1 follows this applied voltage waveform,
The base voltage "V _B9 " of the transistor ₉ is the transistor 6
Due to the influence of the parasitic capacitance 10 of FIG. That is, when the collector current of the transistor 6 is "I" and the capacitance value of the parasitic capacitance 10 is "C", the base voltage "V _B9 " of the transistor 9 is the time constant "I" as shown by "B" in FIG. I couldn't stand up faster than / C ”,
In the shaded portion indicated by “C” in FIG. 6, the collector-base voltage of the high current gain transistor 1 becomes negative,
The high current gain transistor 1 is saturated.

As a result, the speedup of the buffer amplifier shown in FIG. 5 is limited by the response speed of the voltage limiting circuit 50. Therefore, an object of the present invention is to realize a voltage limiting circuit for the collector-emitter voltage that can follow an input voltage of a high current gain transistor that rises quickly.

[0009]

In order to achieve such an object, according to the present invention, the emitter voltage of a high current gain transistor is detected and a voltage obtained by adding a constant voltage to the emitter voltage is used as the high current gain. A first emitter follower circuit for detecting the emitter voltage of the high current gain transistor in a voltage limiting circuit for limiting the collector-emitter voltage of the high current gain transistor by supplying to the collector of the transistor. Grounded base circuit for amplifying the voltage difference between the emitter voltage detected by the emitter follower circuit and the bias voltage with a gain of 1, and a second emitter for supplying the output voltage of the grounded base circuit to the collector of the high current gain transistor. And a follower circuit.

[0010]

By configuring the voltage limiting circuit for the collector-emitter voltage of the high current gain transistor by a base-grounded circuit with a gain of 1 times, the parasitic capacitance of the collector is reduced,
Response speed is improved.

[0011]

The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a configuration circuit diagram showing a buffer amplifier using a first embodiment of a voltage limiting circuit according to the present invention. here,
1, 2, 3, 9, 100 and 101 have the same reference numerals as those in FIG. In FIG. 1, 11 and 14 are resistors, 12 is an NPN transistor, and 13 is a bias voltage source whose bias voltage is "V _BB ". Also, the transistors 3 and 9
And 12, resistors 11 and 14, and bias voltage source 13 form a voltage limiting circuit 50a.

The base of the high current gain transistor 1 is connected to the input terminal 100, and the input voltage is applied to the input terminal 100.
V _IN ″ is applied. The emitter of the high current gain transistor 1 is connected to one end of the constant current source 2, the base of the transistor 3 and the output terminal 101, and the output voltage “V _OUT ” from the output terminal 101. Is output. The collector of the high current gain transistor 1 is connected to the emitter of the transistor 9, and the other end of the constant current source 2 and the collector of the transistor 3 are connected to the negative voltage source "V _EE ".

The base of the transistor 9 is the transistor 1
2 is connected to one end of the resistor 11, and the collector of the transistor 9 and the other end of the resistor 11 are positive voltage source "V _CC ".
Connected to. The emitter of the transistor 12 is the resistor 14
Is connected to the emitter of the transistor 3 via. The base of the transistor 12 is connected to one end of the bias voltage source 13, and the other end of the bias voltage source 13 is grounded.

The operation of the embodiment shown in FIG. 1 is shown in the characteristic curve of FIG.
It will be described with reference to the drawings. First, the input voltage "V_IN"But
Very high "V_IN1” Consider the case. At this time, high
Emitter voltage "V" of current gain transistor 1_E1Is high
Therefore, the bias voltage “V of the bias voltage source 13_BBAgainst
And the transistors 3 and 12 cannot be turned on,
The collector current does not flow to the transistor 12 and the transistor 9
Base voltage "V_B9"Almost a positive voltage source" V_CCIs equal to
It Therefore, the collector current of the high current gain transistor 1 is
Inter-mitter voltage "V"_CE1"Is a high current gain transistor 1
The base-emitter voltage of the_BE1", Transistor
The base-emitter voltage of 9 is "V_BE9If you say, V_CE1= (V_CC-V_BE9) -V_E1 = (V_CC-V_BE9)-(V_IN-V_BE1) It becomes (2). At this time, the voltage limiting circuit 50a is operating.
Since there is no input voltage "V _INHigher current gain as
Collector-emitter voltage of transistor 1
V_CE1“Increases like“ a ”in FIG.

Secondly, the transistors 3 and 12 are turned "ON" with respect to the bias voltage "V _BB " of the bias voltage source 13.
Input voltage “V _IN2 ” to start Consider the case where is applied. At this time, the collector current of the transistor 3 starts to flow because the transistors 3 and 12 start to turn “ON”. Further, when the input voltage “V _IN ” decreases, the transistors 3 and 12 are completely turned “ON” and a current flows through the resistor 14, so that a voltage drop occurs in the resistor 14. When the base-emitter voltages of the high current gain transistor 1, the transistors 3 and 12 are set to “V _BE1 ”, “V _BE3 ”, and “V _BE12 ”, respectively, the voltage drop across the resistor 14 is “
V ₁₄ ″ becomes V ₁₄ = (V _BB −V _BE12 ) − (V _IN −V _BE1 + V _BE3 ) (3).

Here, if the resistance values of the resistors 11 and 14 are made equal, the collector current and the emitter current of the transistor 12 are substantially equal, so that the voltage drop of the resistor 11 "
V ₁₁ ″ becomes almost equal to the voltage drop “V ₁₄ ” of the resistor 14. Therefore, when the input voltage “V _IN ” becomes lower than the voltage value such that the relation of the equation (3) is satisfied, the collector of the high current gain transistor 1 becomes. _-The voltage between emitters "V _CE1 " is V _CE1 = (V _CC -V ₁₁ -V _BE9 ) -V _E1 = (V _CC -V ₁₄ -V _BE9 )-(V _IN -V _BE1 ) = V _CC -V _{BB + V BE12 + V iN -V} BE1 + V BE3 -V BE9 -V iN + V BE1 = V CC -V BB + V BE12 + V BE3 -V BE9 (4) , and the input voltage "V _iN" is in FIG. 2 "V _IN2" ~ "V
_Regardless of the input voltage, it is limited to a constant voltage as shown by "b" in Fig. 2 between _IN3 ". As a result, the equation (4) becomes less than the collector-emitter breakdown voltage of the high current gain transistor 1. The bias voltage of the bias voltage source 13 "V
Adjust _BB ”.

That is, the transistor 12, the resistors 11 and 14, and the bias voltage source 13 are grounded base for amplifying the difference between the emitter voltage "V _E1 " of the high current gain transistor 1 and the bias voltage "V _BB " by a gain of one. It will operate as a circuit.

In addition, an input voltage having a waveform with a fast rising edge
When V _IN ″ is applied, since there is no current mirror circuit as shown in FIG. 5, what limits the response of the voltage limiting circuit 50 a is the time constant determined by the parasitic capacitance of the resistor 11 and the collector of the transistor 12. Here, for example, the parasitic capacitance of the PNP transistor is about "0.8 pF", whereas the parasitic capacitance of the NPN transistor is "0.8 pF".
Since the transistor 12 is an NPN transistor, the parasitic capacitance of the collector is smaller than that of the PNP transistor, and the base-grounded circuit configuration does not deteriorate the response due to the feedback capacitance.

The first embodiment shown in FIG. 1 is an example in which a high current gain transistor is used as a buffer amplifier in which the bias current is reduced, but it is used in a first stage differential amplifier of an operational amplifier or a comparison circuit. Is also effective. However, when it is used for the first-stage differential amplifier of the operational amplifier, the purpose is to reduce the bias current similarly to the buffer amplifier, whereas when it is used for the first-stage differential amplifier of the comparison circuit, the reason is different. That is, the difference between the two input voltages is generally large in the first-stage differential amplifier of the comparison circuit, and the base-emitter voltage of one input transistor is reverse biased. This reverse bias breakdown voltage is a normal NPN
Transistor "3V", PNP transistor "5"
It is about V ″.

Therefore, conventionally, a differential amplifier as shown in FIG. 3 is constructed to increase the reverse bias withstand voltage. In FIG. 3, 15 and 16 are resistors, 17 to 20 are transistors, and 21 is a constant current source. Here transistor 1
By adding 9 and 20 and receiving the reverse bias by dividing the two transistors, the breakdown voltage of the reverse bias of the base-emitter voltage is improved. However, this causes deterioration of the input voltage range and the input offset voltage.

On the other hand, the base of the high current gain transistor
The reverse bias withstand voltage of the emitter-to-emitter voltage is about "15V", which is higher than that of a normal transistor. Therefore, the first-stage differential amplifier using a high current gain transistor is effective.
FIG. 4 is a configuration circuit diagram showing a first stage differential amplifier using a second embodiment of the voltage limiting circuit according to the present invention. here,
3, 9, 11, 12, 13, and 14 have the same reference numerals as those in FIG. In FIG. 4, 9a denotes an NPN transistor whose base is connected to the base of the NPN transistor 9,
Reference numerals 5 and 16 are resistors, 21 is a constant current source, and 22 and 23 are high current gain transistors. Also, the transistors 3, 9,
The bias voltage sources 13 and 9a and 12 and the resistors 11 and 14 form a voltage limiting circuit 50b.

In the second embodiment shown in FIG. 4, the resistor 15,
16, constant current source 21, high current gain transistors 22, 2
A voltage limiting circuit 50b composed of two emitter follower circuits composed of two transistors 9a and 9 for respectively restricting the collector voltage of the high current gain transistors 22 and 23 is added to the differential amplifier composed of three. It is characterized by Further, other configurations and operations in the voltage limiting circuit 50b are similar to those in the first embodiment.

By adopting the configuration as in the second embodiment, it is possible to improve the withstand voltage of the reverse bias of the base-emitter voltage without adding a transistor, and a high speed comparison circuit with a wide input voltage range can be obtained. Can be realized.

[0024]

As is apparent from the above description,
The present invention has the following effects. By configuring the voltage limiting circuit for the collector-emitter voltage of the high current gain transistor with a base-grounded circuit with a gain of 1 times, the collector-emitter voltage of the high current gain transistor that can follow the rising rising input voltage A voltage limiting circuit can be realized.

[Brief description of drawings]

FIG. 1 is a configuration circuit diagram showing a buffer amplifier using a first embodiment of a voltage limiting circuit according to the present invention.

FIG. 2 is a characteristic curve diagram showing a relationship between an input voltage and a collector-emitter voltage of a high current gain transistor in the first embodiment.

FIG. 3 is a circuit diagram showing an example of a conventional first stage differential amplifier.

FIG. 4 is a configuration circuit diagram showing a first-stage differential amplifier using a second embodiment of the voltage limiting circuit according to the present invention.

FIG. 5 is a circuit diagram showing an example of a buffer amplifier using a conventional voltage limiting circuit.

FIG. 6 is a timing chart showing a response waveform to an input voltage waveform of a conventional example.

[Explanation of symbols]

1,22,23 High current gain transistor 2,21 Constant current source 3,6,7,9,9a, 12,17,18,19,20
Transistors 4,5 Diodes 8, 11, 14, 15, 16 Resistances 10 Parasitic capacitances 13 Bias voltage sources 50, 50a, 50b Voltage limiting circuits 100 Input terminals 101 Output terminals

Claims (1)

[Claims] 1. A collector-emitter of the high current gain transistor by detecting an emitter voltage of the high current gain transistor and supplying a voltage obtained by adding a constant voltage to the emitter voltage to the collector of the high current gain transistor. In a voltage limiting circuit for limiting the inter-voltage, a first emitter follower circuit for detecting the emitter voltage of the high current gain transistor, and a voltage difference between the emitter voltage and the bias voltage detected by the first emitter follower circuit are gained. A voltage control circuit comprising: a base-grounded circuit that amplifies by a factor of 1; and a second emitter follower circuit that supplies the output voltage of the base-grounded circuit to the collector of the high-current gain transistor.