JPH0661239A - Semiconductor device and its production - Google Patents

Abstract

PURPOSE:To provide a method which simultaneously allows high cutoff frequency, low base resistance and low emitter resistance for a new bipolar transistor structure. CONSTITUTION:On a one type semiconductivity-type epitaxial semiconductor layer 13 formed on a semiconductor 1, an opposite conductivity-type first semiconductor layer 6 and the one conductivity type second semiconductor layer 7 are successively laminated in a mesa-shape, and a pn-junction is allowed between the first semiconductor layer 6 and the epitaxial semiconductor layer 13 and between the first semiconductor layer 6 and the second semiconductor layer 7. A side wall composed of an insulating film 9 is formed on the side walls of the first semiconductor layer 6 and the second semiconductor layer 7, an opposite conductivity type contact diffused layer 10, which partially connects with the first semiconductor layer 6, is formed in the epitaxial semiconductor layer 13, and a semiconductor device is provided with a first electrode 12 which connects with the semiconductor layer 13, a second electrode 16 which connects with the contact diffused layer 10 and a third electrode 17 which connects with the second semiconductor layer 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a novel structure of a bipolar transistor and its forming method.

Recent bipolar LSIs are required to have high speed. Therefore, it is necessary to achieve high cutoff frequency (f _T ), low base resistance, and small collector-base capacitance.

[0003]

2. Description of the Related Art FIG. 4 is an explanatory view of a conventional example. In the figure, 1 is a semiconductor substrate of opposite conductivity type, 2 is a buried layer of one conductivity type collector, 3 is a contact layer of one conductivity type collector, 4 is an isolation layer of opposite conductivity type, 5 is a field insulating film, and 6 is a first semiconductor. Layer, an epitaxial base layer also serving as a base extraction electrode, 7 a second semiconductor layer, an emitter layer made of poly-Si, 12 a first electrode and a contact electrode, 14 an interlayer insulating film, Reference numeral 16 is a second electrode which is a base electrode, and 17 is a third electrode which is an emitter electrode.

In a conventional bipolar LSI, in order to obtain a high cutoff frequency, a shallow base diffusion layer is formed by performing ion implantation with low acceleration energy. In this case, as shown in FIG. Since the ion implantation channeling and the impurity distribution follow a Gaussian distribution, there is an influence of dispersion, and the limit is about 1,500 Å.

As a countermeasure against this, in recent years, the base layer has been CVD-deposited.
Method, or a method of forming an epitaxial base layer by epitaxial growth using the MBE method has been developed.

However, in this method, as shown in FIG. 4 (b), the base lead layer is formed in the same layer as the internal (intrinsic) base layer 6, so that the base resistance is high.
Further, even if the polysilicon layer in which the impurities are diffused is used as the external base to reduce the resistance, it is not formed in self-alignment with the internal base, and therefore the base resistance becomes high.

Further, there is a problem that the emitter resistance increases due to the growth of a natural oxide film during the formation of the emitter.

[0008]

Therefore, although the cut-off frequency may be high, the base resistance cannot be reduced and the speed cannot be increased.

It is an object of the present invention to provide a method of making a high cutoff frequency compatible with a low base resistance and a low emitter resistance.

[0010]

FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, 1 is a semiconductor substrate of opposite conductivity type, 2
Is a buried layer of one conductivity type collector, 3 is a collector contact layer of one conductivity type, 4 is an isolation layer of opposite conductivity type, 5
Is a field insulating film, 6 is a first semiconductor layer, and is an epitaxial base layer that also serves as a base extraction electrode, 7
Is a second semiconductor layer, is an emitter layer made of poly-Si, 10 is a contact diffusion layer, a base contact layer, 12 is a first electrode, 13 is a one-conductivity type epitaxial collector layer, and 14 is interlayer insulation. A film, 15 is a refractory metal layer, 16 is a second electrode, and 17 is a third electrode.

The above problem is solved by the one-conductivity-type epitaxial semiconductor layer 13 formed on the substrate 1 as shown in FIG.
A first semiconductor layer 6 of opposite conductivity type and a second semiconductor layer 7 of one conductivity type are sequentially stacked on each other in a mesa type, and between the first semiconductor layer 6 and the epitaxial semiconductor layer 13, and , P between the first semiconductor layer 6 and the second semiconductor layer 7, respectively.
A sidewall made of an insulating film 9 is formed on the sidewalls of the first semiconductor layer 6 and the second semiconductor layer 7 to form an n-junction, and the sidewalls of the first semiconductor layer 6 and the first semiconductor layer 6 are partially formed in the epitaxial semiconductor layer 13. A contact diffusion layer 10 of opposite conductivity type to be connected is formed, and a first electrode 12 connected to the semiconductor layer 13 is formed,
By having the second electrode 16 connected to the contact diffusion layer 10 and the third electrode 17 connected to the second semiconductor layer 7, the one conductivity type epitaxial semiconductor layer 13 formed on the substrate 1 is also formed. To define the field insulating film 5,
A step of sequentially laminating a first semiconductor layer 6 of opposite conductivity type and a second semiconductor layer 7 of one conductivity type on the substrate 1 including the demarcated region, the second semiconductor layer 7, and A step of selectively etching the first semiconductor layer 6 in a mesa type to remove it except a predetermined region of the demarcated region; and introducing an impurity into the epitaxial semiconductor layer 13 to selectively remove the first semiconductor layer 6. The step of forming the contact diffusion layer 10 partially connected to the semiconductor layer 6, and the sidewall insulating film 9 on the side wall of the mesa-type second semiconductor layer 7 and the first semiconductor layer 6. It is solved by including the process of performing.

Further, in order to further reduce the emitter resistance and the base resistance, the refractory metal layer 15 is formed on the emitter layer 7.
An example in which the high-concentration base contact layer 11 is added to the base contact layer 10 is shown in FIG.

[0013]

According to the structure of the present invention, the internal base layer can be formed thin by epitaxial growth.
Moreover, since the emitter layer can be formed without etching the internal base layer, the emitter layer can be formed without damaging the thickness of the internal base layer, and the stability of the characteristics is enhanced. Also, the base resistance can be reduced because the internal base layer and the external base contact layer can be formed by self-alignment.

[0014]

FIG. 2 is a schematic sectional view in order of steps of a first embodiment of the present invention, and FIG. 3 is a schematic sectional view in order of steps of a second embodiment of the present invention.

In the figure, the same reference numerals as those in FIG. 1 are used for the substantially same parts between the principle explanatory view and the embodiment. Specifically, 1
Is a p-type silicon (Si) substrate, 2 is an n ⁺ type collector buried layer, 3 is an n type collector contact layer, 4 is a p ⁺ type isolation layer, and 5 is field two-participating silicon (SiO ₂ ).
Film, 6 is base layer, 7 is emitter layer, 8 is SiO ₂ film, 9 is sidewall SiO ₂ film, 10 is base contact layer, 11 is high concentration base contact layer, 12 is collector electrode, 13 is n
Type epitaxial collector layer, 14 is an interlayer SiO ₂ film, 15 is a tungsten (W) film, 16 is a base electrode, and 17 is an emitter electrode.

A first embodiment of the present invention will be described with reference to the schematic cross-sectional views in order of steps of FIG. As shown in FIG. 2A, the n ⁺ type collector buried layer 2, the n type collector contact layer 3, the p ⁺ type isolation layer 4, the field SiO ₂ film 5 are formed on the p type Si substrate 1 by the conventional method. After the formation of the layer, an interlayer SiO ₂ film 14 is formed on the entire surface of the Si substrate 1 by the CVD method.
The layer is grown to a thickness of 1,000Å, the interlayer SiO ₂ film 14 is selectively etched, and a window is opened in the base formation region.

As shown in FIG. 2 (b), p-type, for example, boron (B) is formed on the entire surface of the Si substrate 1 by the CVD method or the MBE method, for example, 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ^-3. The Si epitaxial base layer 6 having a thickness of 500 to 2,000 Å is grown with the impurity concentration of.

Subsequently, the emitter layer 7 made of a poly-Si film is laminated to a thickness of about 3,000Å by the CVD method. After that, a SiO ₂ film 8 is formed on the entire surface of the Si substrate 1 by the CVD method.
3,000Å grow.

As shown in FIG. 2 (c), for example, arsenic (As) is applied to the emitter region by an ion implantation method, and an acceleration voltage of about 40 is applied.
Inject under the conditions of KeV and dose of 1x10 ^{15 to} 1x10 ¹⁷ / cm ² .
After that, leaving the emitter and base formation regions, the other regions are removed by anisotropic etching to form mesa-type emitter-base stacked regions 7 and 6.

Next, for example, boron or boron fluoride is ion-implanted into the n-type epitaxial collector layer 13 at an accelerating voltage of about 10 to 40 KeV and a dose of 1x10 ^{13 to} 1x10 ¹⁵ /
The base contact layer 10 is formed by selectively implanting under the condition of cm ² to join the epitaxial base layer 6.

After that, the SiO ₂ film 9 is grown on the entire surface of the Si substrate 1 by the CVD method by about 3,000 Å, and then anisotropic etching is performed so that the SiO ₂ film 9 is left only on the side surface of the emitter / base region. Then, the side wall SiO ₂ film 9 is formed.

As shown in FIG. 2 (d), activation annealing is performed in a nitrogen (N ₂ ) atmosphere at 1,100 ° C. for about 10 seconds to activate the emitter layer 7 and the base contact diffusion layer 11. Also, the time is controlled so that h _FE becomes a desired value. Next, each contact window is selectively opened using a mask, and an aluminum (Al) collector electrode 12, a base electrode 16, and an emitter electrode 17 are formed by a conventional method.

The second embodiment of the present invention will be described with reference to the schematic cross-sectional views in order of steps of FIG. Basically, it is the same as the first embodiment of FIG. 2, and a method different from the first embodiment is additionally implemented in each process.

As shown in FIG. 3A, the n-type collector burying layer 2 and the n-type collector buried layer 2 are formed on the p-type Si substrate 1 by the conventional method.
Type collector contact layer 3, p-type isolation layer 4 and field SiO ₂ film 5 are formed, and then an oxide film 14 is grown to a thickness of about 1,000Å on the entire surface by a CVD method, and a mask is used to form a base formation region. The window is opened and the SiO ₂ film 14 is removed by etching.

As shown in FIG. 3B, a thickness of 500 to 500 is formed on the entire surface of the Si substrate 1 by the CVD method or the MBE method.
2,000Å, p-type impurity concentration 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ^-3 Si
Of the epitaxial base layer 6 is grown.

In this embodiment, epi-poly growth is used. The grown epitaxial base layer is, for example, Si
A mixed crystal such as Ge may be used. The epitaxial base region is left in the mesa shape, and the other regions are removed by anisotropic etching.

Next, a poly-Si emitter layer 7 having a thickness of 1,000 to 3,000Å is grown on the entire surface to a thickness of about 3,000Å. Further, in order to reduce the wiring resistance of the emitter, a refractory metal such as tungsten (W) having a thickness of 500 to 3,000Å is formed on the entire surface.
15 is grown by the sputtering method or the CVD method. Next, an interlayer SiO ₂ film 8 is formed on the entire surface by the CVD method.
Grow to a thickness of 3,000Å.

As shown in FIG. 3 (c), for example, arsenic is implanted into the emitter region as an emitter diffusion by an ion implantation method under the conditions of an acceleration voltage of about 40 KeV and a dose amount of 1 × 10 ^{15 to} 1 × 10 ¹⁷ / cm ² . Subsequently, the emitter region and the collector region are left, and the other regions are removed by anisotropic etching.

Next, as the contact diffusion layer 10 in the base region, for example, boron or boron fluoride is accelerated by an ion implantation method at an accelerating voltage of about 10 to 40 KeV and a dose of 1 × 10 ^{13 to} 1 × 10 5.
Inject under the condition of ¹⁵ / cm ² .

After that, SiO ₂ is deposited on the entire surface of the substrate by the CVD method.
After the film 9 is grown to about 3,000 Å, anisotropic etching is performed to leave the sidewall SiO ₂ film 9 in the base / emitter mesa region and the collector poly-Si electrode part.

Furthermore, the base contact layer 11 in the base region
On the side wall SiO ₂ film 9 and the emitter layer 6
By using the SiO ₂ film 8 as a mask and self-aligned ion implantation, for example, boron or boron fluoride is used to accelerate the voltage.
Additional injection is performed under the conditions of 10 to 40 KeV and a dose of 1x10 ^{13 to} 1x10 ¹⁶ / cm ² .

As shown in FIG. 3D, activation annealing is performed in a nitrogen atmosphere at 1,100 ° C. for about 10 seconds to activate the emitter layer 7 and the base contact diffusion layer 11.
Also, the time is controlled so that h _FE becomes a desired value. Next, open each contact window using a mask,
The Al collector electrode 12, the base electrode 16, and the collector electrode 17 of Al are formed by a conventional method.

[0033]

As is apparent from the above embodiments of the present invention, according to the structure of the bipolar transistor and the manufacturing method thereof according to the present invention, an extremely thin intrinsic base layer formed by epitaxial growth is formed as an emitter layer. Since it can be formed without etching at times, it largely contributes to the stabilization of the characteristics and the improvement of the reliability without damaging the thickness of the internal intrinsic base.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

2A to 2C are schematic cross-sectional views in order of the processes of the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view in order of the steps of a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1 Opposite conductivity type semiconductor substrate, p-type Si substrate 2 One conductivity type collector buried layer, n ⁺ type collector buried layer 3 One conductivity type collector contact layer, n ⁺ type collector contact layer 4 Opposite Conductive isolation layer, p ⁺ type isolation layer 5, field insulating film, field SiO ₂ film 6, first semiconductor layer, base layer 7, second semiconductor layer, emitter Layer 8 Insulating film layer, SiO ₂ film 9 Sidewall insulating film, sidewall Si
O ₂ film 10 Base contact layer 11 High-concentration base contact layer 12 Electrode wiring layer, collector electrode 13 One conductivity type epitaxial collector layer 14 Interlayer insulating film, Interlayer SiO ₂ film 15 Refractory metal layer , W film 16 electrode wiring layer, base electrode 17 electrode wiring layer, emitter electrode

Claims (2)

[Claims] 1. A first-conductivity-type epitaxial semiconductor layer (13) formed on a substrate (1), a first-conductivity-type first semiconductor layer (6), and a first-conductivity-type second semiconductor layer (6). 7) are sequentially laminated in a mesa type, and between the first semiconductor layer (6) and the epitaxial semiconductor layer (13), and between the first semiconductor layer (6) and the second semiconductor layer. A pn junction between the first semiconductor layer (6) and the second semiconductor layer (7).
(7) A side wall made of an insulating film (9) is formed on the side wall, and a contact diffusion layer of opposite conductivity type (partial connection with the first semiconductor layer (6) is formed in the epitaxial semiconductor layer (13). A first electrode (12) on which the semiconductor diffusion layer (10) is formed and which is connected to the semiconductor layer (13), a second electrode (16) connected to the contact diffusion layer (10), and a second semiconductor (16) A semiconductor device having a third electrode (17) connected to the layer (7). 2. A step of defining a one conductivity type epitaxial semiconductor layer (13) formed on a substrate (1) with a field insulating film (5), and an opposite conductivity on the substrate (1) including the defined region. A first semiconductor layer (6) of a conductive type and a second semiconductor layer (7) of a single conductivity type in this order, the second semiconductor layer (7), and the first semiconductor layer A step of selectively etching (6) in a mesa type except the predetermined area of the demarcated area and selectively introducing impurities into the one conductivity type epitaxial semiconductor layer (13); A step of forming a contact diffusion layer (10) partially connected to the first semiconductor layer (6), the mesa-type second semiconductor layer (7), and the first semiconductor layer (6) And a step of forming a sidewall insulating film (9) on the sidewall of the semiconductor device.