JPH0661039B2 - Memory access control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control circuit, and more particularly, to a memory access suitable for performing drawing including raster operation between a frame memory and a main memory of a display device. Regarding the control circuit.

[Conventional technology]

2. Description of the Related Art In recent years, due to the development of manufacturing technology of IC memories and microprocessors (hereinafter referred to as CPU), low-cost, high-performance bit map type display devices have become widespread. Along with this, development of software that makes full use of the rich expressive ability peculiar to Bitmap screens is being actively conducted, and the accumulation of such software assets is advancing year by year.

A particular operation among such operations on the bit map screen is a calculation operation called raster operation (hereinafter referred to as raster OP). This is a logical operation of image data on the screen and another image data, and the result of the operation is new image data. By this operation, effects such as image composition, superposition, duplication, and color change are obtained. be able to. In the early bit map display devices, all of these calculations were performed by the software processing of the CPU. However, as the number of pixels on the bit map screen increases, the number of gradations of pixels and the number of colors increase, the amount of calculation required for the raster OP continues to increase, which causes a problem in processing time.

In order to solve this processing time problem, a technique for speeding up the process has been known. For example, this technique is disclosed in Japanese Patent Laid-Open No. 209784/1983. FIG. 2 is a diagram showing the above conventional technique. In the figure, 1 is a microprocessor (hereinafter referred to as CPU) for controlling drawing of a bit map display device, 7 is a main memory (main storage: hereinafter referred to as MS), and 6 is a frame buffer (hereinafter referred to as image data). FB), 8 is an indicator (hereinafter Di
12) CPU 1 address bus, 11 CPU
1 is a data bus, 17 is an FB6 data bus, 22 is a data bus switching switch, 4 is a register for temporarily storing data (source data register: hereinafter referred to as SREG), and 5 is a logical operation unit (hereinafter referred to as ALU). .

For simplification, the drawing shows the case where the FB 6 is one plane, but when the FB 6 is in color display or multi-gradation display, it is 9
It is sufficient to provide some of these parts with the part surrounded by the one-dot chain line as a unit.

According to the above-mentioned technique, it is possible to write the result of raster calculation of the data previously written in SREG4 and the data on the data bus 18 by ALL5 to FB6. Generally FB
When 6 is read, A and C of bus switch 22 are connected, and F
Read data from B6 via data buses 17 and 18
Control to write to SREG4. When the write operation is performed on FB6, B and C of the bus switch 22 are connected,
The write data of the CPU 1 is given to the ALU 5 via the data buses 11 and 18, and the data of the SREG 4 is also given to the data bus 19.
Since it is given to the ALU 5 via the, the calculation result of these two data is written to the FB 6 via the data bus 17. There are two possible write data for the CPU 1. 1
One is the data stored in the MS 7, and the other is the data in the FB 6. In either case, the data is already stored in the CPU
Read 1. (FB6 data is a bus switch
It can be read by connecting A and B of 22. [Problems to be Solved by the Invention] In the above-described conventional technique, raster OP for FB6 can be performed, but raster OP for MS7 cannot be performed. In recent years, in software that handles a bit map screen, most of the MS 7 is regarded as a virtual FB and drawn on the MS 7. Therefore, like FB6,
The same drawing performance is required for the MS7 as well.

That is, since the prior art described above does not consider the raster OP for the MS 7, the program for drawing in the FB 6 can perform high-speed drawing by utilizing the hardware, but the drawing for the MS 7 is all raster OP by the software processing of the CPU. There was a problem that I had to draw after I did. In FIG. 2, a circuit for performing binary raster OP has been described for the sake of simplicity. However, in the case of performing ternary raster OP (that is, another set of data buses is input to ALU5) for MS7. However, the load on the software is more than five times as large as when drawing on the FB6. That is, the first problem is that the FB6 and the MS7 cannot be equally drawn.

Next, in the raster OP using the conventional technique, the CP is basically
U1 can perform predetermined drawing only by transferring data. In other words, the calculation is performed by the ALU5,
U1 simply moves the data. On the other hand, in recent years, many CPUs have an instruction (which is called a string instruction) for continuously transferring a plurality of data. This is to transfer data from the source area to the destination area. A large amount of data can be transferred with one instruction, and a high-speed transfer process can be performed because the data bus is not used for other than data transfer while the instruction is being executed. There is.

By the way, in order to perform the raster OP, two pieces of data (three pieces in the case of the ternary raster OP) are required as input data. Therefore, in order to perform the raster OP with one data transfer instruction, at least two parameters indicating the source address and one parameter indicating the one destination address can be specified. There must be. However, the existing CPU string instructions can only indicate two parameters, one for the source and one for the destination.

As described above, in the conventional technique, since the high-speed raster OP is not performed by using the string instruction of the CPU, the raster OP is performed by combining the individual data transfer instructions for many steps. Therefore, raster O
The problem that the highest performance (maximizing the bus utilization rate) cannot be achieved due to the software overhead for executing many steps of data transfer instructions even though the P part is configured by hardware. I got it.
This is the second problem.

An object of the present invention is to provide a memory access control circuit which can perform raster OP processing without distinction between FB and MS and can perform binary or ternary raster OP with a string instruction of a CPU.

[Means for solving problems]

The above-mentioned purpose is to use the output data bus of the first ALU as a conventional F
An address generator (hereinafter referred to as AG) that provides a path to connect to the MS in addition to the path to connect to B and secondly generates an address indicating another source area different from the source area specified by the string instruction of the CPU. This is achieved by providing an access controller (hereinafter referred to as AG) that controls access to the MS by switching addresses generated by the CPU and AG.

[Action]

First, by providing a path in which the output data bus of the ALU is connected to the data bus of the MS, it becomes possible to write the operation result to the MS (draw on the MS). Also AG
The address generated by the
It is possible to indicate the second (second and third) source regions that are lacking in use in the above (if another AG is provided).

In addition, the string instruction is a pair of read and write, and this pair is repeatedly executed to transfer data. However, the timing of this write is caught, the CPU is stopped immediately after the end of the write operation, and the address indicated by the above-mentioned AG. After reading the data from and storing this data, C
If the control is returned to the PU, the operation seen from the CPU is simply the source,
Despite data transfer between days, binary and ternary raster OP drawing can be performed.

〔Example〕

A first embodiment of the present invention will be described below with reference to FIGS. 1 and 3 to 6.

FIG. 1 is a block diagram of the first embodiment of the present invention. In the figure, 1 is a CPU, 2 is an address generator (A
G), 3 is an address controller (AC), 7 is a main storage (MS), 6 is a frame buffer (FB),
8 is a display unit (DiSP), 4 is a register (SREG) for temporarily storing source data, 5 is a logical operation unit (ALU) for performing a raster OP, 21 is the address bus 13 and A of the CPU 1.
An address bus switch for switching the G address bus 14 to connect it to the MS7 and FB6 address buses, and 22 for the CPU 1
The data bus switch for switching the data bus 11 of 11 and the data bus 17 of the FB 6 to connect to the internal data bus 18, and 23 for AL
A data bus switch for switching the data output 20 of U5 to the data bus 17 of FB6 and the data bus 11 'of MS7, and 24 is C
A data bus switch for connecting or disconnecting the data bus 11 of PU1 and the data bus 11 'of MS7.

In the figure, the ALU 5 includes a register for storing a calculation mode that specifies what kind of calculation (logical sum, logical product, negation and combination thereof) as the ALU. In addition, the bus switches 21 to 24 are read out by the CPU 1 to the AC3,
It includes an operation mode register that specifies how to switch in response to a write operation.

Next, the operation will be described. FIG. 3 shows C using the circuit of the present invention.
It is an execution flow of raster OP processing by a continuous data transfer instruction (string instruction) of PU1. Binary raster OP
The process calculates two source data and stores the result in the destination. In the present embodiment, the raster OP process can be executed by the string instruction of the CPU even if the two source data and the data of the destination are in either MS7 or FB6.

First, the case where two sources and one destination are all in the FB6 will be described.

FIG. 4 is a diagram showing the data flow in this case in accordance with the flow of FIG. FIG. 3 will be described with reference to FIG. The 1-line raster OP process in FIG. 3 indicates that the raster OP is performed on a plurality of data. Processing 100
Then, what kind of raster OP is performed is set. That is, the calculation type of the raster OP is set in the calculation mode register (not shown) in the ALU 5, and in this example, two sources (S0 300, S1 301) and a destination (D302) exist in the FB6. This is set in the operation mode register (not shown) in AC3.

In process 101, AG2 is initialized. In this example, AG2
Is the address of S0 300, and C
It is assumed that the read address of PU1 shows the address of S1 301 and the write address of CPU1 shows the address of D302. FIG. 5 shows a specific configuration example of the main part of AG2. The diagram (a) is suitable when the addresses generated by the AG2 are required to be consecutive. When the number of addresses required is n + 1, an n + 1-bit presettable counter (or up-down counter) 500 is required. And then A
This is a configuration of G2. FIG. 7B shows a configuration suitable for the case where a value that is discretely increased (decreased) for each offset value is required as an address generated by AG2, and the address register 502 that holds the latest address value and the increase / decrease It consists of an offset register 501 for holding a flaw and an adder 503. In the processing 101, in the case of FIG. 5 (a), the counter 500 is pre-set with the start address of the area S0 300, and in the case of FIG. 5 (b), the area S0 30 is stored in the address register 502.
The leading address of 0 is set, and the value of the scratch width is set in the offset register 501.

When the processing 101 is completed, the AC3 detects that the CPU1 has completed setting the AG2 (it can be detected by miniaturizing the writing to the AG2), and requests the CPU1 to release the bus. When the CPU1 responds to this request, AC
3 switches the address bus switch 21 to connect A and C (B and C are connected in the initial state). At the same time, AC3 connects A and C of the data bus switch. After that, as a process 200 ', the AC3 reads the data in the area S0 300 using the address output from the AG2 and stores the data in the SREG4.

In process 201 ', AC3 sends a pulse to the signal line 15, and A3
The value of the counter 500 of G2 or the address register 502 is updated. After this processing is finished, the AC3 connects B and C of the address bus switch 21 and returns the control right of the bus to the CPU1.

In process 102, the CPU 1 registers in the CPU 1 for executing a string instruction (a continuous transfer instruction of a plurality of data), for example, a register for holding the address value of the S1 301 area, the address value of the D302 area and the number of data to be transferred (not shown). No.) is initialized.

The next processings 103 to 105 are processing contents of a single string instruction. In process 103, the CPU 1 reads the data in the FB 6 into the CPU 1. At this time, AC3 connects A and B of the bus switch 22 to create a data path. In process 104, the CPU 1 performs F
Attempt to write to B6. At this time, AC3 connects B and C of the bus switch 22 to form a path for supplying the write data from the CPU1 to the input on one side of the ALU5. ALU
Since the contents of SREG4 are previously given to the other inputs of A5, the output of ALU5 results in area S0 300.
And ALU5 set in the process 100 with the data of area S1 301
The operation is performed according to the logical operation mode of. A
At this time, C3 connects A and C of the bus switch 23 to FB.
A write data path for 6 is also created. With the processing up to this point, the first raster OP processing has been completed. FB
When the writing to 6 is detected, the AC 3 shifts to writing the data in the next S0 300 for the next raster OP.

In process 200, the AC3 issues a bus release request to the CPU1 and obtains control of the bus. Next, connect A and C of the address bus switch 21 and A of the data bus switch 22.
And C are connected to read the contents of the area S0 300 of the FB6 and store them in SREG4. In process 201, as in process 201 ′, the address of AG2 is set to the area S0 30 using the signal line 15.
The address is updated to the next position of 0, and B and C of the address bus switch 21 are connected to transfer the bus control right from AC3 to the CPU.
Return to 1. The processes 200 and 200 'and the processes 201 and 201' have the same process contents except that the starting conditions of the processes are different. That is, the processes 200 'and 201' are started when the CPU 1 completes the initialization of the AG2, and the processes 200 and 201 are C
It is activated when PU1 has written data.
In the 1-line raster OP process, the process 200 '
And 201 'are used for reading the data in the area S0 300 for the first time only, and all the processing 200, 201 for the second time and thereafter.
It is read by.

Process 105 is an internal process of the CPU 1. Here, process 102
In the CPU 1, it is judged whether the data has been transferred the number of times of repeating the data transfer set in step 2. If the data has been transferred a predetermined number of times, the process is ended, and if not, the process 10
Return to 3.

What should be noted here is the process in which the raster OP is actually performed.
In the steps 103 to 105, the CPU 1 never executes the instruction fetch. In other words, the bus is 100% available for data transfer, so it can be processed at the fastest speed allowed by the bus.

Next, regarding the processing in the case where all the three storage areas of the two sources and the day station exist in the MS 7,
This will be described with reference to FIG. 3 with reference to FIG. What differs from the last time in the process 100 is that the three areas in the MS7 are set in the operation mode register in the AC3.

What is done in process 101 is the area S0 in AG2 as in the previous time.
This is the initial setting of the address indicating 300. In process 200 ', the initial setting of AG2 is used as a starting condition, and AC3 first obtains the bus use right. Next, AC3 connects A and C of the address bus switch 21, and B and C of the data bus switch 22,
The area S0 30 in the MS 7 is set by connecting A and B of the data bus switch 24 (which is normally connected).
The data of 0 is stored in SREG4. After that, the address of AG2 is updated in processing 201 ', and B of the address bus switch is updated.
And C are connected and AC3 returns control to CPU1. Processing 10
In 2, the string commands are initialized as in the previous time.

In process 103, since A and B of the data bus switch 24 are in the connected state, the CPU 1 sends the data of the area S1 301 to the CP.
Read inside U1. In the process 104, the AC3 detects the write cycle of the CPU1 and detects the A of the data bus switch 24.
Cut B and B, B and C of bus switch 22 and Bass switch 23
B and C are connected. As a result, the write data of the CPU 1 and the data in the SREG 4 are logically operated by the ALU 5, and the result is written in the area D 302 in the MS 7. When the writing is completed, the AC 3 connects A and C of the bus switch 23 and connects A and B of the bus switch 24. This completes the first raster OP.

Processing 200 and processing 201 with writing to MS7 as the start condition
Will start. These read data from the area S0 300 in the MS 7 through the same procedure as the processing 200 'and 201' and store it in SREG4. In process 105, the number of processes is determined and processes 103 to 105 are repeated a predetermined number of times. As a result, the source and day station are all MS7.
A raster OP using a string instruction can be realized even if it is inside.

Areas S0 300, S1 301, D302 are MS7 and FB
There are eight possible combinations when the number is within 6, but these can be realized by combining the processing parts described so far. Bass switch 2 is different for each
The only difference is how to switch 2, 23, and 24, so the description is omitted.

Although the first embodiment of the present invention has been described above, according to this embodiment, a binary raster OP is generated by using the string instruction of the CPU 1 by only providing one set of AG2, AC3 and the bus switches 21-24. Since it can be equally performed for the MS 7, there is an effect that drawing can be performed with the best performance of the bus regardless of the drawing area.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a block diagram of the second embodiment of the present invention. The embodiment of FIG. 1 is suitable for a binary raster OP, whereas the embodiment of FIG. 7 is suitable for a ternary raster OP. The difference in structure is that in FIG.
Increase in G'2 'and SREG'4', ALU5 is 3
This means that the value is input and the number of switching contacts A'of the address bus switch 21 is increased. Along with this, the control of AC3 is slightly different. FIG. 8 shows a flow of the operation by the configuration of FIG. The difference from the control in Fig. 3 is AG'2 'and SREG'.
The only difference is that the additional processing for 4'is added. Those skilled in the art can easily expand the operation to the ternary raster OP by observing the operation described in the first embodiment, and thus detailed description thereof will be omitted. According to this embodiment, the ternary raster OP is FB6 and M.
It can be done at the same speed as S7. FB in the conventional technology
6 and MS7 could not be drawn equally, so the software had to be developed separately, and the processing for MS7 took 5 times or more the time for processing for FB6. Using this embodiment, the drawing software is MS7,
FB6 can be developed in common, and string instructions can be used to increase the bus efficiency to nearly 100%, so it is more than 3 times the raster OP drawing for conventional FB6, and MS7
There is an effect that the speed can be increased more than 15 times.

〔The invention's effect〕

The raster OP is an essential function for superimposing and emphasizing images. Further, drawing on the MS is often used especially for drawing an image to be output to a printer. According to the present invention, not only the drawing of the image displayed on the display but also the drawing of the image output to the printer can be speeded up by a factor of 10 or more. There is an effect that a system with a short time and a good response can be configured.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing a conventional example, and FIGS. 3, 4, and 6 are operation explanation diagrams of the first embodiment, and FIG. 7 (a) and 7 (b) are diagrams showing an example of the configuration of the address generator, FIG. 7 is a diagram showing a second embodiment of the present invention, and FIG. 8 is an operation explanatory diagram of the second embodiment. Is. 1 ... CPU, 2 ... Address generator, 3 ... Access controller, 4 ... Register, 5 ... ALU, 6 ... Frame buffer, 7 ... Main storage, 8 ... Display, 21 ...
Address bus switch, 22 to 24 ... Data bus switch

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Kenichi Saito Kenichi Saito, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Microelectronics Equipment Development Laboratory (72) Inventor Yoshihiro Fujikami Totsuka, Yokohama-shi, Kanagawa 292 Yoshida-cho, Tokyo, Hitachi, Ltd. Microelectronics equipment development laboratory (72) Inventor Takuo Koyama 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Microelectronics equipment development laboratory

Claims (3)

[Claims] 1. A system comprising at least a processor, a first memory group for storing instructions and data of the processor, and a second memory group for storing data to be displayed on a display means, and a logical operation means and the logical operation means. The first switching means for switching and connecting the output of the arithmetic means to the first and second memory groups, the address generating means, the address from the address generating means and the address generated by the processor are switched, A memory access control circuit comprising means for controlling access to the first and second memory groups. 2. A data holding means for temporarily holding data, the output of which is connected to the logical operation means, a data bus of the processor, a data bus of the first memory group, and the data bus of the first memory group. Second switching means for switching the data bus of the second memory group to connect to the data holding means or the logical operation means, the data bus of the first memory group, the data bus of the microprocessor and the data bus of the microprocessor. The memory access control circuit according to claim 1, further comprising a third switching means for switching and connecting the output of the logical operation means. 3. A system having at least a processor, a first memory group for storing instructions and data of the processor, and a second memory group for storing data to be displayed on a display means. One or more systems of address generating means for generating addresses of the memory group, one or more sets of data storing means for storing data stored at the addresses generated by the means for generating the addresses, logical operation means, and the micro A first connection for switching the address of the processor and the address generated by the address generating means and connecting to the address input of the first and second memory groups
A switching connection means, a data bus of the microprocessor, a data bus of the first memory group, and a data bus of the second memory group are connected to the input of the data storage means or the logical operation means by switching. 2 switch connection means, 3rd switch connection means for switching and connecting the data bus of the microprocessor and the output of the logical operation means to the data bus of the first memory group, and the data of the second memory group. A bus is provided with fourth switching connection means for switching and connecting the data bus of the microprocessor and the output of the logical operation means, and means for controlling the first, second, third and fourth switching connection means. A memory access control circuit characterized by the above.