JPH0782456B2 - Cache control method - Google Patents

Description

The present invention relates to, for example, a cache control method for accelerating access to a main storage device, and more particularly to a module processing method thereof.

[Prior Art] FIG. 2 is a block diagram showing, for example, a conventional cache control system, and FIG. 3 is a memory layout diagram of modules stored in a main storage device. In FIG. so,
It consists of a large-capacity, low-speed RAM, and modules (module information, module instructions, module data) are programmed and stored.

(2a) is a central processing unit (CPU), which divides the cache memory into instructions and operands in order to speed up access to a large-capacity, low-speed main memory (1), and stores instructions and data. A cache control method for fetching is used to improve the instruction execution speed of the central processing unit (2a).

(3a) is an instruction cache, which is composed of high-speed, low-capacity RAM, and the central processing unit (2a) takes in the module instructions stored in the low-speed, large-capacity main memory (1), and stores it in the main memory. Speed up access to (1).

(4a) Operand cache, high-speed, low-capacity RAM
The central processing unit (2a) fetches the module information and the module data stored in the low-speed and large-capacity main memory unit (1) to speed up the access to the main memory unit (1).

An instruction control unit (5) decodes the module instruction from the instruction cache (3a) and controls each unit of the CPU.
(6) is an arithmetic processing unit, which is an operand cache (4a)
The module data from is processed.

A memory bus (7) transfers module instructions from the main memory (1) to the instruction cache (3a). Further, the module data is transferred from the main memory (1) to the operand cache (4a). An instruction bus (8) transfers module instructions from the instruction cache (3a) to the instruction control unit (5). An operand bus (9) transfers module data from the operand cache 4a to the arithmetic processing unit (6). Reference numeral (20) is module information, and information indicating the size of arguments used in module instructions and module data is stored in the main storage device (1).

(21) is a module command, which is arranged and stored in the main storage device (1) continuously with the module information (20).
(22) is module data, and the module information (20) and the module instruction (21) are stored in a different memory area.

Since the conventional cache control method is configured as described above, for example, when a program of a module is called while a certain program is being executed, the module information (20) stored in the main storage device (1) is Memory bus (7)
Via the path (a) passing through the operand cache (4a) and the operand bus (9). At that time, a block in which the transferred module information (20) exists (for example, module information in which one block consists of 16 bytes) is registered in the operand cache (4a). Then, the arithmetic processing unit (6) performs a module calling process based on the module information (20), and then executes a module instruction (21) stored in the main storage device (1) via the memory bus (7). It is read into the instruction control unit (5) via a route passing through the instruction cache (3a) and the instruction bus (8). And
The instruction control unit (5) decodes the module instruction (21) and executes the instruction.

[Problems to be Solved by the Invention] In the conventional cache control method as described above, when calling a module, the module information stored in the main storage device is called into the operand cache, and a block of module information that is used only once To register
There is a problem that the utilization efficiency of the operand cache decreases.

In addition, there is a problem that when the instruction execution of the module is started, the probability that the instruction of the module is hit in the instruction cache is low and the instruction access becomes long.

The present invention has been made to solve the above problems, and improves the utilization efficiency of the operand cache.
An object of the present invention is to obtain a cache control method capable of improving the hit rate of the instruction cache and shortening the time from the module call to the start of the module instruction.

[Means for Solving the Problem] In the cache control method according to the present invention, a program module has a main memory in which information regarding the module and an instruction string in which the processing of the module is described are arranged in succession. When the processing of the module is started, information about the module is read from the main storage device via the instruction cache and arithmetic processing is performed, and at the same time, a block in which the information about the module exists in the instruction cache is registered.

[Operation] In the present invention, when a module program is called, the module information stored in the main memory and the beginning of the module instruction are stored in the instruction cache via the memory bus, and the module information is stored. When the module instruction is transferred to the arithmetic processing unit and the module instruction is read from the main storage device based on the module information, the head of the module instruction is read from the instruction cache.

[Embodiment] FIG. 1 is a block diagram of a cache control system according to an embodiment of the present invention, and (1), (5) to (9) are exactly the same as those of the conventional device. The memory layout of the modules stored in the main memory is the same as in FIG.

In the figure, (2) is a central processing unit (CPU), which is a cache memory divided into instructions and operands in order to speed up access to a large-capacity, low-speed main memory (1). By improving the hit rate and the utilization efficiency, the time from the call of the module to the start of the instruction of the module is shortened, and the instruction execution speed of the central processing unit (2) is improved.

Reference numeral (3) is an instruction cache, which is composed of a high-speed and low-capacity RAM, receives the module information and the module instruction stored in the main storage device (1) by the central processing unit (2), and stores them in the main storage device (1). ) To speed up access to.

(4) is an operand cache, which has high speed and low capacity RA
The central processing unit (2) receives the module data (22) stored in the main storage device (1) and speeds up access to the main storage device (1).

(10) is a module information bus, which is provided with a bus line between the instruction cache (3) and the arithmetic processing unit (6),
The central processing unit (2) transfers the module information from the instruction cache (3) to the arithmetic processing unit (7).

In the cache control method configured as described above, when a program of a module is called while a certain program is being executed, the central processing unit (2) stores the module information (20) stored in the main storage device (1). ) And the beginning of the module instruction (21) are transferred to the instruction cache (3) via the memory bus (7).

At that time, when the central processing unit (2) judges that the module information (20) exists in the instruction cache (3), the module information (20) is calculated via the module information bus (10). The data is transferred to the processing unit (6).

On the other hand, when the central processing unit (2) judges that the module information (20) does not exist in the instruction cache (3),
Module information stored in the main memory (1) (2
0) through the memory bus (7) to the instruction cache (3) and module information bus (10) (A)
The module information (20) is transferred to the arithmetic processing unit (6) via the, and the block in which the module information (20) and the head of the module instruction (21) exist in the instruction cache (3) is registered.

Subsequently, the central processing unit (2) uses the instruction cache (3).
When it is determined that the head of the module instruction (21) exists in the command instruction (21), the head of the module instruction (21) is transferred to the instruction control unit (5) via the instruction bus (8).

Then, the command control unit (5) uses the module command (21).
Decode the beginning of and execute the module instruction.

On the other hand, when the central processing unit (2) determines that the head of the module instruction (21) does not exist in the instruction cache (3), the head of the module instruction (21) stored in the main memory (1) is deleted. Transfer to the instruction cache (3) via the memory bus (7) and transfer from the instruction cache (3) to the instruction control unit (5) via the memory bus (7).

Then, the command control unit (5) causes the module command (2
1) Decode the beginning of and execute the module instruction.

In this way, when calling the program of the module, when the module information (20) is transferred to the arithmetic processing unit (6), the module information (2) is stored in the instruction cache (3).
Since the block in which 0) and the head of the module instruction (21) exist is registered, there is a high probability that the head of the module instruction (21) exists in the instruction cache (3), and the instruction cache (3) is hit. The rate can be improved.
Further, the operand cache (4) can improve the utilization efficiency of the operand cache (4) without registering the module information (20) and the beginning of the module instruction (21).

[Effects of the Invention] As described above, according to the present invention, the module information stored in the main memory and the head of the module instruction are transferred to the instruction cache and registered, whereby the instruction cache hit rate is increased. And the utilization efficiency of the operand cache are also improved, and the processing speed of the central processing unit can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a cache control system according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional cache control system, and FIG. 3 is a memory layout diagram of modules stored in a main storage device. . In the figure, (1) is a main storage device, (2) is a central processing unit, (3) is an instruction cache, (4) is an operand cache, (5) is an instruction control unit, and (6) is an arithmetic processing unit. , (10) is a module information bus. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a cache control system in which a cache memory in a central processing unit is divided into an instruction cache and an operand cache, a program module stores information about the module and processing of the module in a main memory. When starting the processing of the module in which the instruction sequence that is continuously arranged, the information about the module is read from the main storage device through the instruction cache and arithmetic processing is performed, and at the same time, the module is stored in the instruction cache. A cache control method characterized by registering a block in which information regarding information exists.