JPH05233523A - Inter-processor data transfer device - Google Patents

Abstract

PURPOSE:To transfer the data at a high speed between such processors as a main processor, a graphic processor, etc. CONSTITUTION:A transfer buffer 7 is controlled by a data transfer controller 6 which performs the DMA transfer of data. A main processor 1 reeds the information on the position of the controller 6 where the date are written in the buffer 7 from the processor 1 before the transfer of date. If this position information is correct, the date are written in the buffer 7. If not, the processor 1 is kept waiting until the buffer 7 becomes idle. The controller 6 calculates the new position information after the position information is reed by the processor 1 and then updates this information. This updating of the information is reported to the processor 1, and the discontinuation state of the processor 1 is canceled. At the same time, the controller 6 repeats the transfer of data to 8 graphic processor 3 as long as the buffer 7 stores the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transfer between processors of a processor having a plurality of processors, and especially between processors suitable for a graphics system requiring a smooth display screen changing process such as a moving image. Data transfer device.

[0002]

2. Description of the Related Art The application field of computer graphics is expanding to visual simulation and visualization of scientific and technological calculation results, and the demand for high-speed drawing for display performance is further increasing. Conventionally, as a hardware technology that responds to such a demand for high speed, graphic processing such as coordinate conversion and clipping is processed by a dedicated processor, and a display list that is graphic data created by the main processor is collectively and rapidly drawn. It is realized by doing.

More recently, in the above-mentioned application fields, since a different graphic is often displayed for each display rather than changing and displaying a display list created once, it is troublesome to create the display list. The immediate mode method, which becomes a bottleneck and directly issues graphic data (drawing command) to the graphics processor, is becoming mainstream. In order to process this immediate mode method at high speed, the data transfer performance between the main processor and the graphics processor becomes a problem.
Since the conventional direct memory access (DMA) method has a large overhead of starting and ending reports for small unit data transfer such as drawing instruction, a method of directly connecting the main processor and the graphics processor with a high-speed bus. Alternatively, a method in which a graphics processor has a FIFO is used.

Regarding the hardware technology of computer graphics, "Visualization Machine; Mitsuo Ishii;
Ohmsha Co., Ltd .; pp. 21-27 "for display list and immediate mode" Nikkei CG; 1
July 991, Issue 58; Nikkei BP, page 249 "
Further, the DMA transfer is described in "68000 Microcomputer; Yuzo Kida, Yoshimune Hagiwara, Kazuhiko Iwasaki; Maruzen Co., Ltd .; 120-126, 220-223".

[0005]

The above-described method of connecting the main processor and the graphics processor with a high-speed bus requires a dedicated bus, which increases the hardware cost, and the main processor even in the FIFO system. And FI
Since data is transferred in units of words between FOs, even if the bus has a high-speed transfer means such as block transfer, it is not effectively used. In order to maximize the data transfer performance between processors, it is necessary to transfer in a unit such as block transfer, but in DMA transfer suitable for such transfer, the start and end reporting processes have overhead. It is an object of the present invention to provide a high speed data transfer device between a main processor and a processor such as a graphics processor.

[0006]

The data transfer device is provided with the following means. Means for designating a position in a transfer buffer for storing a data string transferred from the main processor and accumulating position information to be read when the main processor starts data transfer; and the position information read by the main processor is incorrect. A value that indicates that the main processor has entered a stopped state when the value is a value, means for setting by the main processor, and means for updating the position information in response to the reading of the position information by the main processor; A means for instructing the main processor to cancel the stopped state of the main processor if the specific value is set when the position information is updated.

Further, the following means can be further provided. Graphics in the transfer buffer
Means for obtaining and storing the data length of the data to be transferred to the processor and the position in the transfer buffer for starting the next data transfer; and means for transferring the data of the data length from the transfer buffer to the graphics processor .. Further, a means for accumulating position information may be provided in the transfer device for each data length to be transferred. The transfer device may also be built into the graphics processor.

[0008]

The transfer device for performing the DMA transfer manages the transfer buffer, the main processor reads the position information set in the transfer device before the transfer, and if the position information is correct, writes the data in the transfer buffer. , If it is not correct, stop because it waits for a free transfer buffer.
When the main processor reads the position information, the transfer device calculates and updates new position information, informs the main processor of the update, and cancels the stopped state. At the same time, the transfer device repeats the process of transferring the data to the graphics processor if there is data in the transfer buffer. Further, by providing a plurality of means for accumulating the position information, the position information can be read according to the length of the data to be transferred, and the processing for setting the length of the data to be transferred by the main processor becomes unnecessary.

[0009]

EXAMPLES An example of the present invention will be described in detail below.
FIG. 1 is a block diagram of a data processing device to which the present invention is applied, which is an example in which the present invention is applied to data transfer between a CPU and a graphic processor. In FIG. 1, reference numeral 1 denotes a main processor, which is operated by an operating system and a user program stored in the main memory 2. Reference numeral 3 is a graphics processor, which draws in the frame memory 5 by interpreting and executing a drawing command sent from the main processor 1 by a program stored in the local memory of 4. A data transfer controller 6 transfers the drawing command generated by the main processor 1 in the transfer buffer 7 on the main memory 2 to the graphics processor 3 via the FIFO 8.
At the time of this transfer, the main processor 1 and the data transfer controller 6 access the main memory 2, and such access between processors is controlled by the bus controller 9.

FIG. 2 is a detailed block diagram of the data transfer controller 6, which includes a control circuit 10 for controlling transfer between processors, a control program memory 11 in which a program for the control is stored, and a large number of registers ( 12
~ 24).

Each register will be described below. AD
The DRESS register 12 is a position information register indicating the beginning of the writable address of the transfer buffer, and is L
The ENGTH register 13 is a data length register indicating the length of the drawing command to be written. TOP register 14 and BO
The TTOM register 15 is a register indicating the address of the transfer buffer 7, and is a buffer start address register indicating the beginning of the buffer and a buffer end address register indicating the next address of the buffer end. The MAX register 16 is a maximum data length register for instructing the maximum length of a drawing command transferred at one time, and the transfer buffer 7
Must be less than half the length of INI
The TAIL register 17 is an initialization register for initializing the data transfer controller 6 and is initialized by writing an arbitrary value.

The HEAD register 18 and the TAIL register 19 are a transfer start position register indicating the start address of the drawing command written in the transfer buffer and a transfer end address indicating the address next to the end address. Manage by the Robin method. However, since it is necessary to write one drawing command to consecutive addresses without fail, when the drawing command is divided at the end of the transfer buffer 7, the drawing command is written from the start address and the invalid data address at the end is set to LIMIT. As shown in the invalid position register of the register 20. FLAG register 2
Reference numeral 1 is a waiting state register that stores that the main processor is waiting when the write area in the transfer buffer 7 is exhausted, and the data transfer controller 6 has a writable area in the transfer buffer 7. Sometimes it reports to the main processor with an interrupt. The TMP1 register and the TMP2 register are working registers of the data transfer controller 6.

The registers 12 to 17 are accessible by the main processor. When the main processor accesses the ADDRESS register 12, an interrupt processing program stored in a control program memory 11 to be described later operates. And

A data transfer processing procedure in the embodiment of the present invention will now be described with reference to FIGS. 3 to 8 are flowcharts of processing means executed until the drawing command generated by the main processor 1 is written in the transfer buffer 7, and the drawing command written by the data transfer controller 6 is transferred to the graphics processor 3. Is shown. Each of the flowcharts shows the processing for initializing the data transfer controller 6 in FIGS. 3 and 4, the processing until the main processor 1 writes a drawing command in the data transfer buffer 7 in FIG. 5, and FIG. 8 shows a process in which the data transfer controller 6 reads a drawing command from the transfer buffer 7 and transfers it to the graphics processor 3. The symbolic names used in the flowchart are the symbolic names of the registers of the data transfer controller 6 shown in FIG. Further, the symbol ":" means that what is described on the left side of the symbol is compared with that described on the right side. The details of each flowchart will be described below.

(1) Initialization of the data transfer controller 6 In the initialization processing of the data transfer controller 6 shown in FIGS. 3 and 4, the main processor instructs the data transfer controller 6 to perform initialization (FIG. 3). The data transfer controller 6 is divided into processes for initializing the registers (FIG. 4).

In FIG. 3, the main processor is the main memory 2
A transfer buffer is secured above (for example, about 4 kilobytes), and the top address of the transfer buffer 7 is TOP.
In the register 14, the address next to the end address is BOT
Set in the TOM register 15 (30, 31). Next, the maximum length of drawing commands (for example, 64 bytes) is set to MAX.
It is set in the register 16 (32), and "0" is written in the INITIAL register 17 to instruct initialization of the data transfer controller 6 (33). The data transfer controller 6 executes the processing shown in FIG. 4 by writing to the INITIAL register 17.

In FIG. 4, the data transfer controller 6
Sets "0" in the ADDRESS register 12 and the LENGTH register 13 (34, 35). HEAD
Main processor 1 in register 18 and TAIL register 19
Set the value of the TOP register 14 set by (37),
The value of the BOTTOM register 15 is set in the LIMIT register 20 (38). FLAG register 21 is "0"
Is set (39).

(2) Writing of Drawing Command FIG. 5 shows an example of processing in which the main processor writes a drawing command into the transfer buffer 7. FIG. 5 is a drawing command line command (“command code”, consisting of “X coordinate” and “Y coordinate” at the start point of the line segment and “X coordinate” and “Y coordinate” at the end point. This is an example of a process of continuously writing (in bytes) to the transfer buffer 7. In FIG. 5, the LENGTH register 13 sets "20" which is the length of the line command (40).
ADDRESS register 1 of data transfer controller 6
2 is read and the value is a variable W (area name in the main memory 2 for temporarily storing the value calculated by the main processor 1)
(41).

Next, the processes from 43 to 49 are repeated until the line command data is completed (42). AD
The value of the variable W read from the DRESS register 12 is
It indicates the address of the writable transfer buffer, or indicates an invalid value (“0” in the example). Therefore, check whether the buffer has the correct address (4
3) If the value is correct, write a 20-byte line command to the indicated address (44), and ADDRE again.
The SS register 12 is read and the value is set in the variable W. By reading this ADDRESS register,
The data transfer controller 6 starts reading the written line command. In the buffer check processing (43), when the value of the variable W is "0", (4
6), write “1” to the FLAG register (47),
The process is stopped (48) until an interrupt is reported by the data transfer controller. When the interrupt is reported and the processing is restarted, the ADDRESS register 12 is read again and the value is set in the variable W.

(3) Reading of drawing command The data transfer controller 6 after initialization repeats the processing shown in FIGS. 6 and 7. However, if the transfer buffer 7 has no drawing command, as shown in FIG.
8 and TAIL register 19 have the same value, processing 5
Only 0 is repeated.

When the ADDRESS register 12 is read, an interrupt occurs in the data transfer controller 6, and the process shown in FIG. 8 is executed if the interrupt is not in the disabled state. In FIG. 8, the ADDRESS register 12
Is not "0" (65), TAIL register 1
The value of the LENGTH register 13 (set before reading the ADDRESS register 12) is added to 9 (66). Then, as will be described later, the TAIL register 19 is updated and ADDRE is updated by the round robin method.
The value of the SS register 12 is calculated (67 to 74). AD
In the calculation of the DRESS register 12, if there is a free space in the transfer buffer, the value of the TAIL register 19 is returned to the main processor as a register read value (69, 74),
If there is no free space in the transfer buffer, "0" is returned (7
3). In FIG. 8, the substitution of the value in the ADDRESS register 12 means the update of the ADDRESS register 12 and the reply to the main processor.

Round robin update processing is performed by HEA.
Compare the D register 18 and the TAIL register 19 (6
7), when the value of HEAD register 18 is small, BOT
The value obtained by subtracting the value of the MAX register 16 from the TOM register 15 is compared with the value of the TAIL register 19 (68),
If the value of the TAIL register 19 is smaller or equal, the value of the TAIL register 19 is set in the ADDRESS register 12 (69). On the contrary, TAIL register 1
If 9 is large, the value of the TAIL register 19 is substituted into the LIMIT register 20 (70), and the value of the TOP register 14 is set in the TAIL register 19 (71). Next, H
The value obtained by subtracting the MAX register 16 from the EAD register 18 is compared with the value of the TAIL register 19 (72).
The value of is substituted into the ADDRESS register 12 (73,
74).

Since the TAIL register 19 is updated by the processing shown in FIG. 8, the data transfer controller is shown in FIG.
Then, the data transfer is started according to the processing shown in FIG.
In FIG. 6, since the HEAD register 18 and the TAIL register 19 have different values (50), the length of data read from the transfer buffer is calculated (51) (described later with reference to FIG. 7). In the calculation of the data transfer length (51), the TMP
1 Register 22 sets the data transfer length to the new HE after the transfer.
The value of the AD register 18 is set in the TMP2 register 23. Therefore, the data transfer controller 6 starts the TMP from the address of the transfer buffer 7 indicated by the HEAD register 18.
Read data by the number of bytes indicated by 1 register 22,
The read data is written to the FIFO 8 and data transfer is executed (52). After data transfer, HEAD register 1
The value of the TMP2 register 23 is set to 8 (53). Next, when the value of the ADDRESS register 12 is "0" (54) and the value of the FLAG register 21 is not "0" (55), the main processor 1 is waiting for the transfer buffer to be empty. , Reports an interrupt to the main processor 1 (56), and sets "0" in the FLAG register 21.

In the process of calculating the transfer data length in FIG. 7, the interrupt is prohibited so that the interrupt process shown in FIG. 8 does not operate during the calculation (58). Next, HEAD
Compare the values of register 18 and TAIL register 19 (5
9), if the value of HEAD register 18 is small, TAI
The result of subtracting the value of the HEAD register 18 from the L register 19 is set in the TMP1 register 22 (60), and TM
The value of the TAIL register 19 is set in the P2 register 23. On the contrary, if the value of TAIL register 19 is small, L
The value obtained by subtracting the HEAD register 18 from the IMIT register 20 is set in the TMP1 register 22 (62), and TM
The value of the TOP register 14 is set in the P2 register 23 (63). After setting, cancel interrupt disable.

By the processing shown in FIGS. 3 to 8 above,
Data transfer from the main processor 1 to the graphics processor 3 can be realized. According to this embodiment, when the load of the graphics processor 3 becomes larger than that of the main processor 1 and the FIFO 8 becomes full, the data transfer controller 6 stops at the writing to the FIFO 8, but the interrupt shown in FIG. By enabling the processing, the drawing command can be continuously written in the transfer buffer 7 of the main processor 1. Since the unit in which the data transfer controller reads data from the transfer buffer 7 can always read one or more drawing commands continuously, high-speed transfer such as burst transfer is possible. Further, the interrupt from the data transfer controller 6 to the main processor 1 is made only when the transfer buffer 7 becomes full, and the overhead of the interrupt is from the graphics processor side to the main processor in the conventional DMA transfer. It can be reduced as compared with the case of the interruption.

In the above-mentioned embodiment, the data transfer controller 6 is applied to the graphics processor 3 side, but as another example, it may be applied to a bus controller as shown in FIG. Also in FIG. 9, FIG.
Therefore, the processing of FIG. 8 is applicable. In the example of FIG. 9, FI
Data transfer controller 6 when FO8 is full
Since it cannot be stopped, it is necessary to realize the notification for notifying the data transfer controller 6 that the FIFO 8 is full and the notification for notifying the data transfer controller 6 that the FIFO 8 is available by means of interrupt processing or the like. However, the main processor can access the registers in the data transfer controller 6 at high speed.

In the example of the processing shown in FIG. 5, most of the accesses from the main processor to the registers in the data transfer controller 6 are made by the ADDRESS register 12.
Is reading. A block diagram for speeding up this register reading is shown in FIG. In FIG. 10, CO
The PY register 80 is the ADD of the data transfer controller 6.
This is a register having a copy of the value of the RESS register 12, and an instruction from the main processor, that is, an instruction to read the value of the ADDRESS register 12 from the copy register is written in the EXEC register 81 (for example, "0" is written as the instruction. ), The bus controller 9 performs ADDR by this writing.
The ESS register 12 is read, and the COPY register 80
Set the value to.

FIG. 11 shows an example of a drawing process of the main processor 1 corresponding to the block diagram of FIG. 10 by modifying the process of FIG.
Shown in. In FIG. 5, the process of reading the ADDRESS register 12 and setting the value in the variable W (40, 45,
49) is divided into two processes, a process of setting “0” in the EXEC register 81 (82, 83, 85) and a process of reading a value from the COPY register 80 and setting it in the variable W (84, 86). Other than that, the processes of FIG. 5 and FIG. 11 are the same. The main processor 1 is the ADDRESS register 12
It becomes unnecessary to wait for the reading of the data, and when the data is read into the register of the bus controller 9 faster than the data transfer controller 6, the drawing process becomes faster.

Further, in the above-described embodiment, before the main processor 1 reads the ADDRESS register 12, the length of the drawing command to be written in advance is set to the LENGTH register 1.
It was necessary to set it to 3, but by providing a plurality of ADDRESS registers (90 to 93) for each length of data to be transferred, as shown in FIG.
It is possible to eliminate the H register 13 and reduce the overhead of setting the LENGTH register 13 when the lengths of drawing commands to be transferred are different. For example, in FIG. 12, ADDRES
S1 register 90 is for 4 bytes of "instruction code" only,
The ADDRESS2 register 91 is for 8 bytes of "instruction code" and "data", the ADDRESS3 register 92 is for 12 bytes of "instruction code" and "X coordinate", "Y coordinate", and the ADDRESS4 register 93 is used in the above-mentioned embodiment. It can be used for 20 bytes. In the example of the processing shown in FIG. 5, the ADDRESS register 12
Is read from the ADDRESS4 register 93, and when drawing commands of other lengths are written, the ADDRESS register corresponding to each is read.

Further, in the above-mentioned embodiment, the availability of the transfer buffer 7 is judged depending on whether the value read from the ADDRESS register 12 is "0".
It can also be realized by reporting a bus error to the main processor 1 when the register 12 is read and stopping the processing of the main processor 1. According to this, when the interrupt is reported from the data transfer controller 6, by restarting the stopped processing, it is possible to reduce the overhead required for the address determination in the main processor 1.

[0031]

As described above, according to the present invention, the DMA transfer can be performed without the overhead of the end report processing, so that the high-speed data transfer between the processors can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a data processing device to which the present invention is applied.

FIG. 2 is a detailed block diagram of a data transfer controller.

FIG. 3 is a diagram showing a flowchart of initialization setting processing of a data transfer controller.

FIG. 4 is a diagram showing a flowchart of initialization setting processing in a data transfer controller.

FIG. 5 is a diagram showing a flowchart of drawing processing.

FIG. 6 is a diagram showing a flowchart of main processing of a data transfer controller.

FIG. 7 is a diagram showing a flowchart of a process of calculating a data transfer length.

FIG. 8 is a diagram showing a flowchart of an interrupt process of the data transfer controller.

FIG. 9 is a block diagram of a data processing device in which a data transfer controller is applied to a bus controller.

FIG. 10 is a block diagram of a data processing device that speeds up register reading.

11 is a diagram showing a flowchart of a drawing process in the configuration of FIG.

FIG. 12 is a detailed block diagram of a data transfer controller having a plurality of ADDRESS registers.

[Explanation of symbols]

 1 Main Processor 2 Main Memory 3 Graphics Processor 4 Local Memory 5 Frame Memory 6 Data Transfer Controller 7 Transfer Buffer 8 FIFO 9 Bus Controller

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masato Manda 5030 Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Software Development Division, Hitachi, Ltd. (72) Toshiyuki Kuwana 5-chome, Omika-cho, Hitachi, Ibaraki No. 1 stock company Hitachi Ltd. Omika factory

Claims (4)

[Claims] 1. A data transfer apparatus for controlling transfer of data from a first processor to a second processor via a transfer buffer, the transfer comprising storing a data string transferred from the first processor. Means for designating a position in the data buffer and accumulating position information to be read when the first processor starts data transfer, and a first processor when the position information read by the first processor is an incorrect value Means for setting a specific value indicating that the state has entered a stop state by the first processor, means for updating the position information in response to the reading of the position information by the first processor, and the position Means for instructing the first processor to release the halt state of the first processor if the specific value is set when the information is updated. For example, the data transfer device being characterized in that so as to transfer the data transferred to the transfer buffer from the first processor when the location information is not invalid value to the second processor. 2. The data transfer device according to claim 1, wherein the data length of data to be transferred to the second processor in the transfer buffer and the position in the transfer buffer at which the next data transfer is started are obtained. A data transfer apparatus comprising: a storage unit; and a unit that transfers data of the data length from the transfer buffer to a second processor. 3. The data transfer device according to claim 1, wherein the length of the remaining area in the transfer buffer capable of storing the data string is transferred from the transfer buffer to the second processor at one time. Is less than the maximum data length,
A data transfer device comprising means for updating the position information so as to update the position information to information indicating a leading position of a transfer buffer. 4. The data transfer apparatus according to any one of claims 1 to 3, further comprising means for accumulating the position information corresponding to each length of a data string to be transferred. Characteristic data transfer device.