JPH0877371A - Image forming device - Google Patents

Abstract

PURPOSE: To minimize the number of times of access to an external memory by an MPU, to shorten processing time and to improve the plotting performance of a surface painting. CONSTITUTION: This device is provided with an external memory 61 storing source data, an external memory 62 storing destination data and an MPU 33 having a bus of 2<n> byte. The MPU 33 holds the source data read by a 2<n> byte unit till the data of 2<n> byte is collected for performing a boundary length conversion to destination data for the source data, and writes the source data in the destination of the external memory 62 by the 2<n> byte unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus for performing boundary length conversion processing of image data and performing surface painting of a closed polygon using a raster expansion hardware section.

In a computer system having a plurality of LSIs (large-scale integrated circuits), the widths of buses connecting them may not be uniformized. Along with this, it is necessary to convert the boundary length of data to be processed by an MPU (microprocessor unit) and make it the same number of bytes as the bus width of the LSI to be processed next.

For the MPU, the memory in which the data to be processed exists and the memory in which the data after the boundary length conversion by the MPU is written correspond to the external memory. today,
The processing speed of the MPU becomes faster, and the number of operation clocks with the external memory tends to open. Therefore, it is necessary to minimize the number of times the MPU accesses the external memory, which is slower than the internal memory, and shorten the processing time.

Further, it is desired to improve the performance of surface painting of a closed polygon specified by the user.

[0005]

2. Description of the Related Art FIG. 25 is an explanatory diagram of a conventional example and shows a conventional data boundary length conversion process. In this figure, one square is one byte (8 bits), a shaded square is a blank (NULL) byte, and the external memory storing the data to be processed by the MPU is the source (SRC). The external memory that stores the data after the boundary length conversion processing by the MPU is the destination (DST) area.

FIG. 25 shows an MPU process for converting 8-bit boundary length data of 3 bytes per line, which is one data unit, into 16-bit boundary length data. The MPU reads 1 byte at a time from the source area of the external memory to the destination area of the external memory.
Write (READ / WRITE) access to 1
A blank byte is added to match the boundary length when writing the last byte of the line.

In this case, until the completion of one line of the destination, the MPU had to access the external memory three times, three times for reading and four times for writing. In addition, in the conventional closed polygon surface painting processing, the outer frame of the closed polygon is obtained by coordinate values, and each parallel coordinate is drawn by using a line drawing hardware to create a closed polygon. Had been achieved.

[0008]

SUMMARY OF THE INVENTION The above-mentioned conventional devices have the following problems. In the conventional data boundary length conversion processing, the MPU reads the data for which the boundary length is to be converted from the low-speed external memory for each byte, or the MPU converts the boundary length for each byte at a low speed. Is writing to external memory. Therefore, the process of converting the boundary length has a performance problem in terms of processing time.

Further, in the surface painting processing of the closed polygon, since all coordinate values of the outer frame of the closed polygon are calculated by the MPU, there is a problem in the performance of the surface coating processing apparatus. The present invention solves such a conventional problem, and the MPU performs READ / WRITE to the external memory with the same number of bytes as the bus width of the MPU, thereby minimizing the number of accesses to the low-speed external memory and processing. An object of the present invention is to provide an image forming apparatus that improves the drawing performance of surface painting by shortening the time and using a raster expansion hardware unit and a transfer hardware unit for outline data.

[0010]

In order to solve the above-mentioned problems, the present invention has the following constitution. FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, the data processing unit 3 is connected to an external memory 61, an external memory 62, an imaging hardware unit (IHW) 4 and a bus (BUS). The data processing unit 3 includes a microprocessor (M
A program area 31 in which a program for operating the PU) 33 and the MPU is stored, and an internal memory 32 such as a cache memory that can be accessed by the MPU at high speed are provided.

Data to be processed by the MPU 33 is stored in the external memory 61, and the source (SR) of the MPU 33 is stored in the external memory 61.
C). The external memory 62 is the MPU 33.
The data converted to the desired boundary length is stored,
This is the destination (DST) of the MPU 33. The imaging hardware unit 4 is an LSI that uses the data converted by the MPU 33 of the data processing unit 3.
It is a hardware configured of the above.

[0012]

The operation of the present invention based on the above configuration will be described.
1 to 3 show the data flow of boundary length conversion.

The MPU 33 reads data from the external memory 61 with the maximum number of bytes of the MPU bus width. next,
The MPU 33 uses the internal memory 32 to perform boundary length conversion work. The data converted by the MPU 33 is written in the external memory 62 with the maximum number of bytes of the MPU bus width. After that, the imaging hardware unit 4 processes using the data of the external memory 62.

In the closed polygonal surface painting process, the vertex coordinates of the closed polygon specified by the user are converted into outline data by the MPU 33 and written in the external memory 62, and then the data in the external memory 62 is imaged. The raster expansion hardware unit of the outline data of the hardware unit 4 fills the inside and transfers it to the drawing destination using the transfer hardware unit.

Therefore, in the image forming apparatus according to the present invention, the boundary length conversion performance can be improved by speeding up the boundary length conversion work.

[0016]

2 to 24 are views showing an embodiment of the present invention. Embodiments of the present invention will be described below with reference to the drawings.

§1. Description of Printing Device FIG. 2 is an explanatory diagram of the printing device. The printing device connected to the host 1, which is a higher-level device, includes an input control unit 2, a data processing unit 3, an imaging hardware unit (IHW) 4, and a system. A control unit 5, a memory unit 6, and a printing unit 7 are provided.
Then, each of the above parts is controlled by a control bus (C
-BUS), a memory bus (M-BUS), an image bus (I-BUS), and an IHW bus (H-BUS).

The input control unit 2 includes an MPU, a memory, and an MPU.
It is composed of a peripheral LSI, a channel control LSI, a communication control LSI, etc., and communicates with the host 1 and
The data sent from the printer is converted into page buffer data in the printing apparatus or transferred to the Haffa memory in the memory unit 6.

The data processing unit 3 includes an MPU 33 and an MPU.
An internal memory 32, which is an internal work memory of 33, is provided, and the data processing unit 3 further breaks the data created by the input control unit 2 into an imaging hardware unit 4.
The firmware interface is converted to the firmware interface, and the imaging hardware unit 4 is activated and controlled.

Imaging hardware unit (IHW) 4
Is a hardware unit that performs drawing processing. The system control unit 5 is connected to an operation panel 8, a floppy disk (FPD) 9, a hard disk (HDD) 10, a terminal 11 and the like.
PU, memory, MPU peripheral control LSI, floppy control LSI, hard disk control LSI, communication control LSI
Etc., and manages the entire control unit of the printing apparatus.

The memory unit 6 serves as an external memory of the MPU 33, and the memory unit 6 includes the main memory 6
3, outline data storage unit 64, raster expansion hardware unit work memory 65, bitmap memory (BMM) 6
6. A printer controller (PRC) 67 and the like are provided, and the main memory 63 stores various data and tables. The outline data storage unit 64 stores outline data for the raster expansion hardware unit. The raster expansion hardware unit work memory 65 stores the raster data expanded by the raster expansion hardware unit. The bitmap memory (BMM) 66 stores image data to be printed out.
The printer control unit (PRC) 67 controls to send the contents of the bitmap memory 66 to the printing unit 7.

The printing unit 7 prints the data sent from the bit map memory 66. FIG. 3 is an explanatory diagram of the imaging hardware unit (IHW).

FIG. 3 is a detailed diagram of the imaging hardware unit 4 of FIG. In FIG. 3, the control bus (C-BUS), the memory bus (M-BUS), the image bus (I-BUS), and the IHW bus (I-BUS) are divided into data and addresses, respectively.

DV is a driver, RV is a receiver, and movers 1 to 4 are data movers for supplying data to each imaging hardware. The imaging hardware unit 4 is a transfer hardware unit (RIO) 41 that is hardware that transfers raster data to the bitmap memory 66, and a raster expansion hardware unit (OFG2) 42 that is hardware that converts outline data into raster data. , An image decompression unit (IMC) 43 for decompressing image data, a write overlay decompression unit (WOC) 44 for decompressing write overlay data, an image scaling unit (REC) 45 for scaling image data, and a bus switching of the imaging hardware unit 4. It is composed of an adapter controller 46 for controlling.

The transfer hardware unit 41 includes a FIFO.
A (First In First Out) type request register 41-1 is provided, and the write overlay decompression unit 44 includes a work memory 44-2 and a control unit 44 thereof.
-1 is provided.

§2. Description of Boundary Length Conversion FIG. 4 to FIG. 16 are explanatory diagrams of boundary length conversion processing of image data. (1) Outline of Boundary Length Conversion Process The boundary length conversion process is different from the external memory 61 in which the image data to be processed exists, for example, the main memory 63 of the memory unit 6 and the boundary length of the image data to be processed. This is necessary when there is an LSI having a bus width, for example, the transfer hardware unit 41 of the imaging hardware unit 4.

In this case, the MPU 33 converts the data in the main memory 63 into data in which the bus width of the transfer hardware unit 41 is a boundary length so that the transfer hardware unit 41 can process efficiently. Since the conversion process of the MPU 33 is completed in a short time, the MPU 33 reads the image data (source (SRC) data) of the main memory 63 with the same number of bytes as the bus width of the MPU 33, and the same byte width as the bus width of the MPU 33. The number is written in the outline data storage unit 64 (destination (DST)) which is the external memory 62 used by the transfer hardware unit 41.

FIG. 4 is an explanatory view of the outline of the boundary length conversion processing. In FIG. 4A, 8-bit boundary data on the source (SRC) is converted to 16-bit boundary data on the destination (DST) by a 32-bit bus width M.
It is the boundary length conversion processing procedure which PU converts. FIG.
In (a), one square represents one byte (8 bits), the external memory 61 storing the data to be processed by the MPU is the source (SRC) area, and the data after the boundary length conversion processing by the MPU is The external memory 62 stored is a destination (DST) area.

FIG. 4A shows a process in which data stored in bytes on the source is read by the MPU in units of 4 bytes and written in units of 4 bytes on the destination.

FIG. 4 (b) is a notation in which one data unit length is 6 bytes, and FIG. 4 (c) is a notation in which one data unit length is 7 bytes. Further, FIG. 4D shows the notation of additional data (NULL data).

FIG. 5 is an explanatory diagram of transfer when one data unit length is 6 bytes. FIG. 5 is a boundary length conversion processing procedure in which 8-bit boundary data is converted to 16-bit boundary data by an MPU having a 32-bit bus width. In this case, since one data unit length is 6 bytes, additional data addition processing is performed. It becomes unnecessary.

In this transfer processing procedure, the MPU
Read the 4-byte data "1, 2, 3, 4" on the source, and directly read "1, 2, 3," on the destination.
Write "3, 4". The second time, the MPU reads the next 4-byte data “5, 6, 1, 2” on the source and writes “5, 6, 1, 2” in the destination.
The third time, the MPU reads the next 4-byte data “3, 4, 5, 6” on the source and writes “3, 4, 5, 6” in the destination. Same as below
Is a process of reading data on the source in units of 4 bytes and writing it in the destination in units of 4 bytes.

FIG. 6 is an explanatory diagram of transfer when one data unit length is 3 bytes. FIG. 6 is a boundary length conversion processing procedure in which 8-bit boundary data is converted to 16-bit boundary data by a 32-bit bus width MPU. In this case, one data unit length, which is the horizontal size of image data, is 3 bytes. Therefore, additional processing for adding additional data is required. Further, the MPU has an internal memory of 32 bits or more, and stores the remaining data that cannot be written.

In this transfer processing procedure, the MPU
The 4-byte data “1, 2, 3, 1” on the source is read, and 1-byte data that is blank data (NULL data) is added to the end of the read data in 1-data units. Write on destination as bit units. The remaining (reserved) data "1" at this time is stored in the internal memory of the MPU.

At the second time, the MPU reads the next 4-byte data "2, 3, 1, 2" on the source, and the data unit "1, 2, 1" of the read data and the first remaining data. 3 ”is added to the end of 1” and 1 data unit is written in 16-bit unit on the destination. At this time, the remaining data is 2 of "1, 2"
It becomes a byte.

FIG. 7 is a processing flowchart for adding additional data. Hereinafter, processing numbers S1 to S in FIG.
7 will be described. S1: MPU is 32 bits (4 bytes) from the source
The data is read and the process proceeds to S2.

S2: The MPU reads the read data (DA
It is determined whether or not there is a final byte of one line which is one data unit length in (TA). If there is the last byte of this line in the data read by this judgment (YES) S3
Processing, if there is no last byte (N
O) Move to the processing of S7.

S3: The MPU inserts an additional byte (1 byte data) for boundary alignment after the last byte of all the lines of the read data and moves to the processing of S4. S4: The MPU reads the pending data and the read (R
EAD) data is combined with the data, and the data is written to the destination in units of 4 bytes, and the process proceeds to S5.

S5: The MPU leaves less than 4 bytes of data in the internal memory as reserved data, and proceeds to the processing of S6. S6: The MPU determines if there is no more data on the source to process. If there is no more data on the source to be processed in this determination (YES), this process ends, and if there is more data (NO), the process returns to S1.

S7: When there is no line last byte in the data read in the processing of S2 (NO), the MPU combines the pending data and the read data just read, and the data is transferred to the destination by 4 bytes at a time. Write it above and move to the processing of S5.

(2) Description of Boundary Length Conversion Hereinafter, a boundary length conversion process for converting 8-bit boundary data into 16-bit boundary data by the MPU having a 32-bit bus width will be described. When the length of 1 data unit of 8-bit boundary data is other than 16 bits, 1 byte is added to the end of 1 data unit and 1
Boundary matching is a process in which the number of bytes of the data unit length is set to 16 bits.

FIG. 8 is an explanatory diagram of boundary length conversion.
FIG. 8A is an explanation when the horizontal size which is one data unit length of the image data on the source is 5 bytes. In this case, the MPU adds 1-byte blank (NULL) data to the end of the 5-byte data on the source and transfers the data onto the destination. It should be noted that this blank data is indicated by "0" hereinafter.

FIG. 8B illustrates the case where the horizontal size of the image data on the source is 7 bytes. In this case, M
The PU adds 1-byte NULL data to the end of the 7-byte data on the source and transfers it to the destination.

FIG. 8C illustrates the case where the MPU transfers data having a horizontal size of 3 bytes, which is one data unit, onto the destination. Hereinafter, the description in this case will be described with reference to the explanatory diagram of the boundary length conversion processing procedure in FIG.

First Read Process FIG. 9A shows the first read process. The first time,
MPU is 4 bytes of data "1, 2,
"3, 1" is read. Next, the MPU completes one data unit from the read data, so 1-byte NU
Create 4-byte data with LL data added, and write it to the destination.

Data "1" which is read but not written by this 1-byte addition process
Occurs for 1 byte. This data is used as reserved data, and processing is performed as the leading data of the 4-byte data to be read next.

The table for storing this reserved data is 4
It has a byte structure, and the reserved data is stored in the higher order, and NULL data is stored in the remaining area. Second Read Process FIG. 9B shows the second read process. MPU is
From the address on the source accessed the first time, the 4-byte data “2, 3,
1, 2 ”is read and write data is created using the pending data“ 1 ”.

In this case, since the 1 byte unit is completed by the read data, the MPU is 1 byte NULL.
Create write data with data added and write to the destination. The pending data at this time is "1,
2 ”.

Third Read Processing FIG. 9C shows the third read processing. MPU is
From the address on the source accessed the second time, the 4-byte data “3, 1,
"2, 3" is read and write data is created using the pending data "1, 2".

In this case, since the read data completes a 1-byte unit, the MPU is a 1-byte NUL.
Write data to which L data is added is created and written to the destination. The pending data at this time is "1,
2, 3 ".

Writing Pending Data to Destination FIG. 9D shows a process of writing pending data to the destination. When the MPU performs the third read process, the updated pending data is written to the destination because one data unit is completed.

In this case, since all the read data have been written, the pending data is cleared to 0. After that, the above process is repeated until all designated bytes are processed. FIG. 10 is an explanatory diagram of writing pending data. As shown in FIG. 9D, the phenomenon that one data unit is completed by writing the pending data as it is without reading the source always occurs when the number of bytes of the data unit requires additional processing. There is regularity in this.

This regularity means that when the MPU accesses the source in units of 4 bytes several times in units of 1 data unit, the pending data is written as it is, so that one data unit is completed. In the case of FIG. 9, the number of bytes in one data unit is 3 bytes, so when the source memory is accessed three times, the state shown in FIG. 9D is obtained.

FIG. 10A is an explanation when one data unit is 5 bytes. In FIG. 10A, the MPU is
At the first memory access on the source, 4-byte data “1, 2, 3, 4” is read and written to the destination as it is. There is no pending data at this time.

The MPU reads the data "5, 1, 2, 3" in the second memory access and writes the added data "5, 0, 1, 2" in the destination. The hold data at this time is "3". In addition,
“0” indicates additional data.

The MPU reads the data "4, 5, 1, 2" at the third memory access and writes the added data "3, 4, 5, 0" in the destination. The hold data at this time is "1, 2".

The MPU reads the data "3, 4, 5, 1" at the fourth memory access and writes the data "1, 2, 3, 4" in the destination. The hold data at this time is "5, 1".

The MPU reads the data "2, 3, 4, 5" at the fifth memory access and writes the added data "5, 0, 1, 2" in the destination. Since the hold data at this time is "3, 4, 5", one data unit is completed with this hold data.

As described above, in the case of 5-byte data, one data unit is completed by writing the contents of the pending data to the destination when the source memory access is performed five times.

FIG. 10B is an explanatory diagram when one data unit is 7 bytes. In the case of 7-byte data in FIG. 10B, one data unit is completed by writing the contents of the pending data to the destination when the MPU performs the source memory access seven times.

(3) Boundary length conversion processing procedure in which 8-bit boundary data is converted to 32-bit boundary data by an MPU having a 32-bit bus width The correspondence to the destination 32-bit (4 byte) boundary will be described. When the destination boundary length described with reference to FIGS. 4 to 10 is expanded from the 2-byte boundary length to the 4-byte boundary,
The timing of writing the stored bytes of pending data changes. The procedure will be described below.

The number of bytes in one data unit is divided into four groups based on the value of the remainder when divided by 4. Group A has a remainder of 3 ... 7, 11, 15, 19 etc. Group B has a remainder of 2 ... 6, 10, 14, 18 etc. Group C has a remainder of 1 ... 5, 9, 13, 17 etc. D group remainder 0 ... 4,8,12,16 etc. The storage byte of reserved data is written in the following timing for each group.

Group A In this case, the pending data is written to the destination at the same timing as the procedure when the destination is the 16-bit boundary described with reference to FIGS. 9 to 10.

Group B: In this case, the number of bytes in one data unit divided by 2,
Write the pending data to the destination when the source memory is accessed.

D group In this case, the additional processing of the boundary length conversion is unnecessary,
Since the MPU writes the data accessed from the source to the destination as it is, there is no pending data.

C group In this case, assuming that the number of bytes in one data unit is X, X
When the source is accessed twice, the timing of writing the storage byte of the pending data occurs. However, the difference from when the destination is 16-bit boundary is that the source is not accessed twice until then,
It is possible to complete one data unit by processing the stored bytes of the reserved data.

FIG. 11 is an explanatory diagram when one data unit is 9-byte data. In FIG. 11, data in which one data unit is 9 bytes is processed in a 32-bit boundary. When the MPU accesses the source five times with respect to the source (fifth memory access), one data unit is completed by the storage byte of the reserved data (reserved byte).

Then, when the MPU accesses the source twice to the source (seventh memory access),
One data unit is completed by the reserved byte. Furthermore, 2
When the memory is accessed for the ninth time (the ninth memory access), one data unit is completed by the reserved byte, the reserved byte disappears, and the initial state is set.

With the above regularity, the real byte X = 4n + 1 (n
= 1, 2, 3, ...) It becomes as follows. When the memory is accessed n + 1 times, 3 bytes of reserved bytes are generated.

When the memory is accessed 2n + 1 times,
One data unit is completed by the reserved byte, and the reserved byte becomes 2 bytes. When the memory is accessed 3n + 1 times, one data unit is completed by the reserved byte, and the reserved byte becomes 1 byte.

When the memory is accessed 4n + 1 times,
One data unit is completed by the reserved byte, the reserved byte becomes 0 byte, and the state returns to the initial state. Will be repeated.

(4) Description of Case where Number of Data Bytes After Boundary Length Conversion Processing Decreases FIG. 12 is an explanatory diagram when 16-bit boundary length data in which one line is 3 bytes. In FIG. 12, the data in the external memory serving as the source (SRC) is converted into the data in the external memory serving as the destination (DST).
This is a process in which U is converted.

In this case, the source is 16-bit boundary length, data of 1-line length which is 1 data unit is 3 bytes, and 1-byte blank (NULL) data is added. The MPU has a 32-bit bus for external memory. This MPU has an internal memory of 32 bits or more, and stores the remaining data that cannot be written.

The destination stores the data converted to the 8-bit boundary length by the MPU. The MPU first reads the 4-byte data “1, 2, 3, 0” on the source. At this time, all the read data "1, 2, 3" is the remaining data (pending data)
Becomes

The MPU reads the next 4-byte data “1, 2, 3, 0” for the second time and writes the write data “1,
Create 2, 3, 1 ”and write it to the destination. At this time, the remaining data is "2, 3".

In this case, by the time one line is completed, the number of times the MPU accesses the external memory is 2 for reading and 1 for writing, which is a total of 3 times. Further, since the number of data bytes after the boundary length conversion processing is reduced, there is an advantage that the external memory area occupied by this processing becomes small.

FIG. 13 is an explanatory diagram for converting 16-bit boundary data into 8-bit boundary data. In this case, the MPU has a 32-bit bus width and 1
1 line of source image data, which is a data unit, is X
If it is a byte, it is classified as shown in FIG. 13 and boundary processing is performed.

When X = 4n, no reserved byte is generated, and the MPU writes the read 4-byte data as it is to the destination. : When X = 4n + 1, 3 bytes of reserved bytes are generated when the MPU reads the n + 1th 4-byte data. All the data read at this time becomes a reserved byte, and writing to the destination is not performed.

Due to the processing at the time of reading the 2n + 1th time of the MPU, the reserved byte becomes 2 bytes. Next, the reserved byte becomes 1 byte by the processing at the time of reading the 3n + 2nd time of the MPU. Further, the pending byte becomes 0 and is cleared by the processing at the time of reading the 4n + 2nd time of the MPU.

When X = 4n + 2, no reserved byte is generated and the MPU writes the read 4-byte data as it is. : When X = 4n + 3, 3 bytes of reserved bytes are generated when the MPU reads n + 1th time. All the data read at this time becomes a pending byte, and writing to the destination is not performed.

The number of reserved bytes becomes 2 due to the processing at the time of reading the 2n + 2nd time of the MPU. Next, MPU 3
The number of reserved bytes becomes 1 due to the processing at the time of reading n + 3 times. Further, the pending byte becomes 0 and is cleared by the processing at the time of reading the 4n + 4th time of the MPU.

As described above, by classifying the source data as much as the number of bytes of the bus width of the MPU, the processing can be dedicated and the boundary length conversion processing for one line can be speeded up.

FIG. 14 is an explanatory diagram in the case of converting 32-bit boundary data into 8-bit boundary data. In this case, the MPU has a 32-bit bus width and 1
1 line of source image data, which is a data unit, is X
If it is a byte, it is classified as shown in FIG. 14 and boundary processing is performed.

When X = 4n, no reserved byte is generated and the MPU writes the read 4-byte data as it is to the destination. : When X = 4n + 1, a 1-byte reserved byte is generated when the MPU reads n + 1-th 4-byte data. All the data read at this time becomes a reserved byte, and writing to the destination is not performed.

When the MPU reads 2n + 2nd time, the number of reserved bytes becomes 2 bytes. At this time, all the data read is a reserved byte and writing to the destination is not performed.

Next, at the time of reading the 3n + 3rd time of the MPU, the number of reserved bytes becomes 3 bytes. All the data read at this time becomes a pending byte, and writing to the destination is not performed.

Further, the pending byte becomes 0 and is cleared by the processing at the time of reading the 4n + 4th time of the MPU. : When X = 4n + 2, 2 bytes of reserved bytes are generated when the MPU reads the n + 1th 4-byte data. All the data read at this time becomes a pending byte, and writing to the destination is not performed.

The reserved byte becomes 0 and is cleared by the processing at the time of reading the 2n + 2nd time of the MPU. : When X = 4n + 3, 3 bytes of reserved bytes are generated when the MPU reads n + 1th 4-byte data. All the data read at this time becomes a pending byte, and writing to the destination is not performed.

Due to the processing at the time of reading the 2n + 2nd time of the MPU, the number of reserved bytes becomes 2 bytes. Next, due to the processing at the time of reading the 3n + 3rd time of the MPU, the reserved byte becomes 1 byte. Further, the pending byte becomes 0 and is cleared by the processing at the time of reading the 4n + 4th time of the MPU.

As described above, by classifying the source data in the same number as the number of bytes of the bus width of the MPU, the processing can be dedicated and the boundary length conversion processing of one line can be performed at high speed.

(5) Description of Copying Source Data to Internal Memory of MPU for Processing FIG. 15 is an explanatory diagram of converting 8-bit boundary length data in which one line is 3 bytes into 16-bit boundary length data. Is. In the figure, a source (SRC) and a destination (DST) each represent a data structure in the external memory.

In FIG. 15, the source has an 8-bit boundary length, and one line, which is one data unit, is 3 bytes of data. The MPU has a 32-bit bus for an external memory, and this MPU has a high-speed accessible internal memory having a sufficiently large capacity.

The processing will be described below with reference to the processing of FIG. The MPU once copies (temporarily saves) the source data to an internal memory that can be accessed at high speed.

The MPU has 3 units for this internal memory.
When 2-bit access is performed and the last byte of one line is read, the byte after that is rewritten to the NULL byte to convert it to 16-bit boundary length data and write it to the destination (first write).

In the next process, the MPU returns the access pointer to the internal memory by 1 byte,
Read the data rewritten to NULL again. It should be noted that if the access pointer is shifted by 1 byte and the reading (reading) spans the 32-bit layer of the internal memory, the editing process is required
When programming in a high-level language such as C,
The compiler does not need to be aware of this because the compiler automatically performs edit processing at the assembler level.

Similarly to the above, the MPU rewrites the byte after the last byte of one line into a NULL byte and writes it to the destination (second write). FIG. 16 is an explanatory diagram of converting 16-bit boundary length data in which one line is 3 bytes into 8-bit boundary length data. In the figure, a source (SRC) and a destination (DST) each represent a data structure in the external memory.

In FIG. 16, the source is data having a 16-bit boundary length and one line length of 3 bytes. MP
U has a 32-bit bus for external memory,
This MPU has a high-speed accessible internal memory having a sufficiently large capacity. Hereinafter, description will be given in accordance with the processing of FIG.

The MPU once copies (temporarily saves) the source data to the internal memory that can be accessed at high speed. When the MPU makes 32-bit access to this internal memory and reads the last byte of one line,
The 32-bit data next to the 32-bit data just read is also read. Then, the MPU crushes the NULL data next to the last byte of the first one line to obtain 8
Convert to bit boundary length data and write to the destination (first write).

Further, in the next processing, the MPU advances the access pointer to the internal memory and returns NULL.
Read from the data next to the data replaced with. When the access pointer is shifted by 1 byte, the assembler level editing process is performed in the case of reading across the 32-bit layer of the internal memory, as in the description of FIG.

Similarly to the above, the MPU crushes the NULL data to convert it into 8-bit boundary length data, and writes it to the destination (second write).

As described above, since the source data is once copied to the internal memory of the MPU and processed, the number of accesses to the external memory can be minimized. §3 Description of Closed Polygonal Surface Painting FIGS. 17 to 24 are explanatory views of closed polygonal surface coating.

(1) Raster Expansion and Clip Processing FIG. 17 is a flowchart of raster expansion and clip processing. Hereinafter, description will be given according to the process numbers S11 to S18 in the figure.

S11: The vertex coordinates of the triangle are received from the host device such as the host 1 in the command format (1) (see FIG. 18A) and stored in the memory unit 6 which is an internal storage area. Move.

S12: The clip coordinates are received from the host device such as the host 1 in the command format (2) (see FIG. 18B) and stored in the memory section 6 which is an internal storage area.
Move to processing of 13.

S13: The data processing unit 3 considers relative coordinates in order to create outline data from the vertex coordinates received in the processing number S11, and finds the origin and relative coordinates (see FIG. 19). Further, a value obtained by converting the obtained origin coordinates into the bitmap coordinate system is also obtained for transfer to the bit map memory (BMM) 66, and the process proceeds to S14.

S14: The data processing unit 3 converts the relative coordinates of the vertex coordinates into the outline data format for the raster expansion hardware unit 42. In addition, the data processing unit obtains the frame width and frame height of the polygon from the origin and vertex coordinates that have been converted into relative coordinates, and further obtains the area where the raster rasterization unit is actually performed from the received clip coordinates. The area in charge of the raster expansion hardware unit 42 is determined (see FIG. 20), and S15
Move on to processing.

S15: The data processing unit 3 determines whether or not there is a raster raster remaining. If there is a remainder in this determination (YES), the process proceeds to S16. If there is no remainder (NO), this process ends.

S16: The data processing section 3 determines whether raster expansion is necessary. If raster expansion is required in this determination (YES), the process proceeds to S17. If raster expansion is not required (NO), the process returns to S15.

S17: The data processing section 3 sets the start-up parameters for the area in charge of the raster expansion hardware section 42 (see FIG. 20), and proceeds to the processing of S18. The parameters include the outline data storage area address of the outline data storage unit 64, the development start coordinate position, the effective width, the effective height, the polygon frame width, the polygon frame height, and the like.

S18: The data processing section 3 activates the raster expansion hardware section 42 to expand the raster data from the outline data into the raster data in which the outline (contour) is filled, and to the processing of S15. Return.

(2) Explanation of Command Format FIG. 18A is an explanatory diagram of the command format (1).
This command format (1) is a closed polygon surface painting command ID
(Identifier), overall data length, and coordinates 1 to 3 which are the vertex coordinates on the triangular bitmap memory 66.

FIG. 18B is an explanatory diagram of the command format (2). This command format (2) is composed of a fill clip command ID, the entire data length, the upper left coordinate of the clip frame on the bitmap memory 66, and the lower right coordinate of the clip frame.

(3) Description of Interrupt Process FIG. 18C is an explanatory diagram of the interrupt process. FIG. 17
In the process (1), when assigned areas are assigned to a plurality of raster expansion hardware units 42, the completion is notified to the MPU 33 as soon as the processing of one raster expansion hardware unit 42 is completed. When the data transfer is required by this notification, the transfer hardware unit 41 is activated, so that the FIFO transfer hardware unit 41 is requested to perform processing (S21).

The FIFO type transfer hardware unit 41 transfers the data from the raster expansion hardware work memory unit 65 to the assigned area on the bit map memory 66 for surface painting.

Similarly, when the processing of the next raster expansion hardware unit 42 is completed, the MPU 33 also receives an end interrupt, and when data transfer is required, the FIFO type transfer hardware unit 41 is used.
Request processing (S22).

(4) Description of coordinate conversion The data processing unit 3 considers relative coordinates to create outline data from the vertex coordinates of the bitmap memory (BMM) coordinate system received from the higher-level device, and considers their origin and relative coordinates. Ask for.

FIG. 19 is an explanatory diagram of coordinate conversion. FIG.
9, the data processing unit 3 causes the vertex coordinates (x1, y1), (x2, y2), (x3, y) of the triangle of the BMM coordinate system.
3) Receive. The data processing unit 3 converts the vertex coordinates into relative coordinates for the outline data (X1 = x1−
x2, Y1 = 0) (X2 = 0, Y2 = y2-y1) (X
3 = x3-x2, Y3 = y3-y1). The origin (0, 0) of this relative coordinate is (x3, y1) in the BMM coordinate system.

(5) Description of the area in charge of the plural raster rasterization hardware section From the relative coordinateized origin and vertex coordinates, the polygonal frame width,
An area to be actually raster-expanded is obtained from the frame height and the clip coordinates, areas in charge of the plurality of raster-expansion hardware sections 42 are determined, and start-up parameters of the raster-expansion hardware section 42 are determined.

FIG. 20 is an explanatory diagram of the area in charge of the multiple raster expansion hardware section. In FIG. 20, a region (clip frame that is four shaded portions) where raster rasterization is actually performed is obtained from the clip coordinates, and the four raster rasterization hard sections 42 are obtained.
Assigned areas (shaded areas) are assigned to -1 to 42-4. Also, the raster transfer start coordinate position *, the effective width, the effective height, the polygon frame width, and the polygon frame height, which are the startup parameters of the respective raster expansion hardware parts, are shown.

(6) Description of Operations of Plural Raster Expansion Hardware Sections FIG. 21 is an explanatory diagram of operations of a plurality of raster expansion hardware sections. In FIG. 21, the outline data storage unit 64
Is outline data of relative coordinates (X1,
Y1), (X2, Y2), (X3, Y3) are stored, and the data format passed by the data processing unit 3 to the raster expansion hardware unit is the total length a of the data and the bending point from the start point to the end point. Group length b, start point coordinate, second point coordinate, third point
It becomes point coordinates.

As shown in FIG. 20, the data processing section 3 determines the area for actually rasterizing the outline data in the outline data storage section 64, and assigns the areas in charge of the raster expanding hardware sections 42-1 to 42-4. Decide

Each raster expansion hardware section 42-1 to 42-4
Then, the rasterizing of the outline data to the raster data with which the inside of the outline is filled is performed in the work memory areas of the raster developing hardware work memories 65-1 to 65-4, respectively, according to the start parameters of the areas in charge.

These raster expansion hardware units 42-1 to 42-4
As soon as the expansion processing of 2-4 is completed, using the FIFO-type transfer hardware section 41, the respective raster expansion hardware section work memories 65-1 to 65-4 to the respective areas in charge on the BMM 66 (explained in FIG. 19). Consider the origin coordinates of the BMM coordinate system and the parameters described in FIG. 20),
Complete the polygon.

The four shaded polygonal patterns shown by the BMM 66 in FIG. 20 are provided for convenience of explanation, and are actually the same, for example, solid black. Also,
In the above description, a plurality (4) of raster expansion hardware units 42
However, if only one part of the polygon can be processed at a time, it can be divided into a plurality of times.

Furthermore, the memory unit 6 for storing the vertex coordinates of the closed polygon specified by the user and the clip area designated by the user is provided, and the vertex processing of the closed polygon is converted by the data processing unit 3 to create it. Using the outline data of the outline data storage unit 64 and the outline filling unit of the raster expansion hardware unit 42 and the transfer hardware unit 41,
By expanding and transferring only the clip area specified by the user, it is possible to improve the performance of the surface painting of the clipped closed polygon.

Further, by providing the raster expansion hardware section 42 which can expand the outline data into raster data and judge the expansion result is only blank, the expansion result of the area divided into a plurality of areas is not blank only the fill-in area. The transfer hardware unit 41 transfers the data between the memories to improve the performance of the closed polygonal surface painting with many blank portions.

(7) Description of the case where there are many expanded areas When there are many expanded areas, raster expansion of a closed polygon is realized as follows. As shown in FIGS. 18A and 18B, the vertex coordinates and clip coordinates of the triangle are received from the host in the command format (1) and the command format (2), respectively, and stored in the memory unit 6 which is an internal storage area.

In order to create outline data from the received vertex coordinates in the data processing unit 3, FIG.
Considering relative coordinates such as 9, the relative coordinates are obtained with the origin.
Also, a value obtained by converting the origin coordinates into the BMM coordinate system is obtained for the BMM transfer.

The relative coordinate-converted vertex coordinates are converted into the outline data format for the raster expansion hardware unit 42. The frame width and frame height of the polygon are calculated from the relative coordinates of the origin and the vertex coordinates.

The polygon with relative coordinates is divided into areas in which one raster expansion hardware expands at a time (FIG. 22).
reference). Assuming a reduced coordinate system in which each divided area is one dot, the coordinates of each vertex in the reduced coordinate system obtained by thickening a reduced figure to be described later are obtained.

The vertex coordinates in the reduced coordinate system are converted into the outline data format for the raster expansion hardware unit 42. In consideration of the above data and the received clip area, the start parameters of the raster expansion hardware unit 42 are determined, the outline (contour) is filled, and the raster data is expanded in the raster expansion hardware unit work memory 65.

In the above, the expansion hardware unit work memory 6
Only when the dots corresponding to the respective areas divided from the reduced figure expanded to 5 are black (1 is higher), the area is expanded by the raster expansion hardware unit 42.

By performing the processing as described above, the raster expansion number of the blank portion can be reduced and the performance can be improved. FIG. 22 is an explanatory diagram when there are many expansion areas.
In FIG. 22, a mesh obtained by dividing a polygon having relative coordinates into areas in which one raster expansion hardware unit 42 expands at once is shown. This mesh has L height,
The width is divided into K pieces.

As a result, the raster expansion hardware unit 42 sets 1
Assuming that the area developed every time is N × M dots, the total height is M × L dots and the width is N × K dots.

When a reduced coordinate system with this N × M dot mesh as one dot is created, a reduced coordinate system graphic of L dots in height and K dots in width is formed as shown in the lower right part of FIG. a. How to Obtain Vertex Coordinates in Reduced Coordinate System The area developed by the raster development hardware unit 42 at a time is N × M
Dot, n vertices of user-specified closed polygon
1, Y1) ... Pn (Xn, Yn), the corresponding point Pn ′ (Xn ′, Yn of the vertex Pn in the reduced coordinate system)
′) Is calculated by the following formula.

Xn '= Xn / N Yn' = Yn / M (n = 1, 2, 3 ...) However, if raster expansion is performed using the reduced coordinates obtained by the above equation, raster expansion is originally performed when diagonal lines are drawn. The bit corresponding to the required area may not be black (1).

FIG. 23 is an explanatory diagram of the vertex coordinates of the reduced coordinate system, and FIG. 23 (a) is an explanatory diagram of diagonal lines of the reduced coordinate. In FIG. 23A, when the raster expansion hardware unit 42 draws between the two vertices P1 ′ and P2 ′, the portion surrounded by the diagonal squares is not black, and some portions are not developed.

In order to prevent this, it is necessary to thicken the reduced figure. Therefore, each vertex of the obtained reduced figure is converted into a few vertices. FIG. 23B is an explanation of conversion into three vertices. When the vertices of the reduced figure are on the vertices of the reduction frame, the vertices Pn ′ are converted into the vertices Pn ′ and two extended vertices, that is, a total of three vertices.

FIG. 23C is an explanation of conversion into two vertices. If the vertices of the reduced figure are on the sides of the reduction frame, the vertices Pn ′ are converted into two extended vertices. FIG. 24 is an explanatory diagram of the extended closed polygon. In FIG. 24, P1 ′ to P3
′ Is a vertex in the reduced coordinate system, and P11 to P17 are vertices of the expanded closed polygon.

Closed triangle of reduced figure P1'-P2'-P3
'Is expanded (thickened) to form a closed polygon P1 that is a simulated polygon
1-P12-P13-P14-P15-P16-P17
As described above, the outline data of the expanded closed heptagon is created and expanded by the raster expansion hardware unit 42 (surface painting with black dots).

A mesh (N × M dots) corresponding to the black portion of the reduced figure is formed by using the face-reduced reduced figure.
The raster expansion hardware unit 42 expands only the part of. In this way, the raster expansion of the blank part can be reduced, and this blank part does not need to be transferred by the transfer hardware unit 41. Therefore, there are many blank parts and a large expansion area (at least 16 areas or more) of a closed polygon Surface painting can be performed at high speed.

[0142]

As described above, the present invention has the following effects. (1) In the work of converting the boundary length of data, it is possible to minimize the number of accesses to a low-speed external memory and reduce the processing time.

(2) The destination data editing process can be specialized by classifying the source data by the same number as the number of bytes of the bus width of the MPU, so that the boundary length conversion process for one line can be performed at high speed. .

(3) The processing speed can be improved by the MPU once copying and editing the source data in the internal memory. (4) The drawing performance of closed polygonal surface painting can be improved by using the raster expansion hardware part of the outline data and the transfer hardware part of the memory.

(5) Since the raster data expanded by using the division mode of the raster expansion hardware part is pasted by the transfer hardware part, the drawing process can be performed regardless of the size of the closed polygon. Performance can be improved.

(6) Using the split mode of the raster expansion hardware part, the expanded raster data is transferred only by the clip part of the part divided by the transfer hardware part, thereby performing the clip processing of closed polygonal surface painting. Therefore, the processing performance can be improved.

(7) By using a plurality of raster expansion hardware units and memory transfer hardware units, it is possible to increase the parallel operation time between the software side and the hardware side and improve the processing performance.

(8) Multiple raster expansion hardware units and FIF
By using the O-type transfer hardware unit, the waiting time for the transfer hardware unit of the raster expansion hardware unit can be reduced and the performance can be improved.

(9) By using the blank write flag of the raster expansion hardware section to stop the unnecessary transfer of the blank section by the transfer hardware section and transfer only the area with the face-painted part, a closed polygon with many blank sections The performance of surface coating can be improved.

(10) By creating and referring to the reduced figure, it is possible to reduce the number of raster expansions in the blank portion and improve the performance.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of a printing apparatus according to an embodiment.

FIG. 3 is an explanatory diagram of an imaging hardware unit (IHW) in the embodiment.

FIG. 4 is an explanatory diagram of an outline of boundary length conversion processing in the embodiment.

FIG. 5 is an explanatory diagram of transfer when one data unit length is 6 bytes in the embodiment.

FIG. 6 is an explanatory diagram of transfer when one data unit length is 3 bytes in the embodiment.

FIG. 7 is a processing flowchart when adding additional data in the embodiment.

FIG. 8 is an explanatory diagram of boundary length conversion in the embodiment.

FIG. 9 is an explanatory diagram of a boundary length conversion processing procedure according to the embodiment.

FIG. 10 is an explanatory diagram of writing pending data in the embodiment.

FIG. 11 is an explanatory diagram of a case of 9-byte data according to the embodiment.

FIG. 12 is an explanatory diagram of 16-bit boundary length data in which one line is 3 bytes in the embodiment.

FIG. 13 is an explanatory diagram for converting 16-bit boundary data into 8-bit boundary data in the embodiment.

FIG. 14 is an explanatory diagram for converting 32-bit boundary data into 8-bit boundary data in the embodiment.

FIG. 15 is an explanatory diagram of converting 8-bit boundary length data in which one line is 3 bytes into 16-bit boundary length data in the embodiment.

FIG. 16 is an explanatory diagram for converting 16-bit boundary length data in which one line is 3 bytes into 8-bit boundary length data in the embodiment.

FIG. 17 is a flowchart of raster expansion and clip processing in the embodiment.

FIG. 18 is an explanatory diagram of a command format and interrupt processing according to the embodiment.

FIG. 19 is an explanatory diagram of coordinate conversion according to the embodiment.

FIG. 20 is an explanatory diagram of a region in charge of a multiple raster expansion hardware unit according to the embodiment.

FIG. 21 is an operation explanatory diagram of a plurality of raster expansion hardware units in the embodiment.

FIG. 22 is an explanatory diagram of a case where there are many expansion areas in the embodiment.

FIG. 23 is an explanatory diagram of vertex coordinates of the reduced coordinate system according to the embodiment.

FIG. 24 is an explanatory diagram of an expanded closed polygon according to the embodiment.

FIG. 25 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 3 Data Processing Section 4 Imaging Hardware Section (IHW) 31 Program Area 32 Internal Memory 33 MPU 61 External Memory (Source Data) 62 External Memory (Destination Data)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G09G 5/36 K 9377-5H X 9377-5H

Claims (12)

[Claims] 1. An external memory storing 1-byte boundary source data, an external memory storing 2 ^m (m is an integer of 0 or more) byte boundary data, and 2 ⁿ (n is an integer of 0 or more). ); and a MPU with byte bus, MPU is in the process of editing the data for boundary length converting the source data to the destination data, and hold to the source data read from accumulating 2 ⁿ bytes, 2 ⁿ An image forming apparatus characterized by writing data to a destination of an external memory in byte units. 2. The image forming apparatus according to claim 1, wherein the data editing process is performed by classifying the source data by the same number as the bus width byte number of the MPU. 3. An external memory for storing source data of 2 ^m (m is an integer of 0 or more) byte boundary, an external memory for storing destination data of 1 byte boundary, and 2 ⁿ (n is an integer of 0 or more). ); and a MPU with byte bus, MPU is in the process of editing the data for boundary length converting the source data to the destination data, and hold to the source data read from accumulating 2 ⁿ bytes, 2 ⁿ An image forming apparatus that writes data to a destination of an external memory in byte units. 4. The image forming apparatus according to claim 3, wherein the data editing process is performed by classifying the source data by the same number as the bus width byte number of the MPU. 5. An external memory for storing 1-byte boundary source data, an external memory for storing 2 ^m (m is an integer of 0 or more) byte boundary data, and 2 ⁿ (n is an integer of 0 or more). ) MPU with byte bus width
In the process of editing the data in order to convert the source data to the boundary data in the boundary length, the MPU temporarily copies the source data to a memory that can be accessed at high speed and edits the data on this memory. Characterized image forming device. 6. An external memory for storing 2 ^m (m is an integer of 0 or more) byte boundary source data, an external memory for storing 1 byte boundary of destination data, and 2 ⁿ (n is an integer of 0 or more). ) MPU with byte bus width
In the process of editing the data in order to convert the source data to the boundary data in the boundary length, the MPU temporarily copies the source data to a memory that can be accessed at high speed and edits the data on this memory. Characterized image forming device. 7. A storage unit for storing the vertex coordinates of a closed polygon specified by the user, a data processing unit for converting the vertex coordinates of the closed polygon into outline data, and a raster expansion having a function of filling the inside of the outline. An image forming apparatus comprising: a hardware unit, wherein a raster expansion hardware unit performs surface painting of a closed polygon from the outline data. 8. A storage unit for storing the vertex coordinates of a closed polygon specified by the user, a data processing unit for converting the vertex coordinates of the closed polygon into outline data, and a raster expansion having a function of filling the inside of the outline. An image forming apparatus characterized by performing surface coating of a closed polygon using a raster expansion hardware unit that includes a hardware unit and can process only a part of the requested closed polygon. 9. A storage unit for storing the vertex coordinates of the closed polygon specified by the user, a storage unit for storing the clip area specified by the user, and a data processing for converting the vertex coordinates of the closed polygon into outline data. Section, a raster expansion hardware section that has the function of filling the inside of the outline, and a transfer hardware section that transfers between memories. Only the clip area specified by the user is expanded by the raster expansion hardware section and transferred by the transfer hardware section. An image forming apparatus characterized by performing closed polygonal surface coating. 10. A storage unit for storing the vertex coordinates of a closed polygon specified by the user, a data processing unit for converting the vertex coordinates of the closed polygon into outline data, and a plurality of units having a function of filling the inside of the outline. It has a raster expansion hardware part and a memory transfer hardware part that stores command data in a FIFO format and executes sequentially. A plurality of raster expansion hardware parts expands a plurality of surface painting preparation parts to form a FIFO format transfer hardware part. An image forming apparatus characterized by requesting a transfer. 11. A storage unit for storing the vertex coordinates of a closed polygon specified by a user, a data processing unit for converting the vertex coordinates of the closed polygon into outline data, and a function for filling the inside of the outline and a result of expansion. Equipped with a raster expansion hardware part that can determine only blanks and a transfer hardware part that transfers between memories, the raster expansion hardware part fills a closed polygon, and transfers only the fill part where the expansion result is not blank. An image forming apparatus characterized in that transfer processing is performed by a hardware unit. 12. A data processing unit for converting the vertex coordinates of a closed polygon specified by a user into outline data, and a plurality of raster expansion hardware units having a function of filling the inside of the outline, wherein the data processing unit is a closed A polygon is divided into meshes of a size that can be expanded by one raster expansion hardware part, and the mesh containing the vertices of a closed polygon is treated as one dot, and a simulated polygon surface is painted. An image forming apparatus characterized by the above.