JPH065993A - Multilayer board with internal layer circuits exposed - Google Patents
Multilayer board with internal layer circuits exposedInfo
- Publication number
- JPH065993A JPH065993A JP4183055A JP18305592A JPH065993A JP H065993 A JPH065993 A JP H065993A JP 4183055 A JP4183055 A JP 4183055A JP 18305592 A JP18305592 A JP 18305592A JP H065993 A JPH065993 A JP H065993A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- layer
- spot
- board
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、プリント配線基板、特
にICメモリーモジュール基板やPGA(ピングリット
アレイ)搭載基板の製作に用いられる内層回路露出型基
板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and more particularly to an inner layer circuit exposure type board used for manufacturing an IC memory module board or a PGA (pinglit array) mounting board.
【0002】[0002]
【従来の技術】従来、ICメモリーモジュール基板やP
GA搭載基板は、高密度化の要求からチップ部品の搭載
数を多くすることが行われているが、搭載回路面積には
限度があるので、さほど高密度化できない。2. Description of the Related Art Conventionally, IC memory module substrates and P
The GA mounting board has been increased in the number of mounted chip components due to the demand for higher density, but the mounted circuit area has a limit, and therefore the density cannot be increased so much.
【0003】このようなことから、近時、多層基板例え
ば図2に示すように4層基板1の上面から座ぐり穴2を
形成して、3層目の回路パターン3の一部を露出させ
て、チップ部品搭載回路面積を増大させた内層回路露出
型基板4がICメモリーモジュール基板やPAG搭載基
板の製作に用いられるようになってきた。Under these circumstances, recently, a counterbored hole 2 is formed from the upper surface of a multi-layer substrate, for example, a four-layer substrate 1 as shown in FIG. 2 to expose a part of the circuit pattern 3 of the third layer. Thus, the inner layer circuit exposed type substrate 4 having an increased chip component mounting circuit area has come to be used for manufacturing an IC memory module substrate or a PAG mounting substrate.
【0004】ところで、この内層回路露出型基板4は、
座ぐり穴2内へのチップ部品の実装時、座ぐり穴2内が
溶剤や水による洗浄、フラックス処理等の液処理が行わ
れる為、図2に示されるように座ぐり穴2内に溜まった
液Wは逃げ場がなく、残留し易い。液が残留したまま座
ぐり穴2内にチップ部品を搭載し、内層回路と導通させ
ると、短絡する恐れがあるので、絶対避けねばならな
い。更にチップ部品の搭載数が多くなるに従いこれらか
ら発生する熱及び他の搭載部品の発熱によるモジュー
ル、PGA自体の温度上昇の影響をできるだけ回避する
ことが望まれていた。By the way, the exposed inner layer circuit type substrate 4 is
When the chip parts are mounted in the counterbore 2, the inside of the counterbore 2 is cleaned with a solvent or water, and liquid treatment such as flux treatment is performed. Therefore, as shown in FIG. The liquid W has no escape and easily remains. If a chip component is mounted in the counterbore 2 while the liquid remains and it is electrically connected to the inner layer circuit, a short circuit may occur, which must be absolutely avoided. Further, as the number of chip components mounted increases, it has been desired to avoid as much as possible the influence of temperature rise of the module and PGA itself due to heat generated from these and heat generation of other mounted components.
【0005】[0005]
【発明が解決しようとする課題】そこで本発明は、内層
回路パターンの一部を露出した座ぐり穴内を、チップ部
品の実装時溶剤や水による洗浄,フラックス処理等の液
処理した際、液が残留せず、更に回路の通電時には熱発
散を容易にした内層回路露出型基板を提供しようとする
ものである。Therefore, according to the present invention, when the inside of the counterbore hole exposing a part of the inner layer circuit pattern is subjected to liquid treatment such as cleaning with a solvent or water at the time of mounting chip parts, flux treatment, etc. It is an object of the present invention to provide an inner layer circuit exposure type substrate that does not remain and that facilitates heat dissipation when the circuit is energized.
【0006】[0006]
【課題を解決するための手段】上記課題を解決するため
の本発明の内層回路露出型基板は、多層基板の上面から
座ぐり穴を形成して内層回路パターンの一部を露出し、
前記座ぐり穴の底面の一部から内層回路パターンを避け
て多層基板の下面に貫通穴を穿設してなるものである。An inner layer circuit exposure type substrate of the present invention for solving the above problems exposes a part of an inner layer circuit pattern by forming a counterbore hole from the upper surface of a multilayer substrate.
A through hole is formed in a lower surface of the multilayer substrate while avoiding the inner layer circuit pattern from a part of the bottom surface of the counterbore.
【0007】[0007]
【作用】上記のように本発明の内層回路露出型基板は、
座ぐり穴の底に液逃がし穴が貫通されているので、座ぐ
り穴内へチップ部品を実装する際、溶剤や水による洗
浄,フラックス処理等の液処理を行っても、液が座ぐり
穴内に残留せず、穴から外部へ排出される。従って、座
ぐり穴内へチップ部品を搭載し、内層回路と導通させた
際、短絡することがない。更にザグリ穴内チップ部品よ
り発生する熱及び他の搭載部品の発熱によるモジュー
ル、PGA自体の温度上昇を貫通の通気性によって抑制
することが可能となる。As described above, the inner layer circuit exposed type substrate of the present invention is
Since the liquid escape hole is pierced at the bottom of the counterbore hole, when mounting the chip component in the counterbore hole, the liquid will not get into the counterbore hole even if cleaning with solvent or water or liquid treatment such as flux treatment is performed. It does not remain and is discharged from the hole to the outside. Therefore, when the chip component is mounted in the counterbore and is electrically connected to the inner layer circuit, no short circuit occurs. Further, it is possible to suppress the temperature rise of the module and PGA itself due to the heat generated by the chip part in the counterbore hole and the heat generation of other mounted parts by the air permeability of the penetration.
【0008】[0008]
【実施例】本発明の内層回路露出型基板の一実施例を図
1によって説明すると、4層基板1の上面から座ぐり穴
2を形成して、3層目の回路パターン3の一部を露出
し、前記座ぐり穴2の底面中央部から3層目及び4層目
の回路パターン3,3′を避けて4層基板1の下面に貫
通穴5を穿設している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the inner layer circuit exposed type substrate of the present invention will be described with reference to FIG. 1. A counterbore 2 is formed from the upper surface of a four-layer substrate 1 to form a part of a circuit pattern 3 of the third layer. A through hole 5 is formed in the lower surface of the four-layer board 1 so as to avoid the circuit patterns 3 and 3'of the third and fourth layers from the center of the bottom surface of the counterbore 2.
【0009】このように構成された実施例の内層回路露
出型基板4′の座ぐり穴2内にチップ部品を実装する
際、溶剤や水による洗浄,フラックス処理等の液処理を
行っても液が座ぐり穴2内に残留せず、貫通穴5が逃が
し穴となって外部へ排出される。従って、座ぐり穴2内
にチップ部品を収容搭載し、3層目の回路パターン3と
導通した際、短絡することがない。また、貫通穴5は、
搭載チップ部分がデバイスとして使用される際の発熱を
その通気性により容易に発散させることになる。When the chip parts are mounted in the counterbore 2 of the inner layer circuit exposed type substrate 4'of the embodiment thus constructed, even if liquid treatment such as cleaning with a solvent or water and flux treatment is performed, Does not remain in the counterbore hole 2, and the through hole 5 becomes an escape hole and is discharged to the outside. Therefore, when a chip component is housed and mounted in the counterbore 2 and is electrically connected to the circuit pattern 3 of the third layer, there is no short circuit. Also, the through hole 5
The heat generated when the mounted chip portion is used as a device is easily diffused due to its breathability.
【0010】尚、上記実施例の内層回路露出型基板4′
は、4層基板1に適用した場合であるが、これに限るも
のではなく、6層基板,8層基板……等の多層基板に適
用できるものであり、また座ぐり穴2の形成によって一
部露出する回路パターンは3層目に限るものではなく、
任意の層でよい。そして、貫通穴は、座ぐり穴2の中央
部である必要はなく、穿設される貫通穴の個数も可能な
らば複数設けることもできる。Incidentally, the inner layer circuit exposed type substrate 4'of the above embodiment.
Is applied to a four-layer substrate 1, but is not limited to this, and can be applied to a multi-layer substrate such as a six-layer substrate, an eight-layer substrate ... The exposed circuit pattern is not limited to the third layer,
It can be any layer. Further, the through hole does not have to be the central portion of the counterbore hole 2, and the number of through holes to be bored may be plural if possible.
【0011】[0011]
【発明の効果】以上の説明で判るように本発明の内層回
路露出型基板は、内部回路パターンの一部を露出した座
ぐり穴へチップ部品を実装する際、洗浄,フラックス処
理等の液処理を行っても座ぐり穴内に液が残留せず、座
ぐり穴の底に設けた貫通穴から外部へ排出されるので、
チップ部品を搭載し、内層回路と導通した際短絡するこ
とがない。更にザグリ穴内チップ部品より発生する熱及
び他の搭載部品の発熱によるモジュール、PGA自体温
度上昇を、貫通穴の通気性によって抑制することが可能
となる。As can be seen from the above description, the inner layer circuit exposed type substrate of the present invention is a liquid treatment such as cleaning and flux treatment when mounting a chip part in a counterbore hole exposing a part of the inner circuit pattern. The liquid does not remain in the counterbore even after performing the above, and is discharged to the outside from the through hole provided at the bottom of the counterbore.
It does not short-circuit when a chip component is mounted and it is electrically connected to the inner layer circuit. Further, it is possible to suppress the temperature rise of the module and PGA itself due to the heat generated by the chip component in the counterbore and the heat generation of other mounted components by the air permeability of the through hole.
【図1】本発明の内層回路露出型基板の一実施例を示す
図である。FIG. 1 is a diagram showing an embodiment of an inner layer circuit exposure type substrate of the present invention.
【図2】従来の内層回路露出型基板の一例を示す図であ
る。FIG. 2 is a diagram showing an example of a conventional inner layer circuit exposure type substrate.
1 4層基板(多層基板) 2 座ぐり穴 3 3層目の回路パターン(内層回路パターン) 4′内層回路露出型基板 5 貫通穴 1 4 layer board (multilayer board) 2 counterbore hole 3 3rd layer circuit pattern (inner layer circuit pattern) 4'inner layer circuit exposed type board 5 through hole
Claims (1)
内層回路パターンの一部を露出し、前記座ぐり穴の底面
の一部から内層回路パターンを避けて多層基板の下面に
貫通穴を穿設してなる内層回路露出型基板。1. A counterbore hole is formed from the upper surface of a multilayer board to expose a part of an inner layer circuit pattern, and a through hole is formed in a lower surface of the multilayer board while avoiding the inner layer circuit pattern from a part of a bottom surface of the counterbore hole. An inner layer circuit exposure type substrate formed by punching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4183055A JPH065993A (en) | 1992-06-17 | 1992-06-17 | Multilayer board with internal layer circuits exposed |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4183055A JPH065993A (en) | 1992-06-17 | 1992-06-17 | Multilayer board with internal layer circuits exposed |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH065993A true JPH065993A (en) | 1994-01-14 |
Family
ID=16128953
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4183055A Pending JPH065993A (en) | 1992-06-17 | 1992-06-17 | Multilayer board with internal layer circuits exposed |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH065993A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009033185A (en) * | 2008-09-05 | 2009-02-12 | Sanyo Electric Co Ltd | Semiconductor device and its production method |
US7875980B2 (en) | 2004-09-01 | 2011-01-25 | Sanyo Electric Co., Ltd. | Semiconductor device having laminated structure |
EP2077702A3 (en) * | 2008-01-07 | 2011-02-16 | Fujitsu Ltd. | Wiring board and manufacturing method thereof and wiring board assembly |
JP2018195772A (en) * | 2017-05-22 | 2018-12-06 | 日本特殊陶業株式会社 | Manufacturing method for wiring board, and wiring board holding jig |
-
1992
- 1992-06-17 JP JP4183055A patent/JPH065993A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7875980B2 (en) | 2004-09-01 | 2011-01-25 | Sanyo Electric Co., Ltd. | Semiconductor device having laminated structure |
EP2077702A3 (en) * | 2008-01-07 | 2011-02-16 | Fujitsu Ltd. | Wiring board and manufacturing method thereof and wiring board assembly |
JP2009033185A (en) * | 2008-09-05 | 2009-02-12 | Sanyo Electric Co Ltd | Semiconductor device and its production method |
JP2018195772A (en) * | 2017-05-22 | 2018-12-06 | 日本特殊陶業株式会社 | Manufacturing method for wiring board, and wiring board holding jig |
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