JPH10117058A - Method for working printed board - Google Patents

Method for working printed board

Info

Publication number
JPH10117058A
JPH10117058A JP28903096A JP28903096A JPH10117058A JP H10117058 A JPH10117058 A JP H10117058A JP 28903096 A JP28903096 A JP 28903096A JP 28903096 A JP28903096 A JP 28903096A JP H10117058 A JPH10117058 A JP H10117058A
Authority
JP
Japan
Prior art keywords
hole
insulating layer
inner layer
circuit
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28903096A
Other languages
Japanese (ja)
Inventor
Toshihisa Uehara
利久 上原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AIREX KK
Original Assignee
AIREX KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AIREX KK filed Critical AIREX KK
Priority to JP28903096A priority Critical patent/JPH10117058A/en
Publication of JPH10117058A publication Critical patent/JPH10117058A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a work method for securely and electrically connecting an inner layer circuit and an outer layer circuit. SOLUTION: At the time of burning and removing an insulating layer 3 by irradiating it with laser light, the peripheral walls 74 of a via hole (non- through hole) 7A are obliquely formed toward a center by making them face downward. Although the residual material 3B of the insulating layer 3 exists on an upper face 21 of the inner layer circuit 2 at the bottom of the via hole 7A, the resin residual material 3B on the upper face 21 of the inner layer circuit 2 is dissolved and removed, by cleaning the inner part of the via hole 7A solution which dissolves the resin of permanganate solution. Then, the upper face 21 of the inner layer circuit 2 is cleaned, and the via hole 7A is plated 70. Then, an outer circuit 71 is formed on the outer surface of the insulating layer 3 by etching.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、多層プリント基板
における非貫通の穴を有するプリント基板の加工方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for processing a printed circuit board having a non-through hole in a multilayer printed circuit board.

【0002】[0002]

【従来の技術】電子機器に用いられる基板において、電
子機器の小型化や薄型化等の要求に応えるため、様々な
形状並びに構造のLSIパッケージ並びにプリント基板
が案出されており、高密度化が図られるため、プリント
基板に穿設する非貫通穴或いは貫通孔の口径が小さくな
る傾向がある。従来のプリント基板の穴明け加工は、主
としてドリルによる加工が用いられており、その穴明け
加工は穴の径 0.1mmφが通常の最小加工限界であるが、
一般的には量産化する場合の加工限界は 0.3mmφ程度と
されている。図6に示すように、プリント基板の穴明け
加工は、樹脂等で形成された板状の絶縁層aの上下面に
銅箔b,cが貼付された基板の適所にドリルdで貫通孔
eを穿設した(イ参照)後、銅箔b,cの表面及び貫通
孔eの内面にメッキfを施して絶縁層aの上下面の銅箔
bとcとを電気的に導通させ(ロ参照)、その後、絶縁
層aの上下面をエッチングしてメッキf及び銅箔b,c
の一部を除去して絶縁層aの上下面にメッキ層f1 で接
続される回路パターンb1 ,c1 (ハ参照)を形成す
る。
2. Description of the Related Art For substrates used in electronic devices, LSI packages and printed boards of various shapes and structures have been devised in order to meet demands for smaller and thinner electronic devices. Therefore, the diameter of the non-through hole or the through hole formed in the printed circuit board tends to be small. Conventional drilling of printed circuit boards is mainly performed by drilling, and the hole drilling is usually 0.1 mmφ in the hole minimum diameter is the minimum processing limit,
Generally, the processing limit for mass production is about 0.3 mmφ. As shown in FIG. 6, a hole is formed in a printed board by a drill d at an appropriate position on a board having copper foils b and c adhered to upper and lower surfaces of a plate-shaped insulating layer a made of resin or the like. (See (a)), plating f is applied to the surfaces of the copper foils b and c and the inner surface of the through hole e to electrically connect the copper foils b and c on the upper and lower surfaces of the insulating layer a (b). Then, the upper and lower surfaces of the insulating layer a are etched to perform plating f and copper foils b and c.
Are removed to form circuit patterns b 1 and c 1 (see C) connected to the upper and lower surfaces of the insulating layer a by the plating layer f 1 .

【0003】また、図7において、非貫通穴を持つ多層
のプリント基板について説明する。樹脂等で形成した2
枚の絶縁層a1 及びa2 の上下面に、それぞれ銅箔
1 ,c1 及びb2 ,c2 を貼付し、ドリル(図示略)
により、絶縁層a1 及びa2 をそれぞれ貫通する孔
1 ,e2 を穿設し(イ参照)、銅箔b1 ,c1 及びb
2 ,c2 と貫通孔e1 ,e2 の内面とにメッキf1 ,f
2 を施して、絶縁層a1 及びa2 の上下面の銅箔b1
1 及びb2 とc2 をそれぞれ電気的に導通させ(ロ参
照)、その後絶縁層a1 ,a2 の上下面または片面(図
7では、絶縁層a1 は上面、a2 は下面のみ)をエッチ
ングしてメッキf1 ,f2 及び銅箔b1 ,c1及び
2 ,c2 の一部を除去して絶縁層a1 ,a2 の上下面
または片面(図7では、絶縁層a1 は上面、a2 は下面
のみ)に、メッキ層f11,f22でそれそれ反対側面の銅
箔c1 ,b2 に接続される回路パターンb11,c22(ハ
参照)を形成する。絶縁層a1 とa2 とを、回路パター
ンb1 ,c2 を備える面をそれぞれ対向させ、両絶縁層
1 ,a2 の間にプリプレグ等の接着シートgを介在さ
せて接続し、多層プリント基板を形成する。この時、孔
1 ,e2 は、接着シートgで孔の一方の開口を塞が
れ、非貫通穴となる。
FIG. 7 shows a multi-layer printed circuit board having a non-through hole. 2 made of resin, etc.
Copper foils b 1 , c 1 and b 2 , c 2 are attached to the upper and lower surfaces of the insulating layers a 1 and a 2 respectively, and a drill (not shown)
Thereby, holes e 1 and e 2 penetrating the insulating layers a 1 and a 2 respectively are formed (see (a)), and the copper foils b 1 , c 1 and b
2 , c 2 and the inner surfaces of the through holes e 1 , e 2 are plated f 1 , f 2
2 by subjecting the insulating layer a 1 and is respectively electrically connected to the copper foil b 1 of the upper and lower surfaces c 1 and b 2 and c 2 of a 2 (see B), thereafter the insulating layer a 1, a 2 (7, insulating layer a 1 is a top, a 2 the lower surface only) top and bottom surfaces or one surface a part of the plating f 1, f 2 and the copper foil b 1, c 1 and b 2, c 2 are etched After removal, the upper and lower surfaces or one surface of the insulating layers a 1 and a 2 (in FIG. 7, the insulating layer a 1 is the upper surface and a 2 is the lower surface only), and the plating layers f 11 and f 22 are provided with copper foil on the opposite side. Circuit patterns b 11 and c 22 (see c) connected to c 1 and b 2 are formed. The insulating layers a 1 and a 2 are connected to each other with the surfaces provided with the circuit patterns b 1 and c 2 facing each other and an adhesive sheet g such as a prepreg is interposed between the insulating layers a 1 and a 2 to form a multilayer structure. Form a printed circuit board. At this time, the holes e 1 and e 2 become non-through holes by closing one of the holes with the adhesive sheet g.

【0004】また、さらに高密度化するために 0.3mmφ
以下の非貫通穴を有するプリント基板が必要となり、従
来のドリル加工から、絶縁層を感光性(光硬化性)樹脂
で形成するフォト法による穴加工、或いはレーザ光によ
る穴加工が行われるようになった。図8を参照してフォ
ト法による穴加工を説明すると、イに示すものは、光硬
化性樹脂を用いたものであり、通常の樹脂から成る絶縁
層aの両面に銅箔で形成された内層回路hを設け、内層
回路hを挟んで光硬化性樹脂から成る絶縁層a0 ,a0
を両面に接合したものを、所定の位置jを遮光するマス
クを配置して紫外線等の光kを照射して樹脂を硬化さ
せ、その後遮光位置jに対応する部位m即ち硬化しない
部位mを除去して底部に内層回路hが露出した非貫通穴
nが形成された後(ハ参照)、非貫通穴nの内壁及び底
壁(内層回路hの露出表面)全体及び絶縁層aの外面全
体にわたってメッキpを施した後、エッチングしてメッ
キpの一部を除去するとともに、外層回路qを形成する
(ニ参照)。一方、レーザ光を用いる穴加工(ロ参照)
は絶縁層aの表層からレーザ光rを照射して内層回路h
を露出させている。
In order to further increase the density, 0.3 mmφ
A printed circuit board having the following non-through holes is required, so that hole processing by a photo method in which an insulating layer is formed of a photosensitive (photocurable) resin or hole processing by a laser beam is performed from conventional drilling. became. The hole processing by the photo method will be described with reference to FIG. 8. The one shown in (a) uses a photocurable resin, and an inner layer formed of copper foil on both surfaces of an insulating layer a made of a normal resin. A circuit h is provided, and insulating layers a 0 , a 0 made of a photocurable resin sandwich the inner layer circuit h.
Is bonded to both surfaces, a mask for shielding light at a predetermined position j is arranged, and the resin is cured by irradiating light k such as ultraviolet light, and then a portion m corresponding to the light shielding position j, that is, a portion m that is not cured is removed. Then, after the non-through hole n in which the inner layer circuit h is exposed is formed at the bottom (see C), the entire inner wall and bottom wall of the non-through hole n (exposed surface of the inner layer circuit h) and the entire outer surface of the insulating layer a are exposed. After the plating p is applied, a part of the plating p is removed by etching, and an outer layer circuit q is formed (see d). On the other hand, drilling using laser light (see b)
Irradiates a laser beam r from the surface of the insulating layer a to form an inner layer circuit h.
Is exposed.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来のプリント基板の加工方法においては、内層回路hの
上に絶縁層aの一部が残膜sとして残留することがある
(図9参照)。このように内層回路hの上に絶縁層aの
残膜sがある場合に、内層回路hと表面に設けられる外
層回路qとの接続を行うために非貫通穴nにメッキpを
施しても、メッキpと内層回路hとの間に残膜sが存在
することになり(図10参照)、内層回路hの上面との
接続ができない、または接続の信頼性を損なうという問
題があった。また図11に示すように、非貫通穴nの内
部周壁が略垂直に形成されているから、内層回路hの上
面と非貫通穴nの内部周壁、及び絶縁層aの上面にわた
ってメッキpを施した時に、非貫通穴nの底部である内
層回路hの上面から非貫通穴nの内部周壁にかけて均一
なメッキ層を得ることが難しく、内層回路hの上面に設
けられたメッキ層p1 と、非貫通穴nの内部周壁に付着
したメッキ層p2 との接合部にメッキpが十分に析出せ
ず、メッキpが薄くなる、或いはメッキ層p1とメッキ
層p2 との接合部に間隙tができて、電気的接続の信頼
性を損なうという問題があった。さらに、残膜sを生じ
させないためにレーザ光rの出力を大きくすると、残膜
sをある程度除去することが可能であるが、全てを除去
することが極めて困難であるとともに、レーザ光rの出
力が大きくなると、非貫通穴nの周壁が一層垂直に形成
されることになり、メッキpを施した時に、非貫通穴n
の周壁と底面との接合部にメッキpが十分に析出せず、
メッキpが薄くなり、電気的接続の信頼性を損なうとい
う問題があった。
However, in the above-mentioned conventional method for processing a printed circuit board, a part of the insulating layer a may remain as a residual film s on the inner layer circuit h (see FIG. 9). In the case where the remaining film s of the insulating layer a is present on the inner layer circuit h as described above, even if the non-through hole n is plated p in order to connect the inner layer circuit h to the outer layer circuit q provided on the surface. As a result, a residual film s exists between the plating p and the inner layer circuit h (see FIG. 10), and there has been a problem that connection to the upper surface of the inner layer circuit h cannot be made or connection reliability is impaired. Further, as shown in FIG. 11, since the inner peripheral wall of the non-through hole n is formed substantially vertically, plating p is applied to the upper surface of the inner layer circuit h, the inner peripheral wall of the non-through hole n, and the upper surface of the insulating layer a. Then, it is difficult to obtain a uniform plating layer from the upper surface of the inner circuit h, which is the bottom of the non-through hole n, to the inner peripheral wall of the non-through hole n, and a plating layer p 1 provided on the upper surface of the inner circuit h, plating p the junction between the plated layer p 2 attached to the inside wall of non-through holes n is not sufficiently precipitated, plating p is reduced, or the gap at the junction of the plating layer p 1 and the plating layer p 2 There is a problem in that the reliability of the electrical connection is impaired due to the formation of the electrical connection. Furthermore, if the output of the laser light r is increased to prevent the residual film s from being generated, it is possible to remove the residual film s to some extent, but it is extremely difficult to remove all of the residual film s and the output of the laser light r Becomes larger, the peripheral wall of the non-through hole n is formed more vertically, and when the plating p is applied, the non-through hole n
Plating p does not sufficiently precipitate at the joint between the peripheral wall and the bottom surface of
There has been a problem that the plating p becomes thin and the reliability of electrical connection is impaired.

【0006】本発明の目的は、多層プリント基板におけ
る非貫通の穴による内層回路と外層回路との電気的接続
を確実に行うことのできるプリント基板の加工方法を提
供することである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of processing a printed circuit board capable of securely connecting an inner layer circuit and an outer layer circuit by a non-through hole in a multilayer printed circuit board.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に本発明のプリント基板の加工方法は、基板と、基板の
表面に設けられた内層回路と、該内層回路を含めて基板
の表面を覆う絶縁層と、絶縁層の外表面に設けられた外
層回路とを備えたプリント基板の加工方法であって、レ
ーザ光を照射して底部に内層回路の上面を露出させた非
貫通穴を穿設した後、非貫通穴を洗浄して残留した絶縁
層を除去することにより、内層回路の表面の上の樹脂の
残留物を除去することができ、メッキと内層回路との接
触を確実にすることができ、電気的接続の信頼性を向上
させることができる。また、レーザ光の出力を弱めて、
非貫通穴の周壁を底部に向けて中央側に傾斜させたこと
により、非貫通穴の底面(内層回路の上面)と周壁とが
形成する角度が鈍角になるから、洗浄性が向上し、十分
な樹脂残留物の溶解を行うことができるとともに、メッ
キの付き回り性が向上し、非貫通穴内壁で均一な厚さの
メッキを得ることができる。
In order to achieve the above object, a method for processing a printed circuit board according to the present invention comprises the steps of: forming a substrate, an inner layer circuit provided on the surface of the substrate, and a surface of the substrate including the inner layer circuit. A method for processing a printed circuit board having an insulating layer to cover and an outer layer circuit provided on an outer surface of the insulating layer, wherein a non-through hole exposing the upper surface of the inner layer circuit is formed at the bottom by irradiating a laser beam. After the installation, the non-through hole is washed to remove the remaining insulating layer, so that the resin residue on the surface of the inner layer circuit can be removed, and the contact between the plating and the inner layer circuit is ensured. And the reliability of the electrical connection can be improved. Also, weaken the output of the laser light,
By inclining the peripheral wall of the non-through hole toward the bottom toward the center, the angle formed between the bottom surface of the non-through hole (the upper surface of the inner layer circuit) and the peripheral wall becomes obtuse. In addition to dissolving the resin residue, the throwing power of the plating is improved, and the plating having a uniform thickness can be obtained on the inner wall of the non-through hole.

【0008】[0008]

【発明の実施の形態】本発明の実施例を図面を参照して
説明する。図5において、本発明の加工方法を適用する
プリント基板について説明する。プリント基板1の一側
面に内層回路2を予め形成し、その上に絶縁層となる樹
脂層3を適宜位置に設けて、内層回路2の導体部分であ
るパッド20を露出させ、他の部分を絶縁層3で被覆す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. In FIG. 5, a printed circuit board to which the processing method of the present invention is applied will be described. An inner layer circuit 2 is previously formed on one side surface of the printed circuit board 1, a resin layer 3 serving as an insulating layer is provided at an appropriate position thereon, and a pad 20 which is a conductor of the inner layer circuit 2 is exposed. It is covered with an insulating layer 3.

【0009】ICベアチップ4を、本実施例では対向し
て配設されている内層回路2のパッド20の間に載置し、
ボンディングワイヤ5を用いてICベアチップ4とパッ
ド20とをボンディング接続する。なお、内層回路2のパ
ッド20は、ICベアチップを挟んで両側に対向して設け
られたものに限定されるわけではなく、ICベアチップ
の全周或いは三方を囲むように、或いは一方に設けても
良いことは当然である。
In this embodiment, the IC bare chip 4 is placed between the pads 20 of the inner layer circuit 2 which is arranged to face each other.
The IC bare chip 4 and the pad 20 are connected by bonding using the bonding wire 5. Note that the pads 20 of the inner layer circuit 2 are not limited to those provided on both sides of the IC bare chip so as to be opposed to each other. The good is natural.

【0010】ICベアチップ4の周囲に絶縁層3の厚さ
による段差が形成されて流れ防止ダムとなり、ICベア
チップ4を載置した部分を覆って樹脂等の封止剤6が流
し込まれる際に、不要な部分にまで封止剤6が流出する
ことを防止する。ICベアチップ4を載置した部分を覆
う封止剤6が流し込まれ、ICベアチップ4とボンディ
ングワイヤ5及びパッド20を封止剤6で被覆して保護し
ている。絶縁層3の外側面と内層回路2とを接続するた
めに、絶縁層3の所定位置にバイアホール7を絶縁層3
を貫通して穿設し、内層回路2をバイアホール7内にお
いて露出させた後、メッキ70によってバイアホール7内
の内層回路2と絶縁層3の外側面とを電気的に接続し、
絶縁層3の外側面にはメッキ70に接続された外側回路71
が設けられている。
A step due to the thickness of the insulating layer 3 is formed around the IC bare chip 4 to form a flow prevention dam. When the sealing agent 6 such as resin is poured over the portion where the IC bare chip 4 is mounted, This prevents the sealant 6 from flowing out to unnecessary parts. The sealant 6 covering the portion where the IC bare chip 4 is mounted is poured in, and the IC bare chip 4, the bonding wires 5 and the pads 20 are covered and protected by the sealant 6. In order to connect the outer surface of the insulating layer 3 and the inner layer circuit 2, via holes 7 are formed at predetermined positions of the insulating layer 3.
After the inner circuit 2 is exposed in the via hole 7, the inner circuit 2 in the via hole 7 and the outer surface of the insulating layer 3 are electrically connected by plating 70,
An outer circuit 71 connected to the plating 70 is provided on the outer surface of the insulating layer 3.
Is provided.

【0011】外側回路71は、絶縁層3の外側面におい
て、電子部品等に接続する外部パッド72を備えており、
外部パッド72と、別に絶縁層3の外側面に設けられた電
子部品実装用パッド73とに電子部品8の脚をハンダ付け
する。なお、本実施例においては、プリント基板の一側
面にのみICベアチップを設けたものについて述べてき
たが、プリント基板の両側面に、それぞれ内層回路を設
け、上記実施例と同様にしてICベアチップを設けるこ
とができることは勿論である。また、上記電子部品8に
代えて、ICベアチップを接続することもできる。
The outer circuit 71 has external pads 72 on the outer surface of the insulating layer 3 for connecting to electronic components and the like.
The legs of the electronic component 8 are soldered to the external pad 72 and the electronic component mounting pad 73 separately provided on the outer surface of the insulating layer 3. In this embodiment, the case where the IC bare chip is provided only on one side of the printed board has been described. However, the inner layer circuits are provided on both side faces of the printed board, and the IC bare chip is provided in the same manner as in the above embodiment. Of course, it can be provided. Further, instead of the electronic component 8, an IC bare chip can be connected.

【0012】図を参照して本発明の加工方法の一例につ
いて説明する。図2において、プリント基板の基板1の
表面に、部品実装に合わせた導体回路である内層回路2
がエッチング加工等によって形成され、その上から絶縁
性の樹脂を塗布して絶縁層3を基板1の全面に形成した
後、絶縁層3の必要部分を除去する。絶縁層を除去する
部分として、ICベアチップ4を載置する矩形部分と、
露出させたい内層回路2の部分(内層回路2のバイアホ
ール7等)を定める。
An example of the processing method of the present invention will be described with reference to the drawings. In FIG. 2, an inner layer circuit 2 which is a conductor circuit adapted to component mounting is provided on the surface of a printed circuit board 1.
Is formed by etching or the like, and an insulating resin is applied thereon to form an insulating layer 3 over the entire surface of the substrate 1, and then a necessary portion of the insulating layer 3 is removed. A rectangular portion on which the IC bare chip 4 is mounted as a portion for removing the insulating layer;
The portion of the inner circuit 2 to be exposed (the via hole 7 of the inner circuit 2 and the like) is determined.

【0013】ここでは、底部に内層回路2を露出させる
必要のある部分としてバイアホール7の加工について述
べる。バイアホール7を形成する部位における絶縁層3
の除去される部分3Aに、レーザ照射装置9から、通常
出力または出力を小さくしたレーザ光Rを照射して、除
去される部分3Aを焼失させて除去し、底部に内層回路
2の上面21が露出するバイアホール用穴(非貫通穴)7
Aを形成する(図3参照)。
Here, processing of the via hole 7 will be described as a portion where the inner layer circuit 2 needs to be exposed at the bottom. Insulating layer 3 at the site where via hole 7 is formed
Is irradiated with a laser beam R having a normal output or a reduced output from the laser irradiation device 9 to burn off the removed portion 3A, and the upper surface 21 of the inner layer circuit 2 is formed at the bottom. Exposed via hole (non-through hole) 7
A is formed (see FIG. 3).

【0014】ここで、レーザ加工の一例について説明す
ると、 0.1〜 0.2mmφの穴を形成する際のレーザ加工に
おいては、レーザ光の波長は 9.2〜10.6μmのCO2
スレーザで、10W〜 300Wの出力を有するレーザ発振器
から出力されたレーザ光を、マスク孔等を通して、 0.1
〜 0.2mmφのスポット径にして絶縁層3上に、照射時間
が16μs〜80μsのパルス幅で照射する。この時の連続
出力は、 2.0W〜 0.3Wであり、1パルス当たりの絶縁
層樹脂の焼失深さを0.01〜0.05mm程度として2パルス〜
10パルスで1個の非貫通穴7Aを形成することによ
り、絶縁層3の上面から内層回路2の上面に向かって、
非貫通穴7Aの周壁74を穴の中央側に傾斜させること
ができる。
Here, an example of laser processing will be described. In laser processing for forming a hole having a diameter of 0.1 to 0.2 mm, the wavelength of a laser beam is a CO 2 gas laser of 9.2 to 10.6 μm and an output of 10 W to 300 W. Laser light output from a laser oscillator having
Irradiation is performed on the insulating layer 3 with a pulse diameter of 16 μs to 80 μs on the insulating layer 3 with a spot diameter of about 0.2 mmφ. The continuous output at this time is 2.0 W to 0.3 W, and the burnout depth of the insulating layer resin per pulse is about 0.01 to 0.05 mm, and 2 pulses to 2 W
By forming one non-through hole 7A with 10 pulses, from the upper surface of the insulating layer 3 toward the upper surface of the inner layer circuit 2,
The peripheral wall 74 of the non-through hole 7A can be inclined toward the center of the hole.

【0015】なお、周壁74の傾斜角度θは、絶縁層3
の上面への法線VLに対して周壁74が成す角度であり、
θ=15°〜25°が適しており(図4参照)、θが1
5°より小さい(θ<15°)と、周壁が垂直に近くな
って、メッキ層を均一に設けることが困難になり、θが
25°より大きい(θ>25°)と、底部の径が同一で
あれば穴の上端開口が過大となり、プリント基板が大き
くなるという問題がある。逆に上端開口が同一であれ
ば、底部の径が小さくなり、接続面積が小さくなって電
気的接続に欠陥を生じる恐れがあるという問題がある。
Note that the inclination angle θ of the peripheral wall 74 is
Is the angle formed by the peripheral wall 74 with respect to the normal VL to the upper surface of
θ = 15 ° to 25 ° is suitable (see FIG. 4), and θ is 1
When the angle is smaller than 5 ° (θ <15 °), the peripheral wall becomes almost vertical, and it becomes difficult to uniformly form the plating layer. When the angle θ is larger than 25 ° (θ> 25 °), the diameter of the bottom becomes small. If they are the same, there is a problem that the upper end opening of the hole becomes excessively large and the printed circuit board becomes large. Conversely, if the upper end openings are the same, there is a problem that the diameter of the bottom becomes small, the connection area becomes small, and there is a possibility that a defect occurs in the electrical connection.

【0016】上述の如く、通常出力または低出力のレー
ザ光Rを照射して絶縁層3の部分3Aを焼失させて除去
する(図2参照)際に、バイアホール用穴7Aの周壁74
を下方に向けて中央側に向けて斜めに形成する、即ち上
方開口よりも底部の面積が小さくなるように傾斜させて
形成し(図3参照)、バイアホール用穴7A内に過マン
ガン酸塩溶液等の樹脂を溶解する溶液を噴霧する、或い
は過マンガン酸塩溶液等の樹脂を溶解する溶液に浸漬す
ることにより、バイアホール用穴7A内を洗浄する。
As described above, when the normal output or low output laser beam R is applied to burn and remove the portion 3A of the insulating layer 3 (see FIG. 2), the peripheral wall 74 of the via hole 7A is removed.
Are formed diagonally downward toward the center, that is, inclined so that the area of the bottom is smaller than the upper opening (see FIG. 3), and the permanganate is formed in the via hole 7A. The inside of the via hole 7A is washed by spraying a solution that dissolves the resin such as a solution or by immersing it in a solution that dissolves the resin such as a permanganate solution.

【0017】レーザ加工のみでは、バイアホール用穴7
Aの底部の内層回路2の上面21に絶縁層3を形成する樹
脂の残留物3Bが存在する(図3参照)が、バイアホー
ル用穴7A内を過マンガン酸塩溶液等の樹脂を溶解する
溶液で洗浄することにより、内層回路2の上面21の上の
樹脂残留物3Bを溶解して除去し、内層回路2の上面21
を清浄にした(図4参照)後、図1に示すように、バイ
アホール用穴7Aにメッキ70を施した後、絶縁層3の外
表面に外層回路71を設け、メッキ70と外層回路71を接触
させ、内層回路2と外層回路71とを電気的に接続し、バ
イアホール7を形成する。
In the case of only laser processing, the hole 7 for the via hole is used.
Residues 3B of the resin forming the insulating layer 3 are present on the upper surface 21 of the inner circuit 2 at the bottom of A (see FIG. 3), but the resin such as permanganate solution is dissolved in the via hole 7A. By washing with a solution, the resin residue 3B on the upper surface 21 of the inner circuit 2 is dissolved and removed, and the upper surface 21 of the inner circuit 2 is removed.
After cleaning (see FIG. 4), as shown in FIG. 1, plating 70 is applied to the via hole 7A, and an outer layer circuit 71 is provided on the outer surface of the insulating layer 3, and the plating 70 and the outer layer circuit 71 are provided. To electrically connect the inner layer circuit 2 and the outer layer circuit 71 to form a via hole 7.

【0018】この構成により、内層回路2の上面21の上
の樹脂の残留物3Bを除去することができ、メッキ70と
内層回路2との接触を確実にすることができ、電気的接
続の信頼性を向上させることができる。また、バイアホ
ール用穴7Aの周壁74を傾斜させたことにより、底面
(内層回路2の上面21)と周壁74とが形成する角度が鈍
角になるから、洗浄性が向上し、十分な樹脂残留物3B
の溶解を行うことができるとともに、メッキ70の付き回
り性が向上し、均一な厚さのメッキを得ることができ
る。
With this configuration, the resin residue 3B on the upper surface 21 of the inner layer circuit 2 can be removed, the contact between the plating 70 and the inner layer circuit 2 can be ensured, and the reliability of the electrical connection can be improved. Performance can be improved. In addition, since the peripheral wall 74 of the via hole 7A is inclined, the angle formed between the bottom surface (the upper surface 21 of the inner layer circuit 2) and the peripheral wall 74 becomes obtuse. Thing 3B
Can be dissolved, the throwing power of the plating 70 is improved, and a plating having a uniform thickness can be obtained.

【0019】[0019]

【実施例】レーザ光によって周壁を傾斜させた形状の穴
を形成することにより、洗浄・溶解を行い易くし、絶縁
層表面と穴周壁及び穴底部のメッキ厚を均一にし、残膜
を十分に溶解、洗浄することで次のような結果を得た。
下記の各試験で100サイクル以上、または500時間
以上の耐久の電気的接続信頼性のあるプリント基板を得
ることができた。 〔実施例製品パターン〕:絶縁層厚さ 80μm 穴径 150μm (絶縁層表面開口径 170μm) (穴底部径 140μm) メッキ厚さ 20μm (1)熱衝撃試験(液中) a.下記〜の作業を順次繰り返し(→→→
→→・・・)、〜で1サイクルとして100サイ
クル繰り返す。 −40℃の液に30分浸漬 室温で5分放置 125℃の液に30分浸漬 室温で5分放置 b.下記との作業を順次繰り返し、→を1サイ
クルとして100サイクル繰り返す。 −65℃の液に30分浸漬 125℃の液に30分浸漬 (2)高温放置試験(気中) 気温125℃の雰囲気中に500時間放置する。 (3)低温放置試験(気中) 気温−40℃の雰囲気中に500時間放置する。 (4)恒温恒湿試験(気中) 気温85℃で湿度85%の雰囲気中に500時間放置す
る。 (5)オイルディップ試験 下記との作業を順次繰り返し、→を1サイクル
として100サイクル繰り返す。 温度260℃の油に10秒浸漬 温度10℃の油に10秒浸漬 注)作業ととの移動に要する時間は15秒とする。
EXAMPLE By forming a hole having a shape in which the peripheral wall is inclined by laser light, cleaning and melting are facilitated, the plating thickness on the surface of the insulating layer, the peripheral wall of the hole and the bottom of the hole are made uniform, and the residual film is sufficiently removed. The following results were obtained by dissolving and washing.
In each of the tests described below, a printed circuit board having a durable electrical connection of 100 cycles or more or 500 hours or more was obtained. [Example product pattern]: Insulation layer thickness 80 μm Hole diameter 150 μm (Insulation layer surface opening diameter 170 μm) (Hole bottom diameter 140 μm) Plating thickness 20 μm (1) Thermal shock test (in liquid) a. Repeat the following steps sequentially (→→→
→→ ・ ・ ・), and repeat as 100 cycles as 1 cycle. Immerse in liquid at -40 ° C for 30 minutes Leave at room temperature for 5 minutes Immerse in liquid at 125 ° C for 30 minutes Leave at room temperature for 5 minutes b. The following operations are sequentially repeated, and → is defined as one cycle, and 100 cycles are repeated. Immersion in a liquid at -65 ° C for 30 minutes Immersion in a liquid at 125 ° C for 30 minutes (2) High-temperature storage test (in the air) The device is left in an atmosphere at a temperature of 125 ° C for 500 hours. (3) Low temperature test (air) The sample is left in an atmosphere at a temperature of -40 ° C for 500 hours. (4) Constant Temperature and Humidity Test (Air) The sample is left for 500 hours in an atmosphere at a temperature of 85 ° C. and a humidity of 85%. (5) Oil dip test The following operations are sequentially repeated, and 100 cycles are repeated with → as one cycle. Immerse in oil at a temperature of 260 ° C for 10 seconds. Immerse in oil at a temperature of 10 ° C for 10 seconds. Note) The time required for movement with work is 15 seconds.

【0020】[0020]

【発明の効果】本発明は上述のとおり構成されているか
ら、以下に述べるとおりの効果を奏する。レーザ光を照
射して底部に内層回路の上面を露出させた非貫通穴を穿
設した後、非貫通穴を洗浄して残留した絶縁層を除去す
ることにより、内層回路の表面の上の樹脂の残留物を除
去することができ、メッキと内層回路との接触を確実に
することができる。また、レーザ光の出力を弱めて、非
貫通穴の周壁を底部に向けて中央側に傾斜させたことに
より、非貫通穴の底面(内層回路の上面)と周壁とが形
成する角度が鈍角になるから、洗浄性が向上し、十分な
樹脂残留物の溶解を行うことができるとともに、メッキ
の付き回り性が向上し、均一な厚さのメッキを得ること
ができ、電気的接続の信頼性を向上させることができ
る。
Since the present invention is configured as described above, it has the following effects. After irradiating a laser beam to form a non-through hole exposing the upper surface of the inner layer circuit at the bottom, the non-through hole is washed and the remaining insulating layer is removed to remove the resin on the surface of the inner layer circuit. Residue can be removed, and contact between the plating and the inner layer circuit can be ensured. Also, by weakening the output of the laser beam and inclining the peripheral wall of the non-through hole toward the center toward the bottom, the angle formed between the bottom surface of the non-through hole (the upper surface of the inner layer circuit) and the peripheral wall becomes obtuse. As a result, the cleaning property is improved, sufficient resin residue can be dissolved, the throwing power of the plating is improved, the plating having a uniform thickness can be obtained, and the reliability of the electrical connection can be obtained. Can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明のプリント基板の断面図である。FIG. 1 is a sectional view of a printed circuit board according to the present invention.

【図2】 本発明のプリント基板のレーザ加工時の断面
図である。
FIG. 2 is a cross-sectional view of the printed circuit board of the present invention during laser processing.

【図3】 本発明のプリント基板のレーザ加工終了時の
断面図である。
FIG. 3 is a cross-sectional view of the printed circuit board of the present invention at the end of laser processing.

【図4】 本発明のプリント基板の洗浄後の断面図であ
る。
FIG. 4 is a sectional view of the printed circuit board of the present invention after cleaning.

【図5】 本発明を適用した表面実装型LSIパッケー
ジの一例を示す断面図である。
FIG. 5 is a cross-sectional view illustrating an example of a surface-mount LSI package to which the present invention is applied.

【図6】 従来のドリル加工を示す説明図である。FIG. 6 is an explanatory view showing a conventional drilling process.

【図7】 従来の非貫通穴の加工を示す説明図である。FIG. 7 is an explanatory view showing processing of a conventional non-through hole.

【図8】 従来のフォト法及びレーザ加工を示す説明図
である。
FIG. 8 is an explanatory view showing a conventional photo method and laser processing.

【図9】 従来のプリント基板のレーザ加工終了時の断
面図である。
FIG. 9 is a cross-sectional view of a conventional printed circuit board at the end of laser processing.

【図10】 従来のプリント基板のメッキ終了時の断面
図である。
FIG. 10 is a cross-sectional view of a conventional printed circuit board when plating is completed.

【図11】 従来のプリント基板のメッキ終了時の断面
図である。
FIG. 11 is a cross-sectional view of a conventional printed circuit board when plating is completed.

【符号の説明】[Explanation of symbols]

1 基板、2 内層回路、3 絶縁層、4 ICベアチ
ップ 5 ボンディングワイヤ、6 封止剤、7 バイアホー
ル、20 パッド 71 外層回路
1 substrate, 2 inner layer circuit, 3 insulating layer, 4 IC bare chip 5 bonding wire, 6 sealant, 7 via hole, 20 pad 71 outer layer circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板と、基板の表面に設けられた内層回
路と、該内層回路を含めて基板の表面を覆う絶縁層と、
絶縁層の外表面に設けられた外層回路とを備えたプリン
ト基板の加工方法であって、レーザ光を照射して底部に
内層回路の上面を露出させた非貫通穴を穿設した後、非
貫通穴を洗浄して残留した絶縁層を除去することを特徴
とするプリント基板の加工方法。
A substrate, an inner layer circuit provided on the surface of the substrate, an insulating layer covering the surface of the substrate including the inner layer circuit,
A method of processing a printed circuit board having an outer layer circuit provided on an outer surface of an insulating layer, the method comprising: irradiating a laser beam to form a non-through hole exposing an upper surface of an inner layer circuit at a bottom portion; A method for processing a printed circuit board, comprising cleaning a through hole to remove a remaining insulating layer.
【請求項2】 レーザ光の出力を弱めて、非貫通穴の周
壁を底部に向けて中央側に傾斜させたことを特徴とする
請求項1記載のプリント基板の加工方法。
2. The method for processing a printed circuit board according to claim 1, wherein the output of the laser beam is reduced, and the peripheral wall of the non-through hole is inclined toward the center toward the bottom.
JP28903096A 1996-10-14 1996-10-14 Method for working printed board Pending JPH10117058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28903096A JPH10117058A (en) 1996-10-14 1996-10-14 Method for working printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28903096A JPH10117058A (en) 1996-10-14 1996-10-14 Method for working printed board

Publications (1)

Publication Number Publication Date
JPH10117058A true JPH10117058A (en) 1998-05-06

Family

ID=17737926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28903096A Pending JPH10117058A (en) 1996-10-14 1996-10-14 Method for working printed board

Country Status (1)

Country Link
JP (1) JPH10117058A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0969707A2 (en) * 1998-06-30 2000-01-05 Matsushita Electric Works, Ltd. Multilayer printed wiring board and method for manufacturing same
WO2003044872A1 (en) * 2001-11-19 2003-05-30 Sanyo Electric Co., Ltd. Compound semiconductor light emitting device and its manufacturing method
JP2004343139A (en) * 2001-11-19 2004-12-02 Sanyo Electric Co Ltd Compound semiconductor light emitting element
JP2005005727A (en) * 2001-11-19 2005-01-06 Sanyo Electric Co Ltd Compound semiconductor light emitting device
US7438945B2 (en) 2004-01-16 2008-10-21 Shinko Electric Industries Co., Ltd. Method of producing multilayer interconnection board

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0969707A2 (en) * 1998-06-30 2000-01-05 Matsushita Electric Works, Ltd. Multilayer printed wiring board and method for manufacturing same
EP0969707A3 (en) * 1998-06-30 2000-11-22 Matsushita Electric Works, Ltd. Multilayer printed wiring board and method for manufacturing same
WO2003044872A1 (en) * 2001-11-19 2003-05-30 Sanyo Electric Co., Ltd. Compound semiconductor light emitting device and its manufacturing method
JP2004343139A (en) * 2001-11-19 2004-12-02 Sanyo Electric Co Ltd Compound semiconductor light emitting element
JP2005005727A (en) * 2001-11-19 2005-01-06 Sanyo Electric Co Ltd Compound semiconductor light emitting device
JPWO2003044872A1 (en) * 2001-11-19 2005-03-24 三洋電機株式会社 Compound semiconductor light emitting device
US7276742B2 (en) 2001-11-19 2007-10-02 Sanyo Electric Co., Ltd. Compound semiconductor light emitting device and its manufacturing method
US7438945B2 (en) 2004-01-16 2008-10-21 Shinko Electric Industries Co., Ltd. Method of producing multilayer interconnection board

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