JPH065877A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory with improved read/write characteristics, in which parasitic resistance is reduced without in increase in cell area. CONSTITUTION:A source region 4 and a drain region 6 are formed in a p-type silicon substrate 2. A floating gate 12 is formed above a channel region with a gate oxide film 10 interposed, and a control gate 16 is formed above the gate oxide film 12 with an insulating film 14 interposed. A high-melting metal line 18, such as of tungsten, is formed along word lines 16 in the source region 4. A tungsten silicide layer 19 is formed between the metal line and the source region 4. The metal line 18 is connected with a metallized interconnection 24 through a contact hole 22 in an insulating film 20 of PSG, and the metallized interconnection 24 is connected to ground.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to EPROM and EEPRO.
The present invention relates to a nonvolatile semiconductor memory device having a floating gate electrode such as M and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a semiconductor memory device having a floating gate, a floating gate electrode is formed on a channel region between a source region and a drain region via a gate insulating film, and an intermediate insulating film is placed on the floating gate electrode. A continuous control gate electrode is formed for a plurality of memory cells. The control gate electrode also serves as a word line, the source region is formed so as to be continuous with respect to a plurality of memory cells in the word line direction, and the drain region is provided for each memory cell or a pair of memories adjacent to each other in the direction orthogonal to the word line. Independently for each cell, metal wiring is connected to each drain region through a contact hole. Source region is 1
It is connected to the metal wiring through the contact holes at appropriate intervals such as one for every 6 bits.

[0003]

In such a semiconductor memory device, electrons are injected into the floating gate electrode by hot channel electron (HCE) injection to program data. A parasitic resistance is loaded on the source side, which weakens the lateral electric field between the drain and the source.
As shown in FIG. 4A, as the source resistance is increased, the threshold voltage of the written memory cell is lowered and the writing characteristic is deteriorated. Further, when the memory cell is read, the on-current decreases as shown in FIG.
The data in FIG. 4 are measured values for a memory cell having a channel length of 1.2 μm and a channel width of 2.0 μm.
The measurement is performed on each of three wafers at three points. As an example, considering a layout example in which the source region and the metal wiring are in contact every 16 bits of the memory cell, the resistance applied to the source of the memory cell located farthest from the contact between the source and the metal wiring is , R is the sheet resistance of the source region, then 1 / (1 / 8r + 1 / 9r) = 4.23r. If the sheet resistance r is 50Ω, the load resistance of the source is about 210Ω. This is shown in Figure 4 (A).
The threshold voltage of the memory cell written from is about 0.7.
This leads to deterioration of the writing characteristic that V decreases.

To reduce the source resistance in the conventional memory cell structure, the width of the source region must be increased, which results in an increase in the area of the memory cell. Therefore, an object of the present invention is to reduce the parasitic resistance loaded on the source region without increasing the area of the memory cell to improve the write characteristic and the read characteristic.

[0005]

In the semiconductor memory device of the present invention, each memory cell is connected to a source region, and continuous refractory metal film lines are formed for a plurality of memory cells. Are connected to the metal wiring at appropriate intervals. The refractory metal film line is preferably formed as a wiring parallel to the word line which also serves as the control gate electrode.

The manufacturing method of the present invention includes the following steps (A) to (I). (A) A step of depositing a low-resistance first-layer polysilicon film on a semiconductor substrate via a gate insulating film, and (B) a strip-shaped continuous strip in the source region of a plurality of memory cells in the word line direction. Patterning the first layer polysilicon film so as to have an opening and separate the memory cells in the word line direction;
(C) a step of depositing a second-layer polysilicon film having a reduced resistance on the first-layer polysilicon film via an intermediate insulating film, (D) forming a resist pattern for a control gate electrode, A step of patterning the second-layer polysilicon film by using it as a mask to form a word line which also serves as a control gate electrode, (E) the intermediate insulating film is etched by using the resist pattern as a mask, and the first-layer polysilicon film is etched. A step of exposing the substrate to an opening region of the pattern formed in the film; (F) a step of etching the first-layer polysilicon film using the resist pattern as a mask; (G) a conductive type opposite to the substrate in the exposed part of the substrate. And (H) a step of selectively depositing a refractory metal film only on the exposed portion of the substrate by the CVD method, and (I) an opening in the memory portion. A resist pattern is formed as,
A step of forming a source / drain by introducing an impurity of a conductivity type opposite to that of the substrate into the substrate using the two-layer polysilicon film pattern as a mask.

[0007]

Since the refractory metal film line is formed along the source region, the source resistance is lowered.

[0008]

Embodiment FIG. 1 shows an embodiment. (A)
Is a plan view of the memory section, and (B) is a cross-sectional view taken along the line AA ′ in (A). Peripheral transistors are also formed on the same chip, but only the memory portion is shown as an explanation. A strip-shaped continuous N-type source region 4 is formed on the P-type silicon substrate 2, the N-type drain region 6 faces the source region 4 across the channel region, and a memory is provided in the extending direction of the source region 4. The drain region 6 is isolated between the cells by the element isolation oxide film 8. Source area 4
A floating gate electrode 12 made of a polysilicon film having a low resistance of 2000 to 5000 Å is formed on the channel region between the drain region 6 and the drain region 6 on the floating gate electrode 12. Is an insulating film such as a silicon oxide film or an ONO film having a three-layer structure composed of a silicon oxide film, a silicon nitride film and a silicon oxide film, and a film thickness of 100-500 Å through an intermediate insulating film 14. A control gate electrode 16 made of a polysilicon film having a low resistance of 3000 to 5000 Å is formed. The control gate electrode 16 is formed in a continuous strip shape of a plurality of memory cells in parallel with the direction in which the source region 4 extends, and also serves as a word line.

In the source region 4, a refractory metal film line 18 of tungsten or the like is formed along the extending direction of the source region 4, that is, along the direction of the word line 16 which also serves as the control gate electrode. A tungsten silicide layer 19 is formed between the refractory metal film line 18 and the source region 4. Refractory metal film line 18
Is an interlayer insulating film 2 such as a PSG film for each suitable memory cell.
It is connected to the metal wiring 24 through the contact hole 22 of 0, and the metal wiring 24 is connected to the GND terminal.

A region 26 surrounded by a one-dot chain line in FIG.
Represents one memory cell. The drain region 6 is commonly formed by two memory cells adjacent to each other in a direction orthogonal to the word line 16, and a metal wiring 30 is connected to each drain region 6 through a contact hole 28 of an interlayer insulating film. There is.

A manufacturing method of one embodiment will be described with reference to FIGS. (A) forming an element isolation region on the P-type silicon substrate 2,
After the gate oxide film 10 is formed, the first polysilicon film 12a forming the floating gate is formed to 2000.
It is deposited to a thickness of up to 5000 Å and impurities are introduced into the polysilicon film 12a to reduce the resistance. (B) Polysilicon film 12 by photolithography and etching
Pattern a. The pattern at this time is shown in FIG.
As shown in FIG. 3B which is a cross-sectional view taken along line BB ′, the source region of the plurality of memory cells has continuous band-shaped openings in the word line direction and the word line direction. On the other hand, it is a pattern having openings so as to separate the memory cells. Reference numeral 32 represents an opening formed in the polysilicon film 12a at this time.

(C) An intermediate insulating film 14 is formed on the polysilicon film 12a. The intermediate insulating film 14 is 950 to 1100
A silicon oxide film having a film thickness of 100 to 500Å formed by oxidizing the polysilicon film 12a by dry oxidation at ℃ or a silicon nitride film is further deposited on the silicon oxide film, and further wet at 900 to 950 ℃ It is an insulating film having a three-layer structure of ONO in which a silicon oxide film is formed by oxidation. A second-layer polysilicon film 16a is deposited on the intermediate insulating film 14 to a thickness of 3000 to 5000Å, and impurities are introduced into the polysilicon film 16a to reduce the resistance. (D) A resist pattern 34 is formed by photolithography for forming the control gate electrode, and the second-layer polysilicon film 16a is patterned using the resist pattern 34 as a mask to form the control gate electrode 16 which also serves as a word line.

(E) The intermediate insulating film 14 is dry-etched using the resist pattern 34 as a mask. At this time, the silicon substrate 2 in the region where the element isolation field oxide film 8 is not present is exposed at the portion where the opening 32 is formed in the first-layer polysilicon film on the substrate 2. (F) Further, using the resist pattern 34 as a mask, 1
The first layer polysilicon film 12a is patterned to form the floating gate electrode 12. At this time, the silicon substrate 2 exposed in the opening 32 is partially etched to form a recess.

(G) Arsenic, for example, as a donor impurity having a conductivity type opposite to that of the silicon substrate 2 at 1 × 1 at 30 to 50 KeV.
0 ^{14 to} 5 × 10 ¹⁵ / cm ^{2 is} injected. 36 is an implanted N-type impurity layer. After that, selective tungsten CVD
Film thickness 3000 only on the silicon substrate 2 exposed by the method
A tungsten film 18 of about 6000 Å is deposited. No tungsten film is deposited on the substrate covered with the silicon oxide film. (H) Lamp annealing at 500 to 700 ° C. for 30 seconds to 5
When applied for a minute, a silicide layer 19 is formed at the interface between the tungsten film 18 and the silicon substrate 2. After that, a resist pattern is formed by photolithography so as to have an opening in the memory portion, and arsenic is formed at 50 KeV and 6 × 10 ¹⁵ / cm 2.
^Implant about ² to form the source and drain. afterwards,
A peripheral transistor is formed by a usual method, and a final passivation process is performed through a wiring process. In the peripheral transistor, the gate electrode can use the first-layer polysilicon film or the second-layer polysilicon film of the memory section. As the refractory metal, besides tungsten, other materials such as titanium and molybdenum may be used.

[0015]

According to the present invention, since each memory cell is connected to the source region and a continuous refractory metal film line is formed for a plurality of memory cells, the area of the conventional memory cell, especially the width of the source region can be reduced. Without changing, the load resistance of the source region of each memory cell is remarkably reduced, and the writing characteristic of the memory and the driving ability at the time of reading are improved. For example, when tungsten is used as the refractory metal, the sheet resistance of tungsten is about 1/5000 of the sheet resistance of the diffusion layer.
It becomes the following. When the width of the refractory metal film line is set to 1/2 of the conventional source region width in the present invention, the source resistance of the memory cell is reduced to 1/2500 as compared with the conventional case by only doubling the number of resistance sheets. Reduce. Further, also in the contact with the metal wiring, the contact resistance between the tungsten and the silicon substrate is smaller than that of the conventional contact resistance between the silicon substrate and aluminum, which is about 1/4.

Conventionally, there is a difference in the source parasitic resistance value depending on the distance from the source contact, and there is a layout distribution in the memory writing characteristics and driving ability. However, according to the present invention, this characteristic distribution is also present. It can be kept small. Assuming that the source parasitic resistance value (limit resistance value), which is practically no problem, may be loaded, the distance between the source contacts can be made wider than before, and the memory area and chip size can be reduced. It will be possible.
Since the refractory metal film line can be formed by self-alignment in the manufacturing method of the present invention, the photoengraving process for that purpose is not necessary, and in the process of FIG. 2, (F), (G),
Only the addition of three steps (H) is required, and the increase in manufacturing cost is small.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment, (A) is a plan view,
(B) is a sectional view taken along the line AA ′ of (A).

FIG. 2 is a process sectional view showing the manufacturing method of the embodiment.

FIG. 3 is a plan view (A) of the step (B) of FIG. 2 and its BB.
It is a sectional view (B) at the position of the line.

FIG. 4 is a diagram showing a relationship between a source regulating resistance and a memory characteristic, (A) shows a threshold voltage of a written memory cell, and (B) shows an on-current at the time of reading.

[Explanation of symbols]

 2 Silicon substrate 4 Source region 6 Drain region 10 Gate oxide film 12 Floating electrode 14 Intermediate insulating film 16 Control electrode 18 Tungsten film line 19 Tungsten silicide 22 Contact 24 Metal wiring

Claims (3)

[Claims] 1. A floating gate electrode is formed on a channel region between a source region and a drain region via a gate insulating film, and a plurality of memory cells are continuously controlled on the floating gate electrode via an intermediate insulating film. A gate electrode is formed, each memory cell is connected to a source region, and continuous refractory metal film lines are formed for a plurality of memory cells. The refractory metal film lines are formed into metal wiring at appropriate intervals. A semiconductor memory device characterized by being connected. 2. The semiconductor memory device according to claim 1, wherein the refractory metal film line is formed as a wiring parallel to a word line which also serves as a control gate electrode. 3. A method of manufacturing a semiconductor memory device including the following steps (A) to (I). (A) A step of depositing a low-resistance first-layer polysilicon film on a semiconductor substrate via a gate insulating film, (B) a strip-shaped continuous strip in the source region of a plurality of memory cells in the word line direction. Patterning the first-layer polysilicon film so as to separate the memory cells from each other in the word line direction with an opening, (C) on the first-layer polysilicon film through an intermediate insulating film. And (2) forming a resist pattern for the control gate electrode, and patterning the second-layer polysilicon film using the resist pattern as a mask to form the control gate electrode And (E) etching the intermediate insulating film using the resist pattern as a mask to form the word line that also functions as Exposing the substrate to the opening area of the turn; (F) etching the first-layer polysilicon film using the resist pattern as a mask; (G) introducing an impurity of a conductivity type opposite to that of the substrate into the exposed portion of the substrate. And (H) a step of selectively depositing a refractory metal film only on the exposed portion of the substrate by a CVD method, (I) forming a resist pattern so as to have an opening in the memory portion, and forming the two-layer polysilicon film pattern. A step of forming a source / drain by introducing impurities having a conductivity type opposite to that of the substrate into the substrate as a mask.