JPH0658595B2 - Image display device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an image display apparatus applied to an X-ray CT apparatus, a nuclear magnetic resonance (NMR) CT apparatus, or the like.

[Technical Background of the Invention and Problems Thereof] In the conventional device, the entire screen of the monitor was displayed in black and white or in other colors. However, by performing various processes such as window processing and filter processing, gray level It may be difficult to identify each part of the image just by obtaining the change of the image. In such a case, it is considered so that the image before processing and the image after processing can be displayed simultaneously on the same screen for comparison. There is also a device in which image processing is performed only on an arbitrary predetermined area of the image on a single image and the image is displayed together with the area not subjected to the image processing. As the latter device, for example, as described in Japanese Patent Laid-Open No. 59-43466, a CPU performs image processing on a predetermined area of image data, stores the image data in a frame memory, and stores it in the frame memory. There is a device for displaying image data.
However, such a device is insufficient, and an image before processing is displayed in black and white, an image after processing is displayed in color, and image processing is performed only on an arbitrary area of the image on a single image. It has been requested to apply the above to color only that part and color the other areas in black and white or to display in another color, but it has not been proposed yet.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to perform color conversion on a predetermined area and to define the predetermined area for other areas that have not been subjected to image processing. The predetermined area and the other area can be displayed at the same time with different colors, and the predetermined area is colored with respect to the conventional contrast image only in the brightness difference direction, for example, the gray level direction, thereby contributing to the improvement of diagnostic efficiency. It is to provide an image display device capable of

[Summary of the Invention] In order to achieve the above object, the present invention provides an image display device in which at least one predetermined area of image data is subjected to image processing, and other areas are not subjected to image processing and are displayed together with the predetermined area. A frame memory for storing image data including a predetermined area that has undergone image processing; a data conversion memory for converting image data read from the frame memory; and a display memory for storing image data transferred from the data conversion memory. A plurality of color conversion table memories each having a red area, a green area, and a blue area for inputting image data transferred from the display memory and coloring the image data based on an external setting, and each color conversion table Memory red area, green area, blue area By setting a selection means for red, a selection means for green, a selection means for blue for selecting and outputting a predetermined output from the rear for each of red, green and blue, and conditions for selection output from the selection means. Selection control means for controlling each selection means, and the predetermined area subjected to color conversion and color conversion different from the predetermined area based on the outputs from the selection-controlled selection means, The display means is provided for simultaneously displaying the area and

Embodiments of the Invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing the configuration of the image display device according to the present invention. FIG. 10 shows a frame memory that stores image data or other data CD that has undergone window processing, filter processing, etc. in a predetermined area transferred from a central processing unit (CPU) not shown based on the write signal CW. Yes, its output Fd is a multiplexer (M
UX) 16 and is input to the data conversion memory 7 arranged in the subsequent stage. The data conversion memory 7 converts the n ₀ bit (n ₀ bit) output Fd of the frame memory 10 into an n ₁ bit output Cd and has a capacity of 2 ⁿ words. The data conversion memory 7 can be written (written) by a central processing unit (CPU) (not shown).
Various tables can be used to convert the output Cd into n _1- bit output Cd. Then, the output Cd of the data conversion memory 7 is input to the display memory 11 which is arranged in the subsequent stage and has the same space as the frame memory 10 in the matrix sizes X and Y. The output of the display memory 11 is indicated by Dd.

Next, the structure of the memory control means 15 for controlling the operations of the frame memory 10, the display memory 11 and the like will be described.

The timing generator 3 receives the basic clock CLKA, and is provided with a horizontal synchronizing signal HD, a vertical synchronizing signal VD, a horizontal blanking signal ▲ ▼, and a vertical blanking signal ▲, which are used for image display on a display means (not shown).
▼ and the FM address generation counter (D
M ADR CNT) 2, DM address generation counter (DM ADR CNT)
The signal CLKB to be input to 5 is generated. Further, the timing generator 4 uses the base clock CLKA.
And a signal f (x, y) for setting a specific size (partial transfer size to be described later) including a predetermined area that has undergone image processing in the frame memory 10 is input, for example, via a CPU (not shown), and the horizontal synchronization signal HD and the horizontal synchronization signal HD The signals F (x) and F (y) synchronized with the vertical synchronizing signal VD are generated.

Then, the signals F (x) and F (y) which are the outputs of the timing generator 4 pass through the AND circuit 9 which is arranged in the subsequent stage and has two inputs, and the partial transfer address signal F (x, y) is transmitted. Is input to the FM address generation counter 2 and one input end of a logical product circuit 8 arranged at the subsequent stage and having 3 inputs.

Here, the FM address generation counter 2 is, for example, a synchronous load counter, which outputs the signal CLKB output from the timing generator 3, the partial transfer address signal F (x, y) output from the AND circuit 9, and A signal f that receives a frame memory start address signal S (x, y) input from the outside and is input to one input end of a multiplexer (MUX) 1 arranged in a subsequent stage.
(Xa, ya) is generated. The multiplexer 1 outputs the output signal f of the FM address generation counter 2.
(Xa, ya) or the address signal CA transferred from the CPU address bus, and the address signal F (x
a, ya), and outputs to the frame memory 10.

Further, the logical product circuit 8 receives the partial transfer address signal F (x, y) which is the output of the logical product circuit 9, the partial transfer start signal TRFGO and the write signal WE which are respectively input from the outside, and the display memory 11 As opposed to
The write signal ▲ ▼ is output.

The negative logical product circuit 12 inputs the horizontal blanking signal ▲ ▼ and the vertical blanking signal ▲ ▼ output from the timing generator 3, and outputs a count enable signal HVBLK to the DM address generation counter 5. The DM address generation counter 5 receives the count enable signal HVBLK output from the negative AND circuit 12, the signal CLKB output from the timing generator 1, and the address signal D (input to the display memory 11). xa, y
a) is generated.

Then, a structure is provided for performing pseudo-color coloring based on the image data read from the display memory 11. That is, first, the first color conversion table memory CT0 having the red area R0, the green area G0, and the blue area B0 and the red area R
A second color conversion table memory CT1 including 1, a green area G1 and a blue area B1 is connected to the display memory 11.

Data can be arbitrarily read and written from the outside in each area, and a color conversion table memory for coloring image data individually written based on external settings and read from the previous display memory is configured. To do. For example, data externally written via the address bus CA and the data bus CD by an operator's operation is a synchronizing signal H for display.
The image data Dd read from the display memory 11 using D, VD, ▲ ▼, ▲ ▼, and CLKB as basic signals are used as the address signals of the color conversion table memories CT0 and CT1 in the red area R.
0, green area G0, blue area B0, red area R1, green area G1, and blue area B1 are read independently. Then, a red selecting means (RSEL) 1 for selecting and outputting the output from each area of both color conversion table memories CT0 and CT1 for a predetermined area for each of red, green and blue.
9, green selecting means (GSEL) 20, and blue selecting means (BSEL) 21 are provided. Each selection means 19, 20, 21 outputs an output pair (RD) for each color from the first and second color conversion table memories CT0, CT1.
d ₀ , R-Dd ₁ ), (G-Dd ₀ , G-Dd ₁ ),
It has a function of selecting one from two types of (B-Dd ₀ , B-Dd ₁ ). Each of the selection means 19, 20, 2
The operation control unit 1 is controlled by the inputs to the selection control signal terminals S ₀ and S ₁ , and the selection control unit 3 sets and controls the conditions of the selection output from each selection unit 19, 20 and 21.
0 is provided. For example, this is a main control unit 31 that outputs a control signal C (X, Y) by an external setting.
And a timing generator 25 which inputs C (X, Y) and outputs C (X), C (Y) which are the input signals of the selection control signals S ₀ , S ₁ .

C which is an input signal of the selection control signal terminals S ₀ and S _1.
(X) and C (Y) are 1-bit signals, and the input terminal pairs (Ri1, Ri2), (Gi1, Gi2), (Bi1,) of the selection means 19, 20, 21 are selected according to the selection conditions described later.
Bi2) input signal pair (R-Dd ₀ , R-
Dd ₁ ), (G-Dd ₀ , G-Dd ₁ ), (B-D
Either one of left and right is selected and output from d ₀ , B-Dd ₁ ). Here, the selection conditions are C (X) and C (Y).
In the case of = 1, the effective output signals from the respective selection means 19, 20, 21 are R-Dd ₁ , G-Dd ₁ , B-Dd _1, and C
When (X) · C (Y) = 0, R-Dd ₀ , G-Dd
₀ and B-Dd ₀ are valid signals. The timing generator 25 uses the display synchronization signals CLKA, H.
D, VD, and ▲ ▼ ▲ ▼ are used as basic clocks, and C is set under the condition externally set by C (X) and C (Y).
It has a function of outputting (X) and C (Y). The red RD / A conversion means 22 is provided after the red selection means 19, the green GD / A conversion means 23 is provided after the green selection means 20, and the blue selection means 21 is provided after the green selection means 20. Is connected to a blue BD / A conversion means 24, and is configured to display an image on a display means (color display) not shown.

Next, the operation of the device configured as described above will be described. The image data transferred from the display memory 11 to each of the color conversion table memories CT0 and CT1 is subjected to image processing such as window processing and filter processing as in the conventional case and image processing. It goes without saying that it does not include other areas.

First, writing of image data to the frame memory 10 will be described. When image data is written in the frame memory 10, the multiplexer 1 validates the address signal CA transferred from the CPU address bus and transfers the address signal CA to the frame memory 10. Therefore, the frame memory 10 receives the address signal CA and the write signal (for example, output from the CPU) CW,
The image data transferred from the CPU is written in the memory.

In addition, f input to the timing generator 4
(X, y) is an area (partial transfer size) preset by, for example, a trackball or a joystick as preprocessing, and is input via, for example, a CPU (not shown).

Next, the address signal F (xa, ya) of the frame memory will be described. This address signal F (xa, ya) is output by the multiplexer 1 from the output f of the FM address generation counter 2.
This is the output signal when (xa, ya) is valid. That is, the outputs F (x), F of the timing generator 4
The output f (xa, ya) of the FM address generation counter 2 which uses the logical product F (x, y) of (y) as a load signal and the start address signal S (x, y) input from the outside as a load input signal. By this, the contents of the frame memory 10 are read out. In this way the frame memory 1
The n _0- bit image data Fd read from ₀ is passed through the multiplexer 16 and n ₁ by the data conversion means 7.
After being converted into bit image data Cd, it is input to the display memory 11. The table of the data conversion memory 7 stores data CD (e.g., CP) when the CPU address CA previously input from the CPU (not shown) via the multiplexer 13 is validated as an address input.
Output from U) and write signal CW
The various tables transferred from are written.

The data writing to the display memory 11 is performed when the output () of the AND circuit 8 is in the enabled state. Further, the write / read address of the display memory 11 is the output CLK of the timing generator 3.
B, and the negative logical product H of ▲ ▼ and ▲ ▼ which are blanking signals in the horizontal and vertical directions, respectively.
DM with VBLK (output of negative AND circuit 12) as input
It is designated by the output D (xa, ya) of the address generation counter 5. This D (xa, ya) starts from (0, 0), for example, and then (1, 0) (2, 0) ... (X, 0) (0,
1) (1,1) (2,1) (3,1) ... (0, Y)
(1, Y) (2, Y) ... (X, Y) (0, 0) (1,
0) are output in this order and are signals synchronized with HD and VD, which are horizontal and vertical synchronization signals of the display means (not shown), respectively. Then, the signal Dd read from the display memory 11 by D (xa, ya) is transferred to both the color conversion table memories CT0 and CT1.

In this way, the memory control means 15 makes the frame memory 10
By controlling the operation of the display memory 11 and only the image data of a specific portion of the frame memory 10 can be transferred to the display memory 11 (partial transfer). The partial transfer in this apparatus will be described below.

For example, when transferring only the shaded portion of the frame memory 10, the start address (fx, fy) is changed to S (x, fy).
y) is input to the FM address generation counter 2, and the partial transfer matrix sizes x and y are f (x, y).
Is input to the generator 4. The generator 4 to which f (x, y) is input outputs the partial transfer address signals F (x) and F (y) (FIG. 3) synchronized with HD and VD. Then, the DM address generation counter 5 receives CLKB
Is input, the address D of the display memory 11
When (xa, ya) increases and indicates the address (dx, dy), F (x, y) enables the FM address generation counter 2 to count enable. Further, since the FM address generation counter 2 which is a synchronous load counter loads the start address S (x, y) of the frame memory 10 as fx and fy, it becomes count enable at the same time.
F (xa, ya) is in synchronization with the increase in the address of the display memory 11 and enters the address increment mode.
At this time, a logical product condition is satisfied for the logical product circuit 9 (the signal TRFGO inputting a partial transfer mode from the outside is
At this time, the level becomes “high”), and ▲ ▼ is enabled. Therefore, the display memory 11 is in the write mode.

Here, the operation timing in the partial transfer will be described with reference to FIGS. 2 to 5. In Fig. 2, F
(X) and F (y) are the partial transfer frame memory start address f set in the timing generator 4.
The partial transfer X address F (x) and Y address F (y) are synchronized from (x, y) to HD and VD. In addition, F (x,
y) is an output signal obtained by ANDing F (x) and F (y) in the AND circuit 9, and the y · H period of F (y) becomes a partial transfer time (address) in the vertical direction. . Further, the logical product of ▲ ▼ and ▲ ▼ which are the outputs of the timing generator 3 is HVBLK.

Further, when the partial transfer matrix is x and y, the horizontal transfer time address becomes Xt sec as shown in FIGS. 3 and 4, and the partial transfer address f (xa of the frame memory during this period of Xt sec. , Ya) is (fx, fy)
(Fx + 1, fy) ... (fx + x-2, fy) (fx + x-1, fy)
Then, it is incremented by the FM address generation counter 2 and ends at (fx, fy + 1), and the raster No (number)
As dy increases, it will increase by one address. At this time, the display memory address D
(Xa, ya) is (0, dy) (1, dy) ... (dx-1,) during the horizontal display time Xt sec of the display means (not shown).
dy) (dx, dy) (dx + 1, dy) ... (dx + x-2, dy)
It changes like (dx + x-1, dy) (dx + x, dy) ...
The display means (not shown) is used for display in x, y matrix size. Note that FIG. 5 shows the timing other than the area of the vertical direction partial transfer address (time) y · H shown in FIG. 2, and since F (y) = 0, F
The logical product F (x, y) of (x) and F (y) is “0”.

Therefore, F (x, F, which is the logical product of F (x) and F (y),
When y) is within the area of F (x, y) = H (that is, the partial transfer area), the logical product circuit 8 satisfies the logical product condition, ▲ ▼ is enabled, and the frame memory address (fx, fy) is set. The image data of is written in the address (dx, dy) of the display memory 11 via the data conversion memory 7. That is, the image gater of the frame memory 10 during the period when ▲ ▼ is enabled is
All are transferred to the display memory 11.

In this way, the partial transfer start address S (x, y) of the frame memory 10 is synchronized with the vertical synchronization signal VD and changed for each frame (one screen),
Data corresponding to a plurality of images stored (stored) in the frame memory 10 are sequentially output to the color conversion table memories CT0 and CT1 via the display memory 11. That is, different images color-converted in the predetermined area are sequentially displayed on the display unit (not shown).

On the other hand, the condition setting in the selection control means 30 is C (X) =
1, C (Y) = 1 timing only C (X) · C (Y)
= 1 and at this time, the second color conversion table memory CT1 side is selected. That is, as shown in the timing chart of FIG. 6, data (d
x, dy + y-1), (dx + 1, dy + y-1), ..., (d
Pixels up to x + x-1, dy + y-1) are involved in the conversion in the second color conversion table memory CT1.
When C (X) · C (Y) ≠ 1, the condition setting for selecting the first color conversion table memory CT0 side is made. That is, at this time, as shown in the timing chart of FIG. 7, data (dx, dy +
y), (dx + 1, dy + y), ..., (dx + x + 1, dy)
Pixels up to the first color conversion table memory CT0
Will be involved in. And by the above conditions C
For (X, Y), the range where C (X) · C (Y) = 1 is set on the display memory 11 at the start address (d
x, dy) [X size x, Y size y]. Therefore, C (X) · C (Y) = 1 and C
Two conditions of (X) · C (Y) = 0 are selectively supplied via the timing generator 25 to the selection means 19 and 2 described above.
The selection operation is performed by inputting 0, 21. That is, for example, the output of the color conversion table memory CT0 is selected in a predetermined area transferred from the display memory 11 to the color conversion table memories CT0 and CT1 and subjected to the image processing of the image data, and the color conversion table is selected in other areas. The output of the memory CT1 is selected. Therefore, it is possible to display the predetermined area subjected to the image processing and the other area in different colors on the display unit (not shown).

Further, two or more hatched portions shown on the display memory 11 may be present on one image display (X, Y),
The timing chart at that time is as shown in FIG.

In the above embodiment, the image displayed on the display device is
The two color conversion table memories can be selectively used according to the conditions set from the outside and can be displayed simultaneously. Further, a scanogram in an X-ray CT apparatus or the like has a moving portion (for example, heart) and a non-moving portion (for example, background such as bone), and only this moving portion is included in the frame memory 1
By reading from 0 (that is, partial transfer), the used capacity of the frame memory 10 can be reduced, and the display image can be switched at high speed on the display means (not shown), so that the cine display is easy. Can be done.

The above embodiment is an example, and various modifications can be made within the scope of the gist of the present invention.

In the above embodiment (timing charts shown in FIGS. 2 to 5), the transfer of the image data from the frame memory 10 to the display memory 11 is completed during one frame (between VD and VD). Even if scanning lines are skipped as in the interlace mode, partial transfer is possible. For example, as shown in the timing chart of FIG. 9, one frame may be transferred twice in the even field and the odd field. Since the interlaced scanning is performed, the increase in the vertical direction of each of the FM address generation counter 2 and the DM address generation counter 5 is different from that in the above embodiment (the increase in the horizontal direction is the same).

Further, in the timing chart shown in FIG. 3, even fields and odd fields are alternately transferred for each pixel unit, and in the even fields, F (xa, ya) transfers only even address signals, and in the odd fields. May transfer only F (xa, ya) odd address information. The configuration of the changed portion in this case is shown in FIG.

As shown in FIG. 10, the logical product of the output FSEL of the timing generator 3 and WE, TRFG0 and F (x, y) is obtained by the logic seat circuits 13 and 14, respectively, so that the even memory section of the display memory 11 can be obtained. (EME
M) 11a and the odd-numbered memory unit (OMEM) 11b are switched. That is, the output of the AND circuit 13 (ODWE) causes an odd field, and the AND circuit 1
The output of 4 (EDWE) enables the even fields respectively. At this time, the FM address generation counter 2 is also switched between the even address and the odd address by FSEL. Even with this configuration,
Partial transfer in interlaced scanning is possible.

Further, the partial transfer according to the present invention is not limited to the cine display, and is, for example, an arbitrary size x, y (however, X
≧ x, Y ≧ y), partial transfer of image data of sizes x and y from arbitrary start positions dx and dy of the display memory 11 allows simultaneous display of different images stored in the frame memory 10. It is possible.

Further, in the above-mentioned embodiment, two color conversion table memories are switched and used, but the constitution shown in FIG. 11 in which three or more color conversion table memories are provided and switched and used may be adopted. That is, the number of color conversion table memories CT (0,0), CT (1,
0), ..., CT (M, N) are provided, and one output signal can be selected from (M + 1) × (N + 1) input signals as shown in FIG. A signal C for selecting any one of (M + 1) × (N + 1) color conversion table memories is provided with a means 40, a green selection / selection means 41 and a blue selection means 42.
(X), C (Y) can be output, and Ci (X), Cj
(Y) = 0, Ci (X) · Cj (Y) = 1 (where i =
1, 2, ..., (M + 1), j = 1, 2, ..., N + 1)}
A timing generator 45 is provided to set the condition that becomes from C (X, Y). With such a configuration, the divided area M shown on the display memory 11
Coloring of CT (0,0), ..., MCT (M, N) Ci
By designating the conditions (X), Cj (Y), the color conversion table memory CT (0,0), ..., CT
The display can be switched by selecting (M, N). Therefore, according to this configuration, a plurality of types of images displayed in one image are colored differently and displayed in color. be able to.

[Effects of the Invention] As is clear from the above description, in the image display device of the present invention, color conversion is performed for a predetermined area, and for other areas where image processing is not performed, the area is colored. It is possible to display the predetermined area and other areas differently at the same time, and to contribute to the improvement of the diagnostic efficiency by coloring the predetermined area with respect to the conventional contrast image only in the brightness difference direction, for example, the gray level direction. It has the effect of being able to.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing the configuration of an image display apparatus according to an embodiment of the present invention, FIGS. 2 to 7 are timing charts for explaining the operation timing of the apparatus shown in FIG. 1, and FIG. FIG. 9 and FIG. 9 are timing charts for explaining a modification of the present invention, and FIGS. 10 and 11 are configuration block diagrams showing another modification of the present invention. 7 ... Data conversion memory, 10 ... Frame memory, 11 ... Display memory, 15 ... Memory control means, 19 ... Red selection means, 20 ... Green selection means, 21 ... Blue selection means, 30 ... Selection control means, 40 ... Red selection means, 41 ... Green selection means, 42 ... Blue selection means, CT0, CT1 ... Color conversion table memory, CT (0, 0) ,. CT (M, N) ... Color conversion table memory

Claims (1)

[Claims] 1. An image display device, wherein at least one predetermined area of image data is subjected to image processing and other areas are not subjected to image processing and is displayed together with the predetermined area,
A frame memory that stores image data including a predetermined area that has undergone image processing, a data conversion memory that converts the image data read from the frame memory, and a display memory that stores the image data transferred from the data conversion memory. A plurality of color conversion table memories each having a red area, a green area, and a blue area for inputting image data transferred from the display memory and coloring the image data based on an external setting, and each color conversion table From the red area, the green area, and the blue area of the memory, a selection means for red, a selection means for green, and a selection means for blue for selecting and outputting a predetermined one for each of red, green, and blue, and from the selection means Set the conditions for the selective output of Controlling the selection control means, and simultaneously based on the output from each selection-controlled selection means, the predetermined area subjected to color conversion and the other area subjected to color conversion different from the predetermined area at the same time. An image display device comprising display means for displaying.