JPH0656699B2 - Modulation circuit of digital signal recorder - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulation circuit of a digital signal recording device for recording a digital signal by dividing it into frame units, and more particularly to a frame synchronization signal adding circuit thereof.

[Conventional technology]

FIG. 3 shows, for example, a channel code in a fixed head PCM tape recorder "(American Society of Audio Engineers 7
4th Convention October 1983) "(AES, 74th convention, 198
3, oct, Channel coding for a Stationary Head PCM Tap
e Recoder ") is a circuit diagram of a conventional frame synchronization signal adding circuit, in which 1 is a modulator, 2 is a selector, 3 is a frame synchronization signal generator, and 4 is a shift register.

FIG. 4 is a diagram showing a state of a frame synchronization signal pattern generated in the circuit shown in FIG. 3, in which 5 is an original data string and 6 is a modulated data string.

Normally, when a digital signal is recorded on a recording medium such as a magnetic disk or magnetic tape, the signal format is a frame composed of a frame synchronization signal, data, and a code for detecting an error in a data string in frame synchronization signal units. It is composed of units, and these signal trains are often digitally modulated and then recorded as a means for achieving high density recording.

When the signal recorded under the above conditions is reproduced, the frame synchronizing signal is used as a bit synchronizing signal for demodulating reproduced data, a reset signal for error detection, etc., and is an extremely important signal. For this reason, it is desirable to use a special pattern that is unlikely to occur in the data as the frame synchronization signal, and the hardware size used for detecting the synchronization signal needs to be small, so that the processing should be simple.

The conventional frame synchronization signal adding circuit shown in FIG.
It is applied to the modulation method called WM,
The operation will be described with reference to the drawings.

As shown in FIG. 4, the binary mode original data a is obtained by converting one data bit at a rate of 2 bits by the modulator 1. At that time, it is divided into 2 bits or 3 bits. Converted to 4-bit or 6-bit code. The conversion table is shown in Table 1.

Y: “1” only when the first bit of the next codeword is “0” As can be understood from Table 1, the converted code is
A minimum of two "0" s and a maximum of seven "0s" are continuously inserted between "1" and "1". Furthermore, the adjacent probability of 0 run length is shown in Table 2. The numerical values shown in Table 2 are the number of appearances.

It can be understood from Table 2 that there is no pattern of 7 after pattern of 0 run length 4 in normal modulation data. Here, as described above, since it is desirable to use a special pattern that does not occur in the data as the frame synchronization signal, a pattern in which the 0 run lengths 4 and 7 are adjacent to each other is used as the frame synchronization signal. This pattern is "100001
It is represented by 00000001 "and corresponds to 7 bits as original data.

On the other hand, in this modulation method, as described above, the 0 run length guarantees a minimum of 2, and therefore the first run length is
To satisfy both the data area based on the conversion table of the table and the special pattern, a dummy bit of "1" shown in FIG. 4 is provided in the head bit of the frame synchronization signal area of the original data, and It is necessary to provide a 2-bit signal "00" at the end of the converted frame synchronization signal area. That is, "001000" is used as the frame synchronization signal.
A conversion pattern of 010000000100 ″ is used. At this time, the states (1), (2), and (3) shown in FIG. 4 can be considered in relation to the data at the end of the data area. Since the conversion pattern is used, 0 run length 2 is guaranteed in each of these states.

Next, a means for obtaining such a pattern will be described.

The original data string a input to the modulator 1 is provided with a frame synchronization signal area of at least 9 bits for each frame unit. At this time, as the original data pattern of the frame synchronization signal, a pattern in which the first bit is “1” and the conversion section is completed by the last bit, that is, a pattern that does not change the data in the data area is provided. These original data are sequentially input to the modulator 1 by the data clock b, and normal conversion data are output from the modulator 1 by the channel clock c having a frequency twice that of the data clock b and input to one of the selectors 2. It On the other hand, the special pattern as described above is generated by the frame synchronization signal generator 3 and input to the other side of the selector 2. Both of these signals are switched by a frame synchronization control signal d that divides the original data sequence into frames and has a frame synchronization signal area. It should be noted that this signal d needs to be bit-shifted by the shift register 4 as much as the converted data is bit-shifted by the modulator 1.

By the above means, the modulated signal e is output from the selector 2 using the special pattern that does not occur in the data as the frame synchronization signal.

[Problems to be solved by the invention]

Since the conventional frame synchronization signal adding circuit is configured as described above, the frame synchronization signal length is as long as 9 bits at the shortest. Further, since the frame synchronization signal generator 3 is provided in parallel with the main flow, an 18-bit data generator is required, which causes a problem that the circuit scale becomes large.

The present invention has been made in order to solve the above problems, and a modulation circuit of a digital signal recording device which can be configured with a frame synchronization signal length of an input signal of 8 bits and which can greatly reduce the circuit scale. The purpose is to get.

[Means for solving problems]

The modulation circuit of the digital signal recording device according to the present invention,
Digital modulation means for converting the original data into a channel code based on the conversion table shown in Table 3, and after performing conversion based on the third table, the channel code is subjected to secondary conversion processing in a serial state to perform frame synchronization. A frame synchronization signal generating means for generating a signal is provided so that a signal sequence that does not occur in normal conversion is obtained as a frame synchronization signal.

[Action]

In the present invention, the modulation method shown in Table 3 allows
The minimum run length is 2 and the maximum is 7, and the probability of occurrence of adjacent 0 run lengths is as shown in Table 4, and the pattern of 2 is adjacent to the pattern of 0 run length is 7 Therefore, as a special pattern that does not occur in the data used for the frame synchronization signal, "100
It is possible to use a relatively short pattern such as 000001001 ″, and the circuit for generating this pattern becomes small.

However, (1) D ₁ and D ₂ are ₁ , ₂ after the original data D ₀ to be converted.
Bit data (2) D _A is before D ₀ 1 bit data (3) M _A , M _B , M _C are before converted codes M ₀ , M ₁ 1,
Second and third bit data (4) Is “0”, ○ is “1”, for example Indicates that the data of D ₁ is “0” and M _B is the data of M _B is “1”.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, 7 is a first shift register for serial / parallel conversion of input data, 8 is a logic circuit for converting 1-bit data into 2-bit code according to Table 3 from the parallel data, and 9 is a parallel 2 converted. Second shift register for converting bitch code to serial, 10
Is a third shift register serving as a register for feeding back the converted code to the logic 8, and the input data is converted by the first, second, third shift registers 7, 9, 10 and the logic circuit 8. Digital modulating means for modulating is constructed based on Table 3. Reference numeral 11 is a flip-flop for generating a window for adding a frame synchronization signal, and 12 is a first flip-flop for generating the window.
, 13 is a second gate for generating a special pattern which does not occur in the data in the frame synchronization signal area by the output of the first gate 12, and the flip-flop 11 and the first and second gates. By 12, 13,
A frame synchronization signal generation unit is configured to generate a frame synchronization signal by secondarily converting the data that has been primarily converted by the digital modulation unit.

FIG. 2 shows the operation timing of each part of the circuit shown in FIG. 1. The operation will be described below with reference to FIG.

First, the data string f input to the first shift register 7 is shifted to the right by one data bit by the data clock g and converted into parallel data of 4 bits.
This input data string f contains a frame synchronization signal (hereinafter SY
A SYNC area is provided by an additional signal, and the data in this SYNC area is "0111000".
The pattern is 0 "(see FIG. 2 (f)).

The 4-bit parallel data is input to the logic circuit 8 in order to convert the data i of D ₀ output from the Q ₂ output of the first shift register 7 into a 2-bit code according to Table 3. . Further to this logic circuit 8 is inputted previously converted code is 3 bits _{(M A, M B, M} C) is fed back. The logic circuit 8 converts D ₀ into a 2-bit code of M ₀ and M ₁ based on these 7-input data based on the following logical expression, and outputs the 2-bit code to the second shift register 9.

It should be noted here that the converted code string of the SYNC area is not affected by the data adjacent before and after the area,
The point is that the pattern is fixed to "00100000100100100". Since this uses a pattern of "011 ..." From the first bit as the original data string of the SYNC area, the conversion code for the first "0" is always "0".
This is because “0” is used and “000” is used for the last 3 bits so that the last bit “0” is converted into a code of “00”.

The 2-bit code converted in this way is loaded into the second shift register 9 by the load pulse j every data clock g, and converted into serial data 1 by the channel clock k having a frequency twice that of the data clock g. Is output. The output data string 1 is input to the third shift register 10 in order to feed back a part of the information to the logic circuit 8.

The description so far is until the original data string f having the SYNC area undergoes normal modulation in accordance with Table 3, and shows the primary conversion.

The probability of occurrence of 0 run length of the modulated data in this state is as shown in Table 4, with the minimum being 2 and the maximum being 7. Further, as the adjacent pattern, the pattern of 0 run length is 7 and the pattern of 2 does not follow.

Therefore, as the special pattern that does not occur in the data due to the secondary conversion, as described above, a pattern in which 0 run length is 7 followed by 2 may be provided in the SYNC area.

The secondary conversion will be described below.

The pattern of the SYNC area obtained by the primary conversion is "00100000100100100" as described above. To generate a special pattern that does not occur in data as SYNC from the above pattern, use 8 in the SYNC area.
It is obvious that this can be obtained by setting the channel bit "1" to "0".

Specifically, it is achieved by the following means. First, the modulated data 1 obtained by the primary conversion is output as the data m from the Q ₂ output of the third shift register 10. As shown in FIG. 2, the timing of the output data m is 9 channel bits behind the original data string f. On the other hand, the SYNC additional signal h in the original data
And a signal obtained by delaying it by one data bit by the flip-flop 11 are input to the first gate 12, and a window n for removing "1" in the SYNC region is provided. By inputting the data m and the window n thus obtained to the second gate 13, the 8th bit of the SYNC area becomes "0", and the SYNC pattern becomes "0010".
000000100100 "is obtained and output as the modulation output o.

By the above means, the SYNC pattern becomes a special pattern that does not exist in the data, and a frame synchronization signal having a minimum 0 run length of 2 and a maximum of 7 as a recording signal without degrading the modulation characteristic can be obtained.

As described above, in the present embodiment, since the digital modulation is performed using the conversion algorithm shown in Table 3, the frame synchronization signal in the input signal can have a length of 8 bits. Further, since the modulated frame synchronization signal is generated by performing the secondary conversion processing on the primary conversion data obtained by normal modulation, the conventional frame synchronization signal generator is not required and the circuit scale is reduced. can do.

In the above embodiment, the data in the SYNC area is “0111”.
Although it was described as "0000", this is "0111100.
Even with the original data of "0", the frame synchronization signal of the same pattern as above can be obtained by setting "0" to "0" at the 7th channel bit of the SYNC area after the primary conversion, and the same effect as the above embodiment. Play.

〔The invention's effect〕

As described above, according to the present invention, since the conversion algorithm shown in the S ₁ conversion table is used as the digital modulation method, the special pattern which does not occur in the data as the frame synchronization signal in the input signal is set to the 8-bit length. Can be realized by
Further, since the special pattern is obtained by performing the secondary conversion processing on the primary conversion data normally obtained by modulation, there is an effect that the circuit scale can be reduced as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a modulation circuit of a digital signal recording device according to an embodiment of the present invention, FIG. 2 is a timing chart diagram of the circuit, and FIG. 3 is a circuit diagram of a modulation circuit of a conventional digital signal recording device. FIG. 4 is a diagram showing a state of a frame synchronization signal pattern generated in the conventional circuit. 7 ... 1st shift register, 8 ... Logic circuit, 9 ... 2nd shift register, 10 ... 3rd shift register, 1
1 ... Flip-flop, 12 ... 1st gate, 13 ... 2nd gate.

Claims (2)

[Claims] 1. A modulation circuit of a digital signal recording device for continuously modulating and recording an input digital signal for each frame signal unit including a frame synchronization signal and data and in a time series, wherein the input signal 1 bit of the data is converted into a 2-bit code on the basis of the following S1 conversion table, and data in the frame synchronizing signal area of the input signal is modulated by the digital modulating means to obtain a frame synchronizing signal. As "001000000010010
A modulation circuit for a digital signal recording apparatus, comprising: a frame synchronization signal generating means for obtaining a code string having a 16-channel bit length of 0 ". 2. The data in the frame synchronization signal area of the input signal is "01110000" or "0111100".
0 ", and the digital modulation means sets A and B in the S1 conversion table to A = 0 and B = 1 based on the following S1 conversion table.
The data in the frame synchronization signal area of the input signal is "00100000100100100" or "0".
01000100100100 "is subjected to a primary conversion into a code string, and the frame synchronization signal generating means" 00100000001001 "converts the primary converted data into" 00100000001001 ".
A modulation circuit for a digital signal recording apparatus according to claim 1, wherein the modulation circuit is secondarily converted into a frame synchronization signal of "00".