KR0148177B1 - 25/24 decoding method and apparatus of d-vcr data - Google Patents

Abstract

The present invention provides an S / P conversion unit for converting reproduced serial data into parallel data in units of 25 bits so as to efficiently demodulate D-VCR data modulated by a 2T-precoder encoding method; A parallel decoding unit for simultaneously decoding 25-bit data and removing additional bits; "D-VCR" includes a P / S conversion section for P / S conversion of 24-bit data from which additional bits have been removed, and in particular, the parallel decoding section includes a characteristic configuration for enabling simultaneous demodulation of 25 bits of data. 25/24 demodulation method and apparatus therefor ”.

Description

25/24 demodulation method and apparatus thereof for D-VCR data

1 is a block diagram of a 2T-precoder encoding unit of a D-VCR.

2 is a block diagram of a decoding unit of a 2T precoder, which is a demodulation device for D-VCR data according to the prior art.

3 is a block diagram of a "25/24 demodulation device for D-VCR data" according to the present invention.

4 is a detailed configuration diagram of a parallel decoding unit of the " 25/24 demodulation device for D-VCR data "

* Explanation of symbols for main parts of the drawings

10,52: XOR gate 20: delay unit

30: regeneration amplifier 40: S / P conversion unit

50: parallel decoding unit 60: P / S conversion unit

51: first latch portion 53: second latch portion

The present invention relates to a 25/24 demodulation method and apparatus thereof for modulating D-VCR data modulated by a 2T-precoder encoding scheme. In particular, the present invention relates to a large amount of digital data, including a parallel decoding unit for simultaneously decoding 25-bit parallel data. The present invention relates to a "25/24 demodulation method and apparatus therefor" for efficiently demodulating data.

With the development of semiconductor technology, digital signal processing is possible not only for sound signals but also for wide bandwidth video signals. As recording media and recording technologies are improved, the appearance of home VCRs by digital signal processing becomes possible.

According to the format of the D-VCR, error correction coding and channel modulation are performed to reduce the occurrence of an error before recording the data of the video signal or the audio signal on the tape.

There are many ways of channel modulation developed so far, but D-VCR uses 24/25 modulation.

According to the 24/25 modulation by the 2T-precoder encoding method, one bit is inserted into the upper bit of every 24 bits of the data that is error-corrected and coded, and converted into 25 bits. Outputs the modulated data. Serial data in the form of a modulated bitstream is recorded on a tape.

1 is a configuration diagram of a 2T-precoder encoding unit of a D-VCR.

As shown in FIG. 1, the encoding unit of the 2T precoder is composed of two delay units 20 and an XOR gate 10 for delaying data. The data input to the XOR gate 10 is compared with the data fed back by the two delay units 20 located at the output terminal of the XOR gate 10 and output.

Since there is no data fed back from the output for the first bit of data (D1, hereinafter referred to as the data of the Nth bit) and D2, an initial value (D−) is set for each delay unit 20 for D1 and D2. 1, D-2), and D1 is compared with D-2 and D2 with D-1, respectively.

The data of more than D3 is compared with the data two bits earlier in the XOR gate 10.

That is, odd-numbered data is compared with odd-numbered data (D3-D1, D5-D3, D7-D5, D9-D7, D11-D9, ………, D25-D23), and even-numbered data is compared with even-numbered data. (For example, D4-D2, D6-D4, D8-D6, D10-D8, ………, D24-D22).

On the other hand, consecutive serial data D26 is the first bit of data (D'1) of the next 25 bits of data, which is compared with D24, and D27 is the second bit of data (D'2) of the next 25 bits of data, which is different from D25. Compare and print.

FIG. 2 is a 2T demodulation apparatus for D-VCR data according to the prior art which demodulates data which is modulated and recorded on tape by the 2T-precoder encoding unit of D-VCR of FIG. It is a block diagram of the decoding part of a precoder.

As shown in FIG. 2, the decoding unit of the conventional 2T precoder has two delay units 20 located at the input unit as opposed to the encoding unit of the 2T precoder shown in FIG. In the opposite operation to that in the encoding section, the input data is delayed by the two delay sections 20 and compared with the data two bits later to output the demodulated serial data.

That is, the input data is delayed by the delay unit 20, and each data is compared with the 2 bit previous data at the XOR gate 10 and output. Even during decoding, an initial value should be set in the delay unit 20 for comparison between D1 and D2. The initial values D-1 and D-2 should be the same as in encoding.

However, according to the conventional 2T-precoder decoding method as shown in FIG. 2, since it decodes and demodulates the bitstream type serial data by one bit, it takes time to compare the data of each bit. In addition, there is an inconvenience in that an additional bit added during 24/25 modulation must be separately removed from the decoded data. In particular, the 2T-precoder decoding method according to the prior art is a problem when the amount of data is huge.

In order to solve the problems of the conventional decoding method, the present invention efficiently decodes parallel data in units of 25 bits and removes additional bits added during 24/25 modulation from decoded 25 bit data. An object of the present invention is to provide a "25/24 demodulation method and apparatus thereof for D-VCR data".

Hereinafter, the "25/24 demodulation apparatus of D-VCR data" by this invention is demonstrated in detail.

3 is a block diagram of a "25/24 demodulation device for D-VCR data" according to the present invention.

As shown in FIG. 3, the " 25/24 demodulation device for D-VCR data " according to the present invention includes: an S / P converter 40 for converting reproduced serial data into parallel data of 25 bits; A parallel decoding unit 50 for simultaneously decoding 25-bit data and removing additional bits; And a P / S conversion section 60 for P / S conversion of 24-bit data from which additional bits have been removed.

The reproduced data is amplified by the reproducing AMP 30, converted into 25 bits of parallel data by the S / P converter 40, and then 25 bits of data are simultaneously decoded and parallel decoded by the parallel decoding unit 50. When output from the section 50, the additional bits inserted during 24/25 modulation are removed. The P / S converter 60 outputs demodulated data by P / S converting the 24-bit data from which the additional bits have been removed.

In particular, in the apparatus according to the present invention, the parallel decoding unit 50 includes a characteristic configuration for enabling simultaneous demodulation of 25 bits of data.

4 is a detailed configuration diagram of the parallel decoding unit 50 in the 25/24 demodulator for D-VCR data according to the present invention of FIG.

The parallel decoding unit 50 includes a first latch unit 51 for synchronizing each 25-bit data to a clock and outputting the data to the XOR gate; Twenty-five XOR gates 52 for decoding each data compared to two bits of previous data; A second latch unit 53 is provided to remove the most significant bit of the decoded output and latch the remaining 24 bits.

The structure in which the 25 XOR gates 52 are arranged to decode 25 bits of data at the same time is connected to one input of two odd XOR gates to decode each data compared to data two bits earlier ( XOR1-XOR3, XOR3-XOR5, ……… XOR23-XOR25), and the inputs of two even-numbered XOR gates are connected (XOR2-XOR4, XOR4-XOR6 ……… XOR22-XOR24).

The 24th XOR gate (XOR24) is connected to one input of the first XOR gate, and the 25th XOR gate (XOR25) is connected to one input of the second XOR gate to continuously decode the next 25 bits of parallel data. It is.

By the 25 XOR gates described above, each data of 25 bits can be continuously compared to the data of 2 bits and outputted, and then decoded continuously for the next 25 bits of data. Therefore, according to the 2T-precoder encoding method. Modulated data can be decoded simultaneously in 25-bit units.

The operation of the parallel decoding section of FIG. 4 will be described.

When 25-bit S / P converted data is input, the first latch unit 51 outputs the data to the input unit of each XOR gate 52 in synchronization with a clock, and the 25 XOR gates 52 are as shown in FIG. By the same arrangement structure, decoded 25 bits of data are output for each data compared with 2 bits of previous data.

The decoded 25-bit data is removed from the most significant bit (additional bits added during 24/25 modulation) while passing through the second latch unit 53, and the remaining 24 bits of data are output to the P / S converter 60. Done.

As described above, according to the present invention "25/24 demodulation method and apparatus therefor", the data modulated by the 2T-precoder encoding scheme can be simultaneously decoded continuously in units of 25 bits. In addition, by removing the additional bits immediately after decoding, a large amount of data can be efficiently demodulated in a short time.

Claims (6)

CLAIMS 1. A method for demodulating D-VCR data modulated by a 2T-precoder encoding method, comprising: a first step of converting reproduced serial data into parallel data in units of 25 bits; A second step of simultaneously decoding the 25-bit parallel data and removing the most significant bit; A "25/24 demodulation method of D-VCR data" comprising the third step of converting decoded parallel data into serial data. The method of claim 1, wherein the second step comprises: outputting each data of 25 bits to an XOR gate in synchronization with a clock; Comparing and outputting each data and 2-bit previous data of each data in 25 XOR gates; And removing the most significant bit of the decoded output and synchronizing the remaining 24 bits with a clock to output the 25/24 demodulation method of the D-VCR data. The "25/24 demodulation method of D-VCR data" according to claim 1 or 2, wherein said second step is capable of continuously decoding continuous 25-bit parallel data. An apparatus for demodulating D-VCR data modulated by a 2T-precoder encoding method, comprising: an S / P converter for converting reproduced serial data into parallel data in units of 25 bits; A parallel decoding unit for simultaneously decoding the 25-bit parallel data and removing the most significant bit; And a P / S converter which converts the decoded parallel data in units of 24 bits into serial data. 25/24 demodulation device for D-VCR data. 5. The apparatus of claim 4, wherein the parallel decoding unit comprises: a first latch unit for outputting each of 25-bit input data to an XOR gate in synchronization with a clock; Twenty-five XOR gates for comparing and outputting each data and two-bit previous data of each data; And a second latch unit which removes the most significant bit of the decoded output and outputs the remaining 24 bits in synchronization with a clock, wherein the 25/24 demodulation device for D-VCR data is used. 6. The 25 XOR gates of claim 5, wherein one input terminal of two odd-numbered XOR gates is connected and one input terminal of two even-numbered XOR gates are connected. One input terminal is connected, and one input terminal of the 25th XOR gate and the second XOR gate are connected to decode the 25-bit data simultaneously and successively decode the subsequent 25-bit data. 25/24 demodulation device.