JPH065505B2 - Arithmetic circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an arithmetic circuit for digital signal processing, and more particularly to an arithmetic circuit of a signal processor that performs fixed point arithmetic.

(Prior art and its problems) The advantage of digital signal processing is that it can realize filters and modulators / demodulators with high accuracy or stability that cannot be realized by analog technology. A variable adaptive filter or the like can be easily realized. For more detailed advantages of digital signal processing, etc.
See pages 1280 to 1284 of the December issue.

Digital signal processing, which has many advantages as described above, is often inferior to analog technology in terms of hardware size and power consumption, and digital signal processing has come into practical use rapidly. Digital LS has evolved
It is only recently that I circuit is available,
Especially after the realization of a digital signal processing microprocessor called a signal processor.

Such a signal processor is required to have high-speed arithmetic operation capability because it is necessary to realize the differential and integral operations realized by analog circuits in the digital domain while reducing the hardware scale. Have made different developments. For more details, I will transfer from page 862 to page 869 of the July 1983 issue of the Information Processing Society of Japan, and describe the characteristics of the current signal processor.

In a signal processor, in order to realize high-speed arithmetic operation capability with a small hardware, numerical representation is in principle fixed-point notation and 2's complement representation is often used.
Also, the target handled by the signal processor is an A / D converted analog signal, and it is convenient to represent the digital expression based on the maximum allowable amplitude of the A / D converter, so the maximum amplitude value is set to 1.0. That is, when the position of the fixed point is indicated by the two's complement representation, the fixed point is placed between the most significant bit and the next bit, and it is treated as a numerical value from -1 to +1.

As the input / output format of the multiplication circuit when using such a format, it was published on pages 372 to 376 of IEEE Journal of Solid State Circuits SC-16 Vol. 4 (August 1981). As shown in Fig. 2 of the signal processor, the product between N-bit two's complement fixed-point data is obtained by 2N-1 bits,
Fixed-point positions typically still use a format that lies between the most significant bit and the next bit. For this reason,
If the upper N bits are taken out so that the multiplier output has the same format as the signal data, the dynamic range of the signal can be kept constant.

On the other hand, in calculations such as FIR filters, the input signal at time j,
If the output signals are x _j and y _j respectively, Is performed. The coefficient {a _i } determines the characteristics of the filter. If x _j is a value in the range of -1 to +1 then y _j is also an average value in the range of -1 to +1. The coefficient is set to. However, the value of the coefficient a _i is not always from -1
It is not limited to the range of +1 and, as a result, the intermediate calculation result of y _j often falls outside the range of -1 to +1.

In the method in the conventional method of implementing such a FIR filter, for the range of values of the coefficients {a _i} can be input to the multiplier from -1 to +1, each coefficient of the coefficient {a _i} Select a power of two that is larger than the maximum absolute value, and use the coefficient {b _i } divided by this value.

That is, b _i = a _i · 2 ^-k (2) and Eq. (1) is calculated as follows.

From Equation (3), y _j was obtained by multiplying b _i and x _ji , accumulating them, and multiplying them by 2k. When equation (3) is realized by fixed-point arithmetic, both b _i and x _ji are values from -1 to +1.
b _i x _ji takes a value from -1 to +1 and the fixed multiplier described above can be used. However, when b _i x _ji is added by N terms, the intermediate calculation result and the calculation result may not be in the range from -1 to +1. However, even in this case, in a signal processor that uses a single-precision adder, it is necessary to provide hardware that replaces the maximum value when an overflow occurs for each addition, or ignore the occurrence of such an overflow and use it as calculation noise. I used to treat.

Also, as long as the FIR filter is realized, such an overflow does not make the system unstable, but
In a system such as an IIR filter that uses feedback of calculation results, the problem of overflow leads to system instability, and even if the calculation speed is sacrificed, it is necessary to replace the value with the maximum value when overflow occurs.

As described above, in the calculation method according to the conventional technique, the overflow of the intermediate result of the calculation is ignored or the maximum value is replaced each time the overflow of 1 addition occurs. Even if the output signal y _j becomes a value within the range of +1 from the normal -1 if overflow is prevented, overflow will be ignored or overflowed if a small circuit is used. The maximum value of was frequently corrected, and the output value y _j often contained a large error.

(Object of the Invention) An object of the present invention is to provide an arithmetic circuit for a signal processor capable of improving the calculation accuracy of the output value y _j .

(Structure of the Invention) The present invention provides a fixed-point multiplier that inputs two sets of single-precision bit number data and outputs a product of double-precision bit numbers, and the fixed-point multiplier output is shifted by at least a plurality of bits in the lower direction. A double-precision bit number barrel shifter, a double-precision bit number ALU that performs arithmetic logic operation on the output of the barrel shifter and the contents of the register described later, and bit shift at least in the upper direction with respect to the output of the ALU. A double-precision bit number shifter, an overflow detection circuit that detects that output data has overflowed by the ALU or the shifter, and the overflow detection circuit is controlled by the overflow detection circuit. Of the overflow corrector that replaces the maximum value of It is composed at least of a double precision bit number register for storing and an output terminal of the register for outputting data of at least upper single precision bit number.

(Principle of the Present Invention) The principle of the present invention is that a fixed-point multiplier output has a double-precision bit length. Therefore, even if the double-precision bit-length multiplication result is bit-shifted in the lower direction together with the decimal point position, the shifted result is Even if it is represented by the number of bits before the shift, the precision of the data represented by the double precision bit length will not be insufficient even if the data is truncated by the bit shift.Because the decimal point position has been moved to the lower bit direction,
The dynamic range at the time of accumulation is significantly expanded from -1 to +1 compared to the conventional range. Since the accumulated result is in the conventional range of -1 to +1 on average, it is bit-hifted upward with the decimal point. By doing so, an accurate value is obtained. Hereinafter, this will be described in detail.

Now, in calculating equation (1), a _i and x _j are N
It is assumed that bits are represented in 2's complement as follows.

That is, a _i can range from -2 ^k to 2 ^k, but x
_It is assumed that _j is in the range from -1 to +1 as described above. At this time, the product term Z _i of equation (1) is Can be expressed as That is, for values a _i in the range from -2 ^k to 2 ^k-
Multiplying the value x _{j in} the range from 1 to +1 gives a value in the range from -2 ^k to 2 ^k , and is the product of N-bit number comrades.
The product is 2N-1 bits. In Expression (1), it is necessary to accumulate this term by M terms, and the maximum dynamic range log ₂ M bits may be expanded. Therefore, the smallest integer larger than log ₂ M is set as L, and the decimal point position is included. Then, the numerical value given by the equation (5) is shifted in the lower direction of L bits. In other words, 2N-1 bit data Z _{i in} which L bits Z _i are arranged in the lower direction in this way
^* Is the upper L bit, which is the sign bit of the polarity (matches Z _o ⁱ Then, an error for the lower L bits is generated.

Equation (1) can be calculated by adding this M _i term to Z _i ^* , Becomes Where y _j should be a number in the range of +1 to +1 on average, so in many cases Therefore, even if the upper k + L-1 bits are omitted, the same value is given as the two's complement representation. Therefore, 2 shown in (7)
If N-1 bit data is shifted by k + L-1 bits in the upper direction and the upper N bits are taken out from the data after the shift overflow, a dynamic range from -1 to +1 is obtained like x _j.
y _j will be obtained. If (8) Maximum expression is not in the range of y _j until -1 than +1 obtained when not satisfied, thus from normal y _j is not required, as the overflow in this case positive or negative The value should be y _j .
Since there is no fear of 2N-1 bit representation by the formula (7) is overflowed, to set the value of y _j the positive or negative maximum value is longer if you look at the ^{_{y 0 j, y 0 j =}} 0 In case of y, a positive overflow may be made, and in case of y ₀ ^j = 1, a negative overflow may be made.

If such a calculation is performed, there is a possibility that an error may be added to the output signal y _j because the lower L bits of the signal represented by 2N-1 bits at the time of moving from Expression (5) to Expression (6) are added M times. Only errors that occur or errors due to overflow. Lower L above
The error that occurs when the bit is added M times (corresponding to L bits) is 2L bits when evaluated by the same expression as Equation (5), and y _j
It is at most k + 3L-1 bits even when taking into consideration the shift of k + L-1 bits in the upper direction in outputting. Also, y _j
If the rounded down bit N-1 is larger than this k + 3L-1 to round to N bits as the output of, that is, N-1> K + 3L-1 (9), the above calculation result Dynamic for
The rounding error that occurs to extend the range is virtually invisible.

In the above explanation, when calculating the equation (1), the M term addition increases the dynamic range of the maximum L bits, and even when the maximum dynamic range occurs, the output signal is originally dealt with. The range of possible values of y _j is
Since it is set to +1 rather than -1, the dynamic range is expanded by L'bits smaller than L bits at the time of accumulation, and overflow may occur at the time of accumulation, but it is better than the conventional method. It is also possible to reduce the occurrence of overflow. By doing this,
The accuracy of the value of the expression (6) before the accumulation can be improved, and y _j can be calculated with high accuracy when there is no overflow at the time of accumulation. Therefore, it is desirable that the shift amount before input to the accumulator can be made variable so that it can be changed for each individual application.

(Example) Next, one example of the present invention will be described with reference to the drawings.
Figure 1 shows multiplier input terminal 1, multiplicand input terminal 2, registers 3, 4,
12, multiplier 5, barrel shifter 7, arithmetic logic unit (ALU) 8, shifter 9, overflow detector 10, overflow corrector 1
It is composed of 1, shift amount control terminals 6 and 13, and output terminal 14.
Registers 3, 4, and 12 are the "The Bipolar Digital Integrated Circuits Data Book (The Bipolar Digital Integrated Circuits) published by Texas Instruments in 1985.
gratedCircuitsDataBook) ”on page 7-234, and ALU can use the ICs described on pages 7-252 to 7-262. Multiplier 5 is a device catalog T issued by TRW in 1984.
The ones listed in MC2110 can be used. Barrel shifter 7
And the shifter 9 is "Schottky and Low Power Schottky Databook Inclusion Digital Signal Processing Handbook" issued by AMD in 1977.
(Schottky and Low-power Schottky Data Book Includi
ng Digital Sigual Processing Handbook) ”, pages 4-37 to 4-46 can be used. Overflow detector
Details of 10 and overflow 11 will be described later.

Assume that the register 12 is cleared to 0 for the calculation of the equation (1), a ₀ is input from the terminal 1 to x _j from the terminal 2, and each of a _o and x _j is the expression ( As given in 4). The a _i and x _j added to the terminal 1 and the terminal 2 are stored in the register 3 and the register 4, respectively. Multiplier 5 calculates the product of the contents of register 3 and register 4 as 2N-1 bits.
Give as in (5). In the barrel shifter 7, "L" is input from the terminal 6 in order to shift in the lower direction by an integer L including log ₂ M. Therefore, the output of the multiplier 5 shifts the 2N-1 bit data in the L-bit lower direction by the barrel shifter 7 to obtain Z _i ^* given by the equation (6) which is also expressed by 2N-1 bits. In the 2N-1 bit length ALU8, the output Z _i ^{* of the} barrel shifter 7 and the contents of the register 12, in this case, zero is added to output Z _i ^* . Naturally, no overflow occurs. The shifter 9 adds a shift amount control signal from the terminal 13 so as to shift k + L bits only when calculating the final output y _j of the formula (1). In the present case, the first term of the formula (1) is being calculated. Therefore, the shift amount 0 is applied from the terminal 13, and therefore the output Z _i ^* of the ALU 8 passes through the shifter 9 as it is. Naturally, the overflow by the shifter 9 does not occur. Since neither the ALU 8 nor the shifter 9 overflows, the overflow detector 10 informs the overflow corrector 11 of the occurrence of no overflow, so that the shifter 9
The output Z _j ^{* of} is the output of the overflow corrector 11 as it is. This 2N-1 bit output Z _j is stored in the register 12 to complete the first term calculation a _o x _j of the equation (1).

Then, a ₁ and x _j-1 are added to terminals 1 and 2 to register 3
And 4 store a ₁ , x _j-1 . The multiplier 5 calculates a ₁ x _j-1
It is given in the form of (5), and L is moved downward by the barrel shifter 7.
Bit shift. In ALU8, a ₀ stored in register 12
x _j and a ₁ x _j-1 which is the output of the barrel shifter 7 are added.
Also in this addition, since the barrel shifter 6 shifts the 2N-1 bit multiplier output downward by L bits, no overflow occurs. The output a ₀ x _j + a ₁ x _j-1 of the ALU8 is input to the shifter 9, but zero is also input to the terminal 13 this time,
The shifter 9 only transfers the input a ₀ x _j + a ₁ x _j-1 to the output. Therefore, the shifter 9 does not overflow.
Since neither the ALU 8 nor the shifter 9 causes an overflow, the overflow detector 10 informs the overflow corrector 11 of the occurrence of no overflow, so that the overflow corrector 11 only conveys the output of the shifter 9 to the register 12 this time. The register 12 holds the calculated value of a ₀ x _j + a ₁ x _j-1 . Hereafter, the same operation as the second time is repeated until the M-1th time.

Next, the M-th operation for calculating the formula (1) will be described.
A _M and x _jM are input to terminals 1 and 2, respectively, and stored in registers 3 and 4, respectively. Register 3
And the output of the register 4 is input to the multiplier 5, and a _M x _{j M} is output in the form of the equation (5). This a _M x _{j M} is shifted L bits downward by the barrel shifter 7, and then in ALU8 in register 12. Is added. Also in this case, since the barrel shifter 7 shifts the multiplication result a _M x _{j M} downward by L bits, AL
No overflow at U8. ALU8 as addition output Is output to the shifter 9. The shift amount applied to terminal 13 is k + L this time, Is shifted up by k + L bits and output. In this case, ALU8
Output Whether the overflow occurs or not depends on whether the upper bits of s satisfy Eq. (8). Now, consider the case where the equation (8) is satisfied and an overflow does not occur. In this case, the overflow detector 10 is the ALU 8 and the shifter 9
Since it has not overflowed, the overflow corrector 11 informs the overflow corrector 11 that the output of the shifter 9 bit-shifted y _j in the upper direction of k + L bits to the register 12. The upper N bits of the register 12 are transmitted to the output terminal 14, and the N-bit output y _j having a value in the range of -1 to +1 is obtained at the terminal 14. On the other hand, consider the case where the output of ALU8 does not satisfy equation (8) and overflows. In this case, the overflow detector 10 informs the overflow correction and the overflow occurrence direction (positive or negative) to the overflow corrector 11, and instead of the output of the shifter 9, the overflow corrector 11 is a positive or negative maximum value +1 or Transmit -1 to register 12. Therefore, +1 or -1 represented by N bits is obtained at the output terminal 14 that outputs the upper N bits of the register 12 according to the overflow direction. The above description is for the case where the value of M in equation (1) is small, and in this case, equation (9) is easily established. Therefore, the output y _j is given a correct value as long as it does not overflow in the final shift by the shifter 9, and the calculation accuracy is N bits.

On the other hand, when the value of M in equation (1) is large, equation (9) will not be established.
In this case, the downward shift amount applied to the terminal 6 is not L, but
If L'smaller than L and satisfying the formula (9) is given, the risk of overflow occurring during the calculation of the formula (1) is not 0, but the calculation accuracy can be kept high. However, in this case, it is obvious that the shift amount given to the terminal 13 is 0 from the first time to the M-1th time, which is the same as the previous example, but it is necessary to be k + L 'at the Mth time. There is. In the following case P
The case where ALU8 overflows for the second time will be described. Up to the P-th time, the same as the previous example, register 12
To Is stored.

At the P-th time, a _p , x is applied to registers 3 and 4 via terminals 1 and 2, respectively.
_jp is stored. Multiplier 5 is a _p , x _jp from registers 3 and 4
_Is input and the output a _p x _jp is output. A _p x _uk a register by barrel shifter 7 is L 'bit lower bit shifting
Stored in 12 Is added by ALU8, but it causes an overflow. Now if the overflow happens in the positive direction
The ALU output has a negative value. Shifter 9 is terminal 1 at the Pth time
Since 0 is input to 3, the overflow does not occur, and the overflow result output as a negative value in the ALU is supplied to the overflow corrector 11. The overflow detector 10 detects that the ALU has overflowed, and notifies the overflow corrector 11 that an overflow has occurred and that it is a positive side overflow. Therefore, the overflow corrector 11 ignores the negative output from the shifter 9 and transmits the positive maximum value to the register 12. Therefore, register 12 has the maximum positive value. The effect of ALU overflow is reduced.

FIG. 2 shows an embodiment of the overflow detector 10, and it is assumed that the input of the shifter 9 is 5 bits.
101,102,103,104 are shifter inputs Z ₀ ^* , Z ₁ ^* , Z ₂ ^* , Z ₃ ^* , Z
₄ ^* terminal, exclusive logical NOR gate 110,111,112,113, logical OR gate 120,121,122,123, AND gate 130,200, read only memory 150, shift bit number input terminal 7, overflow detection terminal 160, overflow direction terminal 170 inversion ALU overflow input terminal 190, ALU inversion top It is composed of a bit terminal 180 and a selection circuit 210. The read only memory 150 stores the data shown in Table 1 with the terminal 13 connected to the address. In other words, Table 1 is from terminal 13 A series of logical 0s continues from the most significant bit direction according to the shift amount (k + L) added. Since the ALU circuit already has a terminal for notifying the occurrence of overflow as described in the above-mentioned document and has a terminal for outputting the most significant bit separately, this is added to the terminals 190 and 180, respectively. As the selection circuit 210, the ICs described on pages 7-46 to 7-151 of the aforementioned Texas Instruments company document can be used.

Regarding the overflow of the ALU, since the overflow detection mechanism is inside the ALU as described above, the overflow detection of the shifter will be mainly described below, and finally the overflow of both the ALU and the shifter will be described.

Now, the 2-bit shift designation is input from terminal 13 and the ALU
Assuming that the output is 1,1,1,0,1, and is applied to each of the terminals 100,101,102,103,104, 1,1,0,0 are output to the gates 110,111,112,113, respectively. The output of the ROM at this time is 0,0,1,1 from Table 1, and the ROM output and the outputs of the gates 110,111,112,113 are ORed by the gates 120,121,122,123. Since the ROM output is 1 for the upper 2 bits or less to be compared, the outputs of the gates 120, 121, 122, 123 are all 1. For this reason,
The gate 130 outputs 1 and there was no overflow, in other words Z ₀ , Z ₁ , Z applied to the terminals 100, 101, 102.
₂ indicates that they have the same content.

On the other hand, the same 2-bit shift designation is input from terminal 13,
If the ALU output is added to each of the terminals 100, 101, 102, 103, 104 as 1,1,0,0,1, 1,0,1,0 is output to each of the gates 110,111,112,113. This results in gates 120, 121, 1
22,123 gives 1,0,1,1. Since the gate 121 outputs 0, the gate 130 outputs 0, indicating that an overflow occurs. At this time, the direction of overflow is terminal 100.
Since the most significant bit of the input of the shifter added from 1 is 1, it can be detected that the page-direction overflow occurs due to the 2-bit shift. The same applies to detection of overflow in the forward direction.

According to the following explanation, when the gate 130 is 0, the shifter overflows, and when the terminal 190 is 0, A
It can be seen that an LU overflow has occurred. Therefore, depending on the gate 200, if either one becomes 0, the terminal 1
Outputs 0 to 60 to indicate that an overflow has occurred. Since it is assumed that the ALU and the shifter do not overflow at the same time, when the gate 130 is zero, the shifter overflows. Therefore, when the gate 130 is 1, at least the polarity sign bit added to the terminal 100 is used. Since it is not an overflow, the inverted most significant bit output of the ALU is selected by the selection circuit 210 and output to the terminal 170.
When the ALU overflows, the most significant bit of the ALU is output because the polarity (most significant bit) is inverted due to the overflow.

FIG. 3 is a block diagram of the overflow corrector.
300, positive maximum value input terminal 301, negative maximum value input terminal 302,
It is composed of a shifter output input terminal 303, a correction output terminal 304, an overflow occurrence input terminal 160, and an overflow direction terminal 170. From the description of FIG. 2, the overflow detection signal output terminal 160 indicates an overflow when it is zero, and the overflow direction signal output terminal 170 indicates an overflow in the positive direction when it is 1 and the negative direction is 0. It can be used and connected as shown in Table 2.

When the connection is made in this way, overflow occurs, and in the case of positive direction overflow, the maximum positive value 011 ... 1 added to terminal 301 is generated, and when overflow occurs and negative direction overflow occurs, terminal 301 is added. 0, and the input signal applied to the terminal 303 is directly applied as the output of the selection circuit 300 when the overflow does not occur.

(Effect of the Invention) According to the present invention as described above, it is possible to realize a small fixed-point arithmetic circuit suitable for a signal processor or the like that accurately executes an arithmetic operation such as an FIR digital filter.

Further, according to the present invention, it is possible to provide a circuit capable of arbitrarily selecting the trade-off between the calculation accuracy and the overflow occurrence in the case where the dynamic range of the intermediate result becomes large even if the numerical calculation has the same input / output dynamic range.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a configuration example of an overflow detector, and FIG. 3 is a diagram showing a configuration example of an overflow corrector. In the figure, 1 ... Input terminal, 2 ... Other input terminal 3 ... Register, 4 ... Other register 5 ... Multiplier, 6 ... Lower shift amount input terminal 7 ... Barrel shifter, 8 ... Arithmetic logic unit 9 ... Shifter 10 ... Overflow Detector 11 ... Overflow corrector, 12 ... Register 13 ... Upward shift amount input terminal, 14 ... Output terminal.

Claims (1)

[Claims] 1. A fixed-point multiplier that inputs two sets of data of single-precision bit numbers and outputs a product of double-precision bit numbers, and a plurality of bits can be shifted in the lower direction by at least the output of the fixed-point multiplier. Double precision bit number barrel shifter,
An ALU having a double precision bit number for performing an arithmetic logic operation on the output of the barrel shifter and the contents of a register described later;
With respect to the output of LU, a shifter with a double-precision bit number that shifts the bit at least in the upper direction, an overflow detection circuit that detects that output data has overflowed by the ALU or the shifter, and the overflow detection circuit An overflow corrector which is controlled and replaces the shifter output with a maximum value in the overflow direction when an overflow is detected, a double-precision bit number register for storing the overflow corrector output, and at least an upper single-precision bit number data of the register. An arithmetic circuit characterized by comprising at least an output terminal for outputting the.