JPH0653824A - Phase locked loop oscillator - Google Patents

Phase locked loop oscillator

Info

Publication number
JPH0653824A
JPH0653824A JP4203501A JP20350192A JPH0653824A JP H0653824 A JPH0653824 A JP H0653824A JP 4203501 A JP4203501 A JP 4203501A JP 20350192 A JP20350192 A JP 20350192A JP H0653824 A JPH0653824 A JP H0653824A
Authority
JP
Japan
Prior art keywords
output
voltage
lpf
oscillator
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4203501A
Other languages
Japanese (ja)
Inventor
Eiichi Matsumura
鋭一 松村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4203501A priority Critical patent/JPH0653824A/en
Publication of JPH0653824A publication Critical patent/JPH0653824A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To shorten a lock-up time by quickly raising a low pass filter (LPF) by a comparator during a prescribed period after impressing power supply voltage, and separating the LPF after the lapse of the prescribed time. CONSTITUTION:A frequency divider 12 divides the frequency of an output from a variable voltage control type oscillator 11 and a reference signal generator 13 outputs a signal with reference frequency. A phase detector 14 detects a phase difference between an output signal from the frequency divider 12 and a reference signal from a reference signal generator 13 by mutually comparing both signals and generates an output corresponding to the phase difference. The LPF 15 converts the output of the detector 14 into DC control voltage by smoothing the output as control voltage for the oscillator 11. A comparator 16 compares the control voltage obtained from the LPF 15 with reference voltage VR1. When the voltage of a terminal 21 is lower than the reference voltage VR1, a capacitor in the LPF 15 is quickly charged through the comparator 16. After the lapse of the prescribed time, switches SW1, SW2 are switched.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、位相同期発振器に関
し、特に電源投入時のロックアップタイムを短縮した位
相同期発振器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked oscillator, and more particularly to a phase-locked oscillator with a short lock-up time at power-on.

【0002】[0002]

【従来の技術】従来の位相同期発振器は、可変電圧制御
型発振器と、その出力を分周する分周器と、基準となる
周波数の信号を出力する基準信号発生器と、分周器の信
号と基準信号発生器の基準信号との位相差を比較し位相
差に応じた出力を発生する位相検波器と、位相検波器の
出力を平滑し直流の制御電圧に変換して可変電圧制御型
発振器の制御電圧とするローパスフィルタとを有してい
る。
2. Description of the Related Art A conventional phase-locked oscillator includes a variable voltage control type oscillator, a frequency divider that divides its output, a reference signal generator that outputs a signal of a reference frequency, and a signal of the frequency divider. And a reference signal of a reference signal generator, and a phase detector that generates an output according to the phase difference, and a variable voltage controlled oscillator that smooths the output of the phase detector and converts it to a DC control voltage. And a low-pass filter as a control voltage.

【0003】位相同期発振器の電源が投入されてから可
変電圧制御型発振器が安定な発振周波数の出力を出すま
での間をロックアップタイムというが、この間の動作に
ついて説明する。
The lock-up time is the period from when the power of the phase-locked oscillator is turned on until the variable voltage controlled oscillator outputs a stable oscillation frequency. The operation during this period will be described.

【0004】電源が投入されると、分周器、基準信号発
生器、位相検波器、可変電圧制御型発振器は、数msの
時間遅れはあってもほぼ瞬時に立上がるが、ローパスフ
ィルタはフィルタ用のコンデンサがあるために、コンデ
ンサの充電に時間がかかり、時間遅れが生じる。
When the power is turned on, the frequency divider, the reference signal generator, the phase detector and the variable voltage control type oscillator start up almost instantly with a time delay of several ms, but the low pass filter is a filter. Since there is a capacitor for the capacitor, it takes time to charge the capacitor and a time delay occurs.

【0005】[0005]

【発明が解決しようとする課題】この従来の位相同期発
振器では、ロックアップタイムを短縮しようとすると、
ローパスフィルタの時定数を小さくする必要がある。し
かし、時定数を小さくすると、位相検波器の出力を十分
に平滑できず、可変電圧制御型発振器の出力に変調がか
かり、受信機のVCOとして使用する場合、歪みやS/
Nが悪化するという問題があった。
In this conventional phase-locked oscillator, if the lockup time is shortened,
It is necessary to reduce the time constant of the low pass filter. However, if the time constant is made small, the output of the phase detector cannot be sufficiently smoothed, the output of the variable voltage controlled oscillator is modulated, and when used as the VCO of the receiver, distortion or S /
There was a problem that N deteriorated.

【0006】[0006]

【課題を解決するための手段】本発明による位相同期発
振器は、可変電圧制御型発振器と、前記可変電圧制御型
発振器の出力を分周する分周器と、前記分周器の出力を
一方の入力とし、基準信号出力を他方入力とする位相検
波器と、前記位相検波器の出力と前記可変電圧制御型発
振器の入力端子との間に設けられたローパスフィルタ
と、前記可変電圧制御型発振器の入力端の電圧と第一の
基準電圧とを比較する比較回路と、前記比較回路の出力
と前記ローパスフィルタの入力との間に設けられたスイ
ッチとを有する。
A phase-locked oscillator according to the present invention comprises a variable voltage control type oscillator, a frequency divider for dividing the output of the variable voltage control type oscillator, and an output of the frequency divider. A phase detector having an input and a reference signal output as the other input, a low-pass filter provided between the output of the phase detector and the input terminal of the variable voltage controlled oscillator, and the variable voltage controlled oscillator. It has a comparison circuit for comparing the voltage at the input end with the first reference voltage, and a switch provided between the output of the comparison circuit and the input of the low-pass filter.

【0007】[0007]

【実施例】次に、本発明の実施例を示した図面を参照し
て、本発明を詳細に説明する。
The present invention will now be described in detail with reference to the drawings showing the embodiments of the present invention.

【0008】図1は本発明の第一の実施例による位相同
期発振器のブロック図である。第一の実施例は、可変電
圧制御型発振器11と、可変電圧制御型発振器11の出
力を分周する分周器12と、基準となる周波数の信号を
出力する基準信号発生器13と、分周器12の出力信号
と基準信号発生器13からの基準信号との位相差を比較
し位相差に応じた出力を発生する位相検波器14と、位
相検波器14の出力を平滑し直流の制御電圧に変換して
可変電圧制御型発振器11の制御電圧とするローパスフ
ィルタ15と、ローパスフィルタ15からの制御電圧と
基準電圧VR1とを比較する比較器16とを有してい
る。
FIG. 1 is a block diagram of a phase locked oscillator according to a first embodiment of the present invention. In the first embodiment, a variable voltage controlled oscillator 11, a frequency divider 12 that divides the output of the variable voltage controlled oscillator 11, a reference signal generator 13 that outputs a signal of a reference frequency, and a divider. A phase detector 14 that compares the phase difference between the output signal of the frequency divider 12 and the reference signal from the reference signal generator 13 to generate an output according to the phase difference, and the output of the phase detector 14 is smoothed to control the direct current. It has a low-pass filter 15 which is converted into a voltage and used as a control voltage of the variable voltage controlled oscillator 11, and a comparator 16 which compares the control voltage from the low-pass filter 15 with the reference voltage VR1.

【0009】次に第一の実施例の動作を説明する。電源
が投入されていない状態では、スイッチSW1およびS
W2は図示の状態になっている。この状態で電源が投入
されると、分周器12、基準信号発生器13、位相検波
器14、および可変電圧制御型発振器11はすぐ立上が
る。比較器16の基準電圧(電圧VR1)が与えられ、
端子21の電圧がこの値より小さいと、比較器16の出
力はローになり、抵抗器R2を通してコンデンサC1お
よびC2に充電するとともに、抵抗器R4およびR5を
通してコンデンサC3およびC4にも充電する。比較器
16の出力電流の能力は十分あるので、コンデンサC1
およびC2は急速に充電され、やがてコンデンサC3お
よびC4も充電されて端子21の電圧が上昇し電圧VR
1を越えると比較器16の出力は反転し、ハイとなり、
トランジスタTR1のベースに電圧を供給し、トランジ
スタTR1およびTR2がオンとなる。トランジスタT
R2がオンとなり抵抗器R2ならびにコンデンサC1お
よびC2の電荷を放電するので、トランジスタTR2の
コレクタ電位は下りはじめ端子21の電圧も下がる。端
子21の電圧が基準電圧VRより下がると比較器16の
出力は反転し、この動作を繰返して急速に端子21の電
圧は基準電圧VR1に近づく。
Next, the operation of the first embodiment will be described. When the power is not turned on, the switches SW1 and S
W2 is in the illustrated state. When the power is turned on in this state, the frequency divider 12, the reference signal generator 13, the phase detector 14, and the variable voltage controlled oscillator 11 immediately start up. The reference voltage (voltage VR1) of the comparator 16 is given,
When the voltage at terminal 21 is less than this value, the output of comparator 16 goes low, charging capacitors C1 and C2 through resistor R2 and capacitors C3 and C4 through resistors R4 and R5. Since the output current capacity of the comparator 16 is sufficient, the capacitor C1
And C2 are rapidly charged, and eventually capacitors C3 and C4 are also charged, and the voltage at terminal 21 rises and voltage VR
When it exceeds 1, the output of the comparator 16 is inverted and becomes high,
A voltage is supplied to the base of the transistor TR1 and the transistors TR1 and TR2 are turned on. Transistor T
Since R2 is turned on and the electric charges of the resistor R2 and the capacitors C1 and C2 are discharged, the collector potential of the transistor TR2 begins to drop and the voltage of the terminal 21 also drops. When the voltage at the terminal 21 falls below the reference voltage VR, the output of the comparator 16 is inverted, and this operation is repeated, and the voltage at the terminal 21 rapidly approaches the reference voltage VR1.

【0010】所定の時間が経った後、スイッチSW1お
よびSW2を図示の状態と反対の状態に切換えてやれば
位相検波器14からの位相差に応じた出力によって可変
電圧制御型発振器11の発振周波数が制御されるので、
すみやかに安定動作に入りロックアップタイムの短縮が
はかれる。
After a lapse of a predetermined time, if the switches SW1 and SW2 are switched to the states opposite to those shown in the figure, the oscillation frequency of the variable voltage controlled oscillator 11 is produced by the output from the phase detector 14 according to the phase difference. Is controlled,
Stable operation starts immediately and lockup time can be shortened.

【0011】図2は本発明の第二の実施例のブロック図
である。図1に示した第一の実施例と同等の動作をする
構成要素には同一の参照番号を付している。第二の実施
例においては、新たに急速充電用のシュミット回路17
を設け、その基準電圧VR2はVR1より低いので、比
較器16の出力はローに、シュミット回路17の出力は
ハイとなり、急速にコンデンサC1およびC2に充電さ
れ、かつシュミット回路17の出力から抵抗器R4およ
びR5を通してコンデンサC3およびC4に充電され
る。端子21の電圧が基準電圧VR2を越えるとシュミ
ット回路17の出力はオフする。比較器16はさらに動
作をつづけ、端子21の電圧が基準電圧VR1より高く
なると出力は反転する。以降の動作は第一の実施例の場
合と同様である。第二の実施例の場合が、第一の実施例
よりロックアップタイムを極めて短縮できる。
FIG. 2 is a block diagram of the second embodiment of the present invention. The same reference numerals are attached to the components that operate in the same manner as in the first embodiment shown in FIG. In the second embodiment, a new Schmitt circuit 17 for quick charging is newly added.
Since the reference voltage VR2 thereof is lower than VR1, the output of the comparator 16 becomes low, the output of the Schmitt circuit 17 becomes high, the capacitors C1 and C2 are rapidly charged, and the output of the Schmitt circuit 17 becomes a resistor. The capacitors C3 and C4 are charged through R4 and R5. When the voltage at the terminal 21 exceeds the reference voltage VR2, the output of the Schmitt circuit 17 is turned off. The comparator 16 continues to operate, and the output is inverted when the voltage at the terminal 21 becomes higher than the reference voltage VR1. The subsequent operation is the same as that of the first embodiment. In the case of the second embodiment, the lockup time can be extremely shortened as compared with the first embodiment.

【0012】[0012]

【発明の効果】以上説明したように、本発明は電源投入
時に実使用上体に近い発振周波数で可変電圧制御型発振
器が発振するように電源電圧投入後の所定時間の間に比
較器によりローパスフィルタを急速に立上げ所定の時間
経過後にスイッチによって切離すことによって、ロック
アップタイムを短かくできる。
As described above, according to the present invention, when the power is turned on, the variable voltage controlled oscillator oscillates at an oscillating frequency close to that of the body actually used, so that the low-pass comparator is used for a predetermined time after the power is turned on. The lock-up time can be shortened by rapidly starting the filter and disconnecting it by a switch after a predetermined time has elapsed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一の実施例のブロック図である。FIG. 1 is a block diagram of a first embodiment of the present invention.

【図2】本発明の第二の実施例のブロック図である。FIG. 2 is a block diagram of a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11 可変電圧制御型発振器 12 分周器 13 基準信号発生器 14 位相検波器 15 ローパスフィルタ 16 比較回路 17 シュミット回路 SW1,SW2,SW3 スイッチ 11 Variable Voltage Controlled Oscillator 12 Frequency Divider 13 Reference Signal Generator 14 Phase Detector 15 Low Pass Filter 16 Comparison Circuit 17 Schmitt Circuit SW1, SW2, SW3 Switches

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 可変電圧制御型発振器と、 前記可変電圧制御型発振器の出力を分周する分周器と、 前記分周器の出力を一方の入力とし、基準信号出力を他
方入力とする位相検波器と、 前記位相検波器の出力と前記可変電圧制御型発振器の入
力端子との間に設けられたローパスフィルタと、 前記可変電圧制御型発振器の入力端の電圧と第一の基準
電圧とを比較する比較回路と、 前記比較回路の出力と前記ローパスフィルタの入力との
間に設けられたスイッチとを有することを特徴とする位
相同期発振器。
1. A variable voltage controlled oscillator, a frequency divider that divides the output of the variable voltage controlled oscillator, and a phase that uses the output of the frequency divider as one input and the reference signal output as the other input. A low-pass filter provided between the detector, the output of the phase detector and the input terminal of the variable voltage controlled oscillator, and the voltage at the input end of the variable voltage controlled oscillator and the first reference voltage. A phase-locked oscillator comprising: a comparison circuit for comparison; and a switch provided between the output of the comparison circuit and the input of the low-pass filter.
【請求項2】 前記可変電圧制御型発振器の入力端の電
圧と前記第一の基準電圧より低い第二の基準電圧とが入
力されるシュミット回路とを有し、 前記シュミット回路の出力で前記ローパスフィルタ内の
コンデンサを充電することを特徴とする請求項1記載の
位相同期発振器。
2. A Schmitt circuit to which a voltage at an input terminal of the variable voltage controlled oscillator and a second reference voltage lower than the first reference voltage are input, the output of the Schmitt circuit being the low-pass filter. The phase-locked oscillator according to claim 1, wherein a capacitor in the filter is charged.
JP4203501A 1992-07-30 1992-07-30 Phase locked loop oscillator Withdrawn JPH0653824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4203501A JPH0653824A (en) 1992-07-30 1992-07-30 Phase locked loop oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4203501A JPH0653824A (en) 1992-07-30 1992-07-30 Phase locked loop oscillator

Publications (1)

Publication Number Publication Date
JPH0653824A true JPH0653824A (en) 1994-02-25

Family

ID=16475205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4203501A Withdrawn JPH0653824A (en) 1992-07-30 1992-07-30 Phase locked loop oscillator

Country Status (1)

Country Link
JP (1) JPH0653824A (en)

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19991005