JPH0653413A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize a master slice system semicustomized LSI in a shorter time at lower cost by selecting the connecting system between an underlying chip and various types of outer case depending on the chip size and the pin count. CONSTITUTION:Electrode pads for connection with outer case are formed in two zigzag rows along the periphery of a semiconductor chip 1. wherein the size of first outside pad 3 is differentiated from that of second inside electrode pad 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a structure of an electrode pad of a master slice type semi-custom semiconductor integrated circuit.

[0002]

2. Description of the Related Art There is a wire bonding method as a method for connecting a semiconductor chip to an external substrate or an external case. This is to connect an electrode pad provided in a semiconductor chip and an electrode portion of an external substrate or an external case with a gold wire having a diameter of about 30 μm, but it is relatively easy and highly reliable at present. , Has become the mainstream of semiconductor integrated circuit assembly.

However, with respect to the chip shrinking due to the progress of the semiconductor manufacturing process, the increase in the number of bits of the CPU, and the increase in the number of pins due to the demand for multi-phase signal processing and the like, the bonding method is not necessarily effective. That is, the current standard of wire bonding method is generally wire length: 2.5 mm, pad pitch: 120 μ.
However, in the case of assembling a 4 mm square chip in a plastic case, the maximum number of pins is about 100 together with the limitation of the lead frame processing technology. However, with a 0.8 μm rule gate array, 4 m
There is a degree of integration of about 10,000 gates in an m-square, and the number of pins required for it is 160 or more in reality.

Conventionally, in such a case, the chip size has been increased to the extent that the number of pins can be secured.
It is no longer possible to deal with it due to the impact of the unit price of gates, which is decreasing year by year. Therefore, the TAB bonding method suitable for a narrow pad pitch has begun to be applied. Firstly, there is no wire length limitation, secondly, the pad pitch can be up to about 40 μm so far, and there are advantages over the above wire bonding method. The required semiconductor chip is this TAB
It is designed with a pad pitch and pad size compatible with the bonding method.

[0005]

On the other hand, a master slice type semi-custom LSI, in which basic transistors are arranged in a matrix and a wiring layer is formed for each desired circuit function, has a short development period, high specialization, It is used in many applications as an important semiconductor element along with CPU and memory due to its good confidentiality.

Therefore, a semi-custom LSI represented by a gate array has a selling point in how to manufacture a product in a short period of time from the date when circuit information is obtained from a customer.
Various efforts have been made to achieve this, one of which is the preparation of assembly materials in advance. This is to predetermine the connection relationship between the base chip and the external case before creating the customer's circuit information, and prepare the jigs and materials necessary for assembly so that they can be used at any time. Naturally, it is necessary to prepare not only one type of external case but also many types of cases that are expected.

In such a situation, if the base chip is designed with a pad pitch and a pad size intended only for the TAB bonding method, the wire bonding method cannot be used at all, and the material maintenance by the TAB bonding method is required even in the case of assembly by wire bonding. Forced. For example, when a material for a 100-pin plastic case is prepared for a base chip of 4 mm square, the TAB bonding method, which requires a cost corresponding to the material cost of the TAB tape, is more disadvantageous than the wire bonding method in terms of cost ratio.

[0008]

In a semiconductor integrated circuit of the present invention, a commonly used basic cell is provided on a semiconductor chip, and wiring is formed on the semiconductor chip to realize a desired circuit function. In the semiconductor integrated circuit to be used as the semiconductor chip, the electrode pads are arranged in two rows and in a staggered pattern on the peripheral portion of the semiconductor chip, and the first electrode pad provided on the outer side and the second electrode pad provided on the inner side The size is different.

[0009]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a plan view of a first embodiment of the present invention, and FIG. 2 is an enlarged plan view of an electrode pad portion in FIG.

In FIGS. 1 and 2, on a semiconductor chip 1 made of silicon or the like, basic cells commonly used for wiring are arranged in a basic cell arrangement region 2 in, for example, a matrix form, and in the peripheral portion thereof. Has two types of square electrode pads arranged in two rows and in a zigzag pattern. And
Particularly, the size of the outer first electrode pad 3 is formed larger than that of the inner second electrode pad 4.

In FIG. 2, the first electrode pad size (width) a is 110 μm, and the second electrode pad size b is 7.
When the distance c between the basic cell disposition region 2 and the second electrode pad 4 and the distance d between the second electrode pad 4 and the first electrode pad 3 are 0 μm, the width q of the pad region is 3 μm.
It is set to about 00 μm. If a 5 mm square chip is designed under this condition, a base chip in which basic cells of 10,000 gates are spread is formed. When the pitch p of electrode pads is 85 μm, the number of electrode pads is 100 on the outside and 200 on the full pad.
It will be about. Therefore, when assembling into a case with 100 pins or less, as shown in FIG. 3, a wire bonding method in which the wire 5 is used to connect the electrode pad and the lead 6 is used. In case of 100 pins or more, see Fig. 4.
As shown in (a) and (b), the bump ball 7 formed on the electrode pad and the TAB lead 6A supported by the support film 8 such as polyimide are connected by the TAB bonding method.

In case of a chip of 5 mm square and 100 pins, the wire length is about 2 mm and it can be assembled without any problem. If the pad size is 70 μm and the pad pitch is 85 μm, the wire bonding method cannot be used at all, and the TAB bonding method must be used even in the case of 100 pins or less, resulting in high cost.

FIG. 5 is a plan view of the electrode pad portion of the second embodiment of the present invention. In the second embodiment, the size of the outer first electrode pad 3A is smaller than that of the inner second electrode pad 4A, and the other points are the same as in the first embodiment.

In FIG. 5, the size a of the first electrode pad 3A is 70 μm, and the size b of the second electrode pad 4A is 1.
10 μm, a distance c between the chip active region and the second electrode pad and a distance d between the second electrode pad and the first electrode pad
Is 30 μm, the pad area q is within about 300 μm, and as in the first embodiment, the number of inner pads is 100 and the number of outer pads is 200 with a 5 mm parallel chip. Therefore, when assembling in a case with 100 pins or less, a wire bonding method is used, and in the case with 100 pins or more, the TAB as shown in FIG.
It is assembled by a bonding method, but at this time, it is advantageous that the TAB lead 6A can be made wider than in the first embodiment. The wire length during wire bonding is slightly increased.

[0015]

As described above, according to the present invention, staggered electrode pads are provided in two rows in the peripheral portion of the chip, and the size of the outer and inner electrode pads is made different, so that the base chip Since a bonding method suitable for the chip size and the number of pins can be selected as a connection method with a variety of external cases, there is an effect that a master slice type semi-custom LSI can be realized at a lower cost in a shorter time.

[Brief description of drawings]

FIG. 1 is a plan view of a first embodiment of the present invention.

FIG. 2 is a plan view of an electrode pad portion according to the first embodiment of the present invention.

FIG. 3 is a plan view of the case where the wire bonding method is used to assemble the first embodiment.

4A and 4B are a plan view and a cross-sectional view when assembled by the TAB bonding method using the first embodiment.

FIG. 5 is a plan view of an electrode pad portion for explaining a second embodiment of the present invention.

[Explanation of symbols]

 1 Semiconductor Chip 2 Basic Cell Arrangement Area 3, 3A First Electrode Pad 4, 4A Second Electrode Pad 5 Wire 6 Lead 6A TAB Lead 7 Bump Ball 8 Support Film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/82

Claims (1)

[Claims] 1. A semiconductor integrated circuit in which a commonly used basic cell is provided on a semiconductor chip, and wiring is formed on the semiconductor chip to realize a desired circuit function. The electrode pads are arranged in two rows in a zigzag pattern in the peripheral portion, and the first electrode pad provided on the outer side and the second electrode pad provided on the inner side have different sizes. Semiconductor integrated circuit.