JPH06511353A - Solder film reflow method for forming solder bumps on circuit traces - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Solder film glue flow method for forming solder bumps on circuit traces Technical field The present invention provides solder-bumped circuit traces. , relates to a method of forming on printed circuit boards and the like. More specifically, Lighting removes the thin solder film deposited on the circuit traces. Flow (reflow) L, the stage of collecting and merging solder to form solder bumps The method is comprised of:

Background technique In the manufacture of microelectronic packages, integrated circuit components are used for solder bump interconnections. Therefore, it is known to be mounted on a printed circuit board. For this purpose, The circuit board includes copper circuit traces disposed on a dielectric substrate. Load parts To attach solder bumps to bond pads on components, they are typically preformed. A solder alloy microsphere is placed on top of the pad and heated to reflow the solder. bump The component with the Assembled with board. This assembly is heated to reflow the solder and cooled. When the solder hardens again, it quickly bonds to the traces and pads of the component. to physically couple the component to the circuit board and to connect the component electrically to the traces. electrical signals are transmitted and processed between the components.

Forming solder bump interconnects delivers more solder to form interconnects It is proposed to apply a solder bump to the trace at its attachment location in order to came. Also, as is well known, electroplating is convenient for applying solder to printed circuit boards. It is. However, electroplating does not require solder bumps that provide large clumps at that location. Creates a uniform coating over the entire surface, as opposed to Therefore, the specified value on the circuit trace There remains a need for improved methods for performing solder bumps in exposed locations.

Demonstration of invention The present invention is directed to a method of forming bump circuit traces, which method comprises: , depositing a thin film of solder alloy onto the trace, and depositing the solder alloy on the trace. The step includes reflowing to form a bump.

In one aspect of the invention, the trace includes a first linear section and a first linear section. the first section at the intersection so that the angle between the sections is between 45 degrees and 135 degrees. a second linear section arranged to intersect the yon. 1st The trace section has a uniform convergence (typically less than 500 microns, (preferably 150 microns). The second trace section is has a uniform radius, which may be equal to or different from the radius of the first section; This is also typically less than 500 microns, preferably between 50 and 150 microns.

In another aspect of the invention, the solder bumps are formed on the terminals, and the terminals are predetermined. The configuration includes a wide area pad connected to a linear runner section with a do. A runner width of less than 500 microns is suitable, with a width of 50 to 150 microns. preferred. A wide area pad has a radius measured parallel to the runner's radius. exceed.

In any case, the traces are formed of a metal (most commonly copper) that has solderability. will be accomplished. Before reflow, the traces are pre-constructed with solder alloy and uniformly It includes a thin outer coating with a thickness. The trace is then heated to melt the solder layer. When melted, the solder alloy surprisingly collects at intersections or large area pads. It is recognized that the desired bump can be formed. In a preferred embodiment, the solder layer is an electrical Deposited to a thickness of approximately 10 to 25 microns by with a height greater than 40 microns (preferably 60 to 80 microns). form a bump.

In a further aspect of the invention, a method of manufacturing a printed circuit board is provided. Ru. This method: First, a dielectric substrate (copper coating) is applied, and then a photolithography is applied to the coating. Applying a mask, etc. Contains stages. The mask defines an opening that exposes the copper in the trace area, but Coat the area adjacent to the race with copper coating I. The masked copper coating will dissolve. The cathode is immersed in an electroplating bath containing tin ions and lead ions. 1 and then deposit tin and lead at the same time on the exposed copper (c Form a thin solder film. Part 1, remove the mask and play Immerse the plate in copper etching solution. The solder coating has copper traces underneath it. while the etching solution etches the exposed copper to define the trace. do. The traces are then heated for a period of time to form one solder bump.

Therefore, the present invention provides a convenient way to form solder bumps on circuit traces. provide a method. ) (Since it is formed by a thin solder film, the time force (reduced).

In addition, the solder film has the advantage of serving as an etching mask port before reflow. circuit board using only one photo1 photo mask. Lace can be defined and solder can be deposited. The solder is thin) and is deposited as a film. However, the trace force (that?) is heated and melts the solder alloy. The solder then joins and is used (for example, to connect parts by interconnecting solder bumps). form a bump of sufficient mass to

Brief description of the drawing The invention will be further clarified by reference to the accompanying drawings, in which: FIG.

FIG. 1 shows the circuit traces employed to form solder bumps according to the present invention. , a partial top view of a printed circuit board.

Figure 2 is a diagram of Figure 1 taken along line 2-2 showing the solder coating/trace before reflow. FIG. 2 is a cross-sectional view of a printed circuit board.

Figure 3 shows the circuit trace of Figure 2 after reflowing the solder film to form the bumps. FIG.

FIG. 4 shows an alternative embodiment of circuit traces forming solder bumps according to the present invention. , a partial top view of a printed circuit board.

FIG. 5 shows another embodiment of circuit traces forming solder bumps according to the present invention. FIG. 2 is a partial plan view of the printed circuit board shown.

FIG. 6 shows yet another embodiment of circuit traces forming solder bumps according to the present invention. FIG. 2 is a partial plan view of the printed circuit board shown.

FIG. 7 shows a printed circuit board showing terminals on which solder bumps are formed from Invention 1. It is a top view of a board.

Figure 8 shows the printed circuit of Figure 1 cut along line 2-2 showing the terminal before solder reflow. It is a sectional view of a road board.

Figure 9 is a cross-sectional view of the terminal in Figure 2 after reflowing the solder alloy to form bumps. be.

FIG. 10 shows solder bumps formed on a printed circuit board according to the present invention. This is an electron micrograph.

FIG. 11 shows a print having an alternative configuration suitable for forming solder bumps according to the present invention. FIG. 3 is a perspective view of terminals on the circuit board.

FIG. 12 shows yet another configuration suitable for forming solder bumps according to the present invention. FIG. 3 is a perspective view of a terminal on the component circuit board.

BEST MODE FOR CARRYING OUT THE INVENTION In a first preferred embodiment, referring to FIGS. 1 to 3, the method of the present invention is employed. , forming a printed circuit board 10 having solder bump circuit traces 12 . Puri The component circuit board IO is constituted by a dielectric substrate 14, and the dielectric substrate is connected to the FR4 card. It is composed of epoxy resin and glass fiber layers. substrate 14 has a planar major surface 16 to which circuit traces 12 are attached. Features of the present invention For clarity, only a portion of the circuit board 10 is shown in the figure and may not be shown. The area covered only constitutes a small portion of the total, and the circuit trace 12 It is understood that they extend over other areas of the circuit board to transmit and process signals.

In accordance with the invention, circuit trace 12 includes a first linear section 18 and a second linear section 18. Section 20 (each with uniform convergence throughout approximately 1°0 microns) It is composed of Section 18.20 at the intersection indicated generally at 22 so that they intersect and the angle between the sections is a right angle, i.e. 90 degrees. , located on the surface 16.

Referring to FIG. 2, in accordance with the method of the present invention, circuit traces 12 are initially It is formed by two metal layers 24 and 26 with edges. Layer 24 is the substrate surface 1 A metal with high electrical conductivity that is placed in direct contact with 6 and helps transmit electrical signals. Formed by copper. The copper layer 24 is formed by an electroplated tin/lead solder alloy. coated with a thin layer 26 consisting of

Printed circuit board 10 is manufactured by patterning the copper coating to define traces 12. , step 18.20 containing intersecting sections, electroplating solder onto the traces. It is manufactured by following steps. Therefore, copper plating is first applied to the dielectric substrate 14. to completely cover surface 16. This coating therefore covers layer 2 of trace 12. 4 and adjacent areas around trace 12. Appropriate copper plating The circuit board is commercially available and has a copper coating approximately 17 microns thick. Features. This copper coating is then coated with a photosensitive polymer material that selectively irradiation to develop the polymer and form a photoresist mask.

This mask is approximately 25 microns thick and covers the copper plating area around the traces. and defines an opening through which layer 24 of the trace portion is exposed.

The masked circuit board is immersed in a tin/lead plating solution and the cathode is biased. then deposit the solder alloy onto the exposed copper traces. A suitable plating tank is Its composition per liter of water is 56.3 grams of tin (stannic fluoroborate). 26.3 grams of lead (added as a lead fluoroborate concentrate), 26.3 grams of lead (added as a lead fluoroborate concentrate), ), 99°8 grams of fluoroboric acid, 26.3 grams of boric acid, and liquid Peptide The weight is 19.5 grams. The masked circuit board has a tin/lead opposing 'IL. Spaced apart from the pole, it is immersed in a plating bath at ambient temperature. Electrolyte on copper plating A potential is applied to negatively bias the copper with respect to the counter electrode, and the metal tin and metal Lead is simultaneously codeposited onto the exposed copper surface.

Tin is deposited on top of the copper film before removing unwanted copper around the traces. /One advantage of plating lead is that the uninterrupted plating allows for uniform electrical conductivity. Easy plating flow to create position (elec+rodeposit) It is something that can be allocated. The resulting plating is approximately 40% lead, with the remainder being lead. The plate is constructed of tin and has a thickness of about 20 microns. The thickness of the plating is Plating should be limited to the opening above the trace, as it should be thinner than the trace. and does not extend to the mask surface.

After plating, the circuit board is immersed in an alkaline solution to remove the photoresist mask. This exposes the copper plating area around the solder coated traces. Let it come out.

The circuit board is immersed in an aqueous copper etching solution containing ammonium peroxonisulfate. Soak and rinse with water. The etchant removes the exposed copper. however , the tin/lead alloy is resistant to the corrosion of etching solutions and acts as a mask. to protect the copper traces underneath. In this way, unnecessary copper is removed from around the trace. The traces are removed to complete the manufacture of the solder plated traces shown in Figure 2. features a copper coating 24 coated with a uniform, thin solder coating 26.

The printed circuit board with double layer traces 12 is heated to reflow the solder; A desired bump is formed on the intersection 22. In isopropyl alcohol catalyst amine hydrochloride and amine, ° Composed of amine hydrobromide A flux is applied to the solder coating surface. The circuit board is exposed to a hot point of 250℃. Immerse in the lyoxyalkylene glycol bath for 15 seconds. During dipping, solder The alloy melts and reflows, drawing solder from the sections to the intersection 22. This facilitated the formation of the bump 3o shown in FIG. After reflow, A residual solder coating 32 remains on section 18.20, but its thickness is different from that of the original coating. significantly thinner in comparison. Bump 30 has a height of more than 40 microns (6 0 to 80 microns is preferred). For this reason, the bumps 30 are similar to the solder bumps. It is particularly suitable for making connections and attaching electrical components to printed circuit boards IO.

In the embodiment shown in FIG. It grows. This arrangement allows the member attached to the intersection 22 and another part of the electrical circuit to It is particularly useful for allowing electrical signals to be transmitted between the bumps 30 and It is advantageous. However, the method of the present invention requires that both linear sections of the electrical circuit It is not limited to traces that are active leads, only one section is in the circuit. It can be employed to create solder bumps at the intersections when connected.

Referring to FIG. 4, a printed circuit board 50 is provided with solder bumps according to the method of the present invention. circuit traces 52 having alternative configurations suitable for formation thereon; Ru. Traces 52 are placed on a flat dielectric substrate 54 similar to substrate 14 of FIG. It will be done. The traces 52 form an intersection (generally designated 60) that intersects at a right angle a. a first linear section 56 and a second linear section 58. Ru.

In this embodiment, linear section 56 is connected to a remote electrical function on circuit board 50. and provides an active lead for transmitting electrical signals to and from the intersection 60. In order to serve the purpose, it extends beyond the area shown in FIG. However, the second sex Yon 58 is shortened so that no electrical circuit is connected other than through the connection through lead 56. Do not connect to road. As shown in FIG. 4, trace 52 is a copper layer and a thin, uniform electroplated coating of tin/lead solder. i.e. , trace 52 is made by patterning the copper layer and electrically depositing a thin solder film under conditions similar to FIG. This figure shows after chemical deposition but before solder alloy glue flow. Then The race 52 is heated, for example by immersion in a hot oil bath, to remove the solder on the outside. The coating is melted so that the molten solder flows from the adjacent section to the intersection 6. 0 to form solder bumps.

If enough molten alloy is available to form a bump, it will be formed during reflow. The size of the bump is determined primarily by the surface tension of the molten alloy and It is independent of the length of the session. For this reason, for linear sections with equivalent convergence, 4, the size of the bump formed at the intersection 60 of the traces 52 in FIG. , considered equal to the bump formed at the intersection 22 of trace 12 in FIG. section 58 as necessary to make up for any shortfall in the amount of metal collected from section 58. Further molten metal is collected from section 56.

Referring to FIG. 5, in yet another embodiment of the invention, printed circuit board 70 includes: It includes a figure 7 trace 72 suitable for forming bump intersections in accordance with the present invention. to Race 72 is attached to dielectric substrate 74 and includes a first section 76 .

The first section 76 is mounted on the circuit board 70 to serve as an active lead for an electrical circuit. Extends to connect remotely with other electrical functions. Trace 72 also includes A short section 78 . intersects trace section 76 at difference section 82 . 80. Section 76.78°80 is between adjacent sections are arranged equiangularly with the intersection 82 in the center so that the angle a'' of is 120 degrees. Ru. The tray 772 is shown before reflow, and the lower tray directly in contact with the substrate 74 is shown before reflow. Copper layer and a uniform, thin electrical metal layer of tin/lead solder alloy similar to trace 12 in Figure 2. It is composed of

The traces are then heated to melt the outer solder coating, resulting in the intersection 8 2, the solder joins to form a solder bump. In this example, two The short sections 78.80 come together by capillary action to form a bump. The amount of solder in the area adjacent to the intersection 82 is increased.

FIG. 6 shows yet another trace configuration suitable for forming solder bumps in accordance with the present invention. An example is shown below. Printed circuit board 90 is a dielectric substrate with traces 94 attached. 92. Trace 94 is connected to an electrical circuit to act as an active lead. constructed by a first linear section 96 extending long to connect with remote features of the road. will be accomplished. The traces 94 also intersect with each other at the intersection indicated by 104. Also intersecting section 96 are three short linear sections 98, 100, 102. including. Sections 96, 98, 100, and 102 are at right angles between adjacent sections. They are arranged equiangularly around the intersection 104 so as to form the following. Trace 94 is The initial plating state before flow is shown, which shows the underlying copper layer in direct contact with the substrate 92, and and a uniform thickness of outer solder electroplating placed on top of each section. be done.

The trace 94 is then heated, for example by immersing it in an oil bath. Reflow the solder coating so that the solder flows through sections 96 and 96 by capillary action. 98, 1.00° are collected from 102 and merge at the intersection 104 to form a solder bump. form. The embodiment of Figure 6 is designed so that adjacent sections form a preferred right angle. while increasing the amount of solder in the portion adjacent to the intersection portion 104. There are particular advantages in this respect.

In the embodiments described so far, the incredible formation of solder bumps is shown in the circuit traces. What happens at the intersection of the first linear section and the second linear section Admitted.

This method uses a 500 micron subsurface Particularly suitable for use in sections with zero width. Section convergence is approximately 50 to 15 0 micron is desirable. In the above embodiment, equal convergence is used to form the bump. However, other design considerations of electrical circuits, e.g. Sections with different convergence can be adopted as necessary to accommodate various conditions. Li The optimal condition for bump formation during flow is an arrangement in which the angles between the sections are right angles. It is thought that this is brought about by placing it in a certain position. However, proper bump The condition for forming is that the angle between the sections is in the range of about 45 degrees to 135 degrees. Ru.

In another embodiment of the invention, referring to FIGS. 8-10, the method of the invention is employed. to form a printed circuit board 110 having a plurality of solder bump terminals, and The components of the integrated circuit are mounted by interconnecting the integrated circuits. printed circuit board 110 is constituted by a dielectric substrate 112 similar to the circuit board 10 of FIGS. 1 to 3.

Circuit board 110 further includes a plurality of terminal sections 116, each of which has terminal sections 116. The electrodes are attached to the planar surface of the substrate 112 and surrounded by adjacent exposed areas 114. . In accordance with this embodiment, each terminal 116 connects with a linear runner section 120. It is constituted by a wide area circular terminal-panod 118 connected to the terminal. runner section The rings 120 extend radially from the circular pad 118 and have a uniform radius W (approximately 10 (preferably 0 microns). In a preferred embodiment, terminal pad 118 is approximately It has a diameter W of 150 microns.

Referring to FIG. 8, according to the method of the present invention, each terminal section 116 is initially identical. It is made up of two metal layers 122 and 124 having an extent of .

Layer 122 is placed in direct contact with substrate 112 and is an electrical layer that serves to transmit electrical signals. Preferably, it is made of copper, a metal with high conductivity. The copper layer 122 is a thin layer Hibiki 124 is electroplated tin/lead solder. Preferably, it is composed of an alloy. The manufacturing of the printed circuit board 110 is shown in FIG. Mask the copper film to define the traces using the steps shown in Figures 1 through 3. step, removing the mask to expose the surrounding copper, and etching the exposed copper. This is done by a step of tinting, so that the solder film is It acts as a screen.

The originally formed printed circuit board has a uniform thin solder coating placed over the traces. Consisting of a film, this circuit board is added! l! l, then reflow the solder as desired form a bump.

The circuit board was placed in a polyoxyalkylene glycol bath at a high temperature of 250°C for 15 seconds. immersed. During dipping, the solder alloy melts and reflows into the linear runner section. 120 to accumulate the solder on the terminal pad 118, which causes the solder in FIG. It was observed that the bump 124 shown in FIG.

After reflow, a residual solder film 126 remains on the runner 120, but its thickness is It is significantly thinner than the film of

FIG. 10 shows an electron microscope of a solder bump on a terminal formed according to this example. It's a photo. The bump height from the copper trace was approximately 60 microns. For this reason , the bumps form solder bump interconnects to attach electrical components to printed circuit boards. It was considered particularly suitable for wearing.

Therefore, this example uses solder paste to create solder bumps on the terminal pads of copper traces. It provides a flow method. This reflow method uses a tray containing terminal pads. Only one photoresist mask is required to define the space.

This method also involves depositing the solder by electroplating and then depositing the solder on the tray. Can be used as a mask during etching. This method allows you to By creating a condition where the solder is collected and merged onto the pad, the solder stop is avoid use. This method also deposits a relatively thin film, which can then be reused. Plating time is reduced by flowing into the desired mass for bump formation.

Although not limited to any particular theory, the incredible formation of bumps during reflow is due to the Due to individual configuration. The terminal has a wide area pad connected to a relatively narrow runner. During reflow, molten solder is buffered from adjacent runners by capillary action. It is effective for collecting on the board. The terminal design ensures that the desired bumps and bumps are maintained during reflow. Minimize the required solder film thickness while collecting enough solder to size It is desirable to optimize the ratio of runner radius to pad radius in order to . The runner width here refers to the width of the runner directly adjacent to the wide area pad. The width of the runner is the width of the runner, while the pad radius is the width of the pad measured parallel to the width of the runner. refers to the maximum dimension of This method is similar to the one commonly employed in circuit trace design. , is considered particularly suitable for use with runners having a width of less than about 500 microns. available. The radius of the runner is preferably about 50 to 150 microns. band's radiance, That is, the diameter of the circular pad is at least as large as the width of the adjacent runner. 1.2 times is effective in collecting enough solder to form a proper bump. It is fruitful. The width of the pad is preferably about 1.2 to 2.0 times the convergence of the runner.

Referring to FIG. 11, in yet another embodiment, printed circuit board 140 is square Includes a pad 146, which is a wide area for merging the solder alloy to form a bump. Suitable for providing area. The circuit board 140 includes an epoxy glass substrate 142 and and a terminal section 144, which includes a pad 146 and a terminal section 144. and an adjacent runner 148 extending to one corner of the square pad. terminal pad The terminal section is shown together with the solder coating to better illustrate the shape of the head. but before doing the reflow to form the bumps, the copper traces, and a thin uniform solder layer similar to the terminal shown in FIG. During reflow, solder are collected from the runner section onto the terminal pads to form a generally hemispherical bump. make.

Still another example, FIG. 12 shows a printed circuit board 160, which is made of epoxy The end of the structure constituted by xyglass substrate 168 and suitable for implementing the present invention. It also has a child 164. The terminal 164 has a rectangular pad 166 and a pad 166. an adjacent runner section 162 extending from one side of the runner section 6; Ru. To better illustrate the shape of the pad, the terminals are the same as those shown in Figure 8. Figure 3 shows the state before reflow after t% deposition. During reflow, solder are collected from adjacent runners onto the terminal pads to create the desired rounded bump. .

An important feature of the invention is that from an initial thin coating of solder alloy on the traces to a reflow It is to form a bump in between. Copper is relatively low cost and can carry electrical signals. As a trace metal, it has advantageous electrical properties, including low resistance, which helps Most commonly chosen, terminals include, for example, nickel or gold. This gold can be formed from any suitable metal that provides a solderable surface. The metal can be applied directly onto a dielectric substrate or onto a copper or other metal base. , an intermediate layer may be provided between the base and the solder. The solder layer is suitable for solder alloy such as It can also be formed by Typical solder alloys consist of lead, tin and indium It can be formed mainly from one or more metals selected from the group, among which lead-based alloys containing about 5 percent tin by weight; Indium-based alloys containing approximately 30 percent lead are included. half The field is a nearreutectic tin containing about 35 to 45 percent lead. / Preferably made of lead alloy. Solder is deposited by electroplating. It is preferable to sputter or trace a thin layer of solder metal. It may be formed by any method suitable for application thereon.

In the illustrated embodiment, the thin solder film glue flow also leaves a residual film on the runner. The membrane was also left behind. In order to provide enough molten alloy to maximize the bump size, It is desirable to deposit the field with sufficient thickness. Depending on the intended use, Residual coating on the runner may provide benefits, e.g. by providing a protective coating. Sometimes. On the other hand, certain trace configurations can minimize initial solder deposition. In some cases, it may be desirable to reduce or eliminate residual coatings. thickness is 2 Solder films of less than 5 microns can be formed using ring reflow for bump formation. Provide sufficient metal during the reflow. The initial solder film thickness was approximately 10 to 25 microns is desirable. To form solder bump interconnections, use a copper tray. Bumps with a height of at least 40 microns (approximately 60 to 8 0 micron) is desirable.

Although the invention has been described with respect to certain embodiments, it is not intended to be limited to the above description. It is not intended that the invention be limited, rather, to the extent set forth in the claims that follow.

Embodiments of the invention for which exclusive ownership or privilege is claimed are set forth below. .

FIG, 7 FIG, 8 Continuation of front page (81) Specified times EP (AT, BE, CH, DE.

DK, ES, FR, GB, GR, IE, IT, LU, MC, NL, SE), J P, KR (72) Inventor: Bethkenbaugh, William M. United States of America 78 Bisz Lane, Burlington, Illinois (72) Inventor Cholewczynski, Kennys, Illinois, USA 806 Post Lane, Treemwood

Claims (15)

[Claims] 1. Solder onto predetermined sections of circuit traces attached to the dielectric substrate. A method of forming a bump, the method comprising: manufacturing a solder-wettable metal circuit trace, the step of manufacturing said circuit trace; the predetermined section and the predetermined section. Stage composed by connected adjacent sections，Constructed by solder alloy applying an outer coating to the circuit trace, the outer coating covering the predetermined section and said adjacent section, said outer coating being positioned over said section and said adjacent section; having a uniform thickness, and heating said outer coating at an effective temperature to form said half-coat. melt the solder alloy and transfer the molten solder alloy from the adjacent section to the predetermined forming solder bumps in the desired sections; A method characterized by comprising: 2. Claim wherein the outer coating has a thickness of less than about 25 microns. The method described in 1. 3. wherein the solder bump has a height greater than about 40 microns. The method according to claim 1. 4. The outer coating has a thickness of about 10 to 25 microns, and the solder bumps have a thickness of about 10 to 25 microns. The method of claim 1, having a height of about 60 to 80 microns. 5. The circuit traces are formed of copper metal, and the outer coating is The percentage consists of approximately 35 to 45 percent lead and the remainder substantially tin. The method according to claim 1, characterized in that the solder alloy is made of a solder alloy. 6. The method includes a first linear section and an intersection with the first linear section. a second linear section that intersects at an angle of about 45 degrees to 135 degrees; consisting of a step of manufacturing a circular trace constituted by, and furthermore The method includes heating the outer coating to form solder bumps at the intersections. 2. A method according to claim 1, characterized in that the method is constituted by the steps of: 7. The first linear section and the second linear section are adjacent to the intersection. and having a uniform width of less than 500 microns throughout. How to put it on. 8. At least one of the first linear sections and the second linear section are , adjacent the intersection and having a uniform width of about 50 to 150 microns throughout. 7. A method according to claim 6, characterized in that: 9. The method includes a terminal pad and a runner sector connected to the terminal pad. said runner section. The section has a section width at a portion adjacent to the terminal pad, and has a section width adjacent to the terminal pad. the outer coating has a width greater than the section width; forming a solder bump on the terminal pad by heating the terminal pad. 2. A method according to claim 1, characterized in that: 10. the runner section has a section width of less than 500 microns; The terminal pad has a width that is 1.2 times greater than the linear section width. 10. The method of claim 9, characterized in that: 11. The width of the terminal pad may be about 1.2 to 2.0 times the section width. The method according to claim 9, characterized in that: 12. The runner section has a section width of about 50 to 150 microns. 10. The method according to claim 9, comprising: 13. The terminal pad is circular, and the runner section is connected to the terminal pad. 10. A method according to claim 9, characterized in that the method extends radially from. 14. The terminal pad is square, and the runner section is connected to the terminal pad. 10. The method of claim 9, further comprising extending from one corner of the board. 15. The terminal pad is rectangular, and the runner section extends along the terminal pad. 10. A method according to claim 9, characterized in that it extends from one side of the board.