JPH0650913B2 - Automatic polarization switching device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an automatic polarization plane switching device such as a satellite broadcast receiver.

2. Description of the Related Art In recent years, in a device for receiving C-band satellite broadcasting, which has become popular in the United States, a polarizer (hereinafter referred to as a polarizer) that determines whether to receive vertical polarization or horizontal polarization. Is used.

Problems to be Solved by the Invention However, the conventional method of automatically switching the plane of polarization in response to the change of the receiving channel is not yet widely used, and the one currently used is Many of them are not accurate enough.

Further, conventionally, there are many examples in which whether or not the polarization plane matches the desired radio wave is determined by one parameter, but there is a problem that malfunction occurs when there is a strong noise wave. For example, if only the AGC voltage of the receiver is used for determination, if there is a ground wave stronger than the desired wave near the desired wave, the
The C voltage depends.

In view of the above problems, the present invention provides an automatic polarization plane switching device that can improve the accuracy of determining the optimum point of polarization plane.

Means for Solving Problems The automatic polarization plane switching device of the present invention determines whether or not the polarization plane is optimum by determining the frequency of horizontal AFC, the detection of horizontal sync pulse, the minimum number of white peak and black peak noises. And AGC
Judgment is based on the combination of voltage peak points.

Effect According to the present invention, the video signal during the FM detection output is synchronously separated, the horizontal AFC is operated, and it is determined whether or not it is a TV signal by the difference between the frequency of the AFC and the frequency of the crystal oscillator, and the synchronous separation is performed. The interval of the horizontal sync signal in the output is measured by the crystal oscillation frequency, while the black peak and white peak noises of the pedestal clamped signal are counted. Therefore, it is determined that the minimum point of noise is the normal polarization plane, and it is possible to automatically switch the polarization plane with high accuracy.

Embodiment FIG. 1 shows a block diagram of an embodiment of the present invention. 1 in the figure
Is a parabolic antenna, 2 is a hollow support column for supporting an outdoor unit (ODU) 3, and a cable 6 and a lead wire 7 are installed in the hollow portion. The outdoor unit 3 is considered here as a so-called LNB (low noise block converter). 4 is roughly classified into a polarizer, and there are a method of rotating the probe by a motor (servo type) and a method of switching the magnetization direction of ferrite (solid type). In either method, the plane of polarization can be controlled by DC voltage. 5 is a pillar of the parabolic antenna 1, 6 is a high frequency cable for transmitting the output of the outdoor unit 3 to the indoor satellite receiver 17, and 7 is a voltage for controlling the plane of polarization of the polarizer 4 or a pulse having a certain pulse width. It is a ground for transmitting signals and a pair of lead wires. A tuner 8 is tuned to a desired frequency and is also called a 2nd mixer. Reference numeral 9 is an intermediate frequency IF (for example, 510 MHz) amplifier, 10 is an FM signal detector, and 11 is a detector and an amplifier for generating an AGC voltage. 12 is an FM detector 10
A circuit for selecting and tuning one of a plurality of audio carriers in the output of the above to obtain an audio signal in the base frequency band, 13 a sync separation circuit, a circuit including a horizontal AFC circuit and a crystal reference oscillator, 14 Is a circuit for detecting noise closer to black than the black peak level and noise closer to white than the white peak level, 15
Is the peak noise within a fixed time (peak noise detection circuit 1
4) counting circuit for detecting the noise minimum point, and 16 is a control voltage generating circuit for controlling the servo-type polarizer 4, which converts the DC control voltage into a pulse width and outputs it. . The pulse width may be changed directly without using the DC voltage. Reference numeral 17 denotes an RF converter which mixes the output of the audio detection circuit 12 and the output of the FM detection circuit 10 and outputs it as a VHF band television signal. It goes without saying that if the output of the RF converter 17 is supplied to the antenna terminal of a normal television receiver, the image and sound of television radio waves transmitted from the satellite can be viewed.

Next, with reference to FIG. 2 and FIG. 3, a determination means for determining whether or not the signal is a TV signal will be described. In FIG. 2, 18 is a sync separation circuit, 19 is a horizontal oscillation and AFC circuit, and the output pulse is φ in FIG.
₁ includes the horizontal synchronizing signal φ ₀ in the video signal. If the horizontal synchronizing signal φ ₀ is a regular TV signal, (t ₂ ~
t ₁₂ ) = (t _{3 to} t ₁₃ ) = 63,556 μs. Φ ₉₀₀ and φ _{10 in} FIG. 3 are signals obtained from the counter of the frequency dividing circuit 21 which divides the output of the 14.31818 MHz crystal oscillation circuit 20 by 910, and t _{1 to} t ₁₁ = t _{4 to} t ₁₄ = 6.
It is 3.556 μsec. The flip-flop 22 is set at the falling edge of the output pulse φ ₁ and the Q output becomes high level. Therefore, the clear terminal of the counter of the frequency divider 21 becomes high level, and φ ₉₀₀ and φ ₁₀ are output. If φ ₁
Is in phase with the horizontal synchronizing signal φ ₀ and is not pulled to the same frequency, the flip-flop 22 is set at t ₃ ,
Even if the counter of the frequency divider 21 starts frequency division, there is almost no occurrence of t _{12 of} φ ₁ between t ₁₁ and t ₁₄ . Because, when the horizontal oscillation frequency of the horizontal oscillation AFC circuit 19 is selected to be about (15,734-250) Hz during free running, 14,
The time between the outputs t ₁₁ and t ₂ of 900 18318 MHz is t ₂ to t ₁₁ ≈ 62,858 μsec, that is, about 15,
The frequency becomes 909 Hz, and the interval between the 920th t ₁₄ and t ₂ is approximately 64,254 μsec, that is, approximately 15,563 Hz.
If the pull-in range is about ± 200Hz, 15,734 ±
The frequency within 200 = 15,934 to 15,534 Hz is drawn to 15,734 Hz, and φ ₁ is equal to the above 15,9.
It does not become 34 to 15,534 Hz. That is, by dividing the t _2, phi ₁ of t ₁₂ If the result is between t ₁₁ ~t _14, no problem thought to be synchronized with the horizontal synchronizing signal of the normal television signal. On the other hand, the flip-flop 23 outputs φ _{10 in} the output of the frequency divider 21, that is, the output of the crystal oscillator 20 to t.
It is reset by the output when counting ₂ to 10 and the frequency divider 21 when counting the output of the crystal oscillator 20 from t ₂ to 900
The output is set at φ ₉₀₀ . Therefore, in FIG. 3, t ₂ and t
_{If 3} were in phase for the first time, there would be no pulse at t ₁ of φ ₉₀₀ and flip-flop 23 would not be set at t ₁ , so φ ₂ would not go high from t _{2 to} t ₄ . In the case of FIG. 3, φ ₀ and φ ₁ are already synchronized. The Q output of the flip-flop 23 becomes φ _{2 in} FIG. 3, the inverter 25 inverts φ ₁ , and the NAND gate 24 outputs φ ₁ and φ _2.
When both of the above are supplied, the output becomes φ _{3 in} Fig. ₃ ,
If the multivibrator 26 that can be re-triggered is driven at t ₂ , its Q output keeps a high level until t _{17 as} shown in φ ₄ in FIG. 3 (time constant 63,556 μsec.
Choose a larger size). At t ₁₂ , the multivibrator 26 is re-triggered so that the Q output of the multivibrator 26 remains high while φ ₀ and φ ₁ are synchronized. If φ ₀ and φ ₁ are not synchronized, φ ₂ and φ ₁ are not synchronized, φ ₃ is output or not output, and the multivibrator 26 is sometimes triggered, so t _{2 to} t ₁₇
The idea to choose a slightly wider eyes than 1H, when the φ ₀ and φ ₁ is not synchronized, the output Q of the multivibrator 26 is almost at any time low level. That is, when the output of the multivibrator 26 is at a high level, it means that the horizontal synchronizing signal in the regular video signal is detected, and it can be determined that the detection output is a video signal. Since the output pulse of the horizontal AFC circuit 19 does not include noise, if the S / N is such that the AFC operates, it can be determined whether or not it is a video signal. Therefore, it can be seen that the signal is a video signal even if the plane of polarization is slightly deviated. On the other hand, when the Q output of the multivibrator 26 becomes low level, the trailing edge detection circuit 30 detects the end of the high level pulse and resets the flip-flop 22 via the NOR gate 33. Therefore, the counter of the frequency divider 21 stops the frequency division of the output of the crystal oscillator 20. Horizontal AF
Since the output φ ₁ of the C circuit 19 exists at the free-running frequency close to 15,734 Hz as described above even when it is not synchronized with the horizontal synchronizing signal φ ₀ , the flip-flop 2 has a falling edge of φ _1.
2 is set, and the outputs φ ₁₀ and φ _{900 of the} frequency divider 21 appear, but φ ₁ is 15,734-250 = 1 as described above.
At 5,484 Hz, the relationship between φ ₂ and φ ₁ deviates so much that the multivibrator 26 is not triggered for most of the time. When the power is turned on, a power ON pulse is transmitted from the power ON pulse generation circuit 31 to the flip-flop 22 via the NOR gate 33, and the flip-flop 22 is reset. Further, since it is necessary to switch the plane of polarization every time the receiving channel is switched, the flip-flop 22 is reset by causing the circuit 32 to generate a pulse in conjunction with the channel switching. Therefore, the flip-flop 22 is reset for most of the period when the normal video signal is not received.

Next, detection of white peak and black peak noise will be described with reference to FIG. In FIG. 4, 34 is a multivibrator 2.
While Q output of 6 is high level, horizontal pulse φ ₁ is 1/52
A frequency divider that divides the frequency by 5 generates a low-level pulse for 1H and stops counting by the noise counter 40. 35
Is a clamp pulse generation circuit that clamps the pedestal level immediately after the horizontal synchronizing signal in the video signal from the horizontal pulse φ ₁ , 36 is a pedestal clamp circuit that clamps the output of the detection circuit 10, and 37 is a white peak noise detection circuit.
The white peak level of the pedestal clamped video signal is
Since it is constant in the range in which the AGC is operating, the impulse noise of FM appearing further to the white side than the white peak is detected. 38 is FM that goes further to the black side than the pedestal level
It is a black peak noise detection circuit for detecting the impulse noise of. The detection circuits 37 and 38 both convert the detected noise into positive-direction pulses and output them, the OR gate 39 forms a logical sum, and the counter 40 counts the number of noises in both positive and negative directions. The counter 40 counts noise for 524H while the output of the frequency divider 34 is positive.

Reference numeral 41 denotes a comparator, which compares the output of the latch memory 42 and the output of the noise counter 40 when the noise number of the previous frame is stored in the latch memory 42. The number of noise, the 1-2 degree difference because changes from moment to moment, since polarization occurs without changing, for example, the state of the 2 ² or more terminal of the counter 40 latches the memory, and the comparator 4
Compare with 1. The output of the comparator 41 is the noise counter 4
When the output of the noise counter 40 is larger than that of the latch memory 42, the large output is "H" level, and when the output of the noise counter 40 is small, the small output is "H".
It shall be a level. If the comparator 41 is operated only during 1H when the output of the frequency divider 34 is at a low level, the large or small output is output only during this period.
If either large or small is "H", the state is stored in the latch memory 42. This causes the output of the comparator 41 to be written and stored in the latch memory 42 when the output of the NOR gate 43 becomes negative. If the noise counter 40 is composed of a 10-bit binary counter and 2 ° and 2 ′ are not used for comparison, 8-bit comparison is performed, and both the comparator 41 and the latch memory 42 need to be 8-bit. When the small output of the comparator 41 is inverted to "L" by the inverter 44, the output of the AND gate 45 becomes "H" only when the large output is "H". The shift register 46 is a serial input / parallel output shift register having a capacity of 3 bits or more. When the output of the AND gate 45 is read to the shift register 46 at the trailing edge of the “L” pulse for 1H of the output of the frequency divider 34, the noise of that frame is the noise of the previous frame at the end of each frame. When the number increases, "H" is written in the shift register 46. When the plane of polarization is correct, noise is minimized, so when the 3-bit output of the shift register 46 is "H", "L", or "H", the plane of polarization was normal in the previous frame. I understand. The inverter 47 inverts the second bit of the shift register 46 to perform a 3-input AND
When the first bit and the second bit output are added to the gate 48, the output of the AND gate 48 becomes “H” in the frame next to the polarization plane optimum frame, and the fact that the previous frame was the polarization plane optimum is shown. Show.

Reference numeral 55 in FIG. 5 is a voltage sweep circuit. If the sweep speed of the polarization plane control of this circuit is 180 ° / 3 seconds, it will be 1 degree per field, that is, 2 degrees per frame, and will be shifted 2 degrees after 1 frame delay. However, the deviation of 1 to 2 degrees hardly affects the deterioration of the image quality. The influence of 2 times is (1-cos88
It can be almost ignored. With the above, the noise minimum point is A
It has been described that the determination can be made by the output "H" of the ND gate 48.

Next, the polarization plane control voltage generation circuit 16 will be described with reference to FIG. A sample and hold circuit 49 stores the DC voltage level of the AGC detector 11, and samples and holds the output of the AGC detector 11 once per frame by the trailing edge of the output of the frequency divider 34. Reference numeral 50 denotes an analog comparator, which is the leading edge of the output of the frequency divider 34 (or between the leading edge and immediately before the trailing edge).
The outputs of the GC detector 11 are compared, and the output is judged by the judgment circuit 5
Supply to 1 '. The decision circuit 51 'has the same structure as the circuit 51 of FIG. If the AGC voltage has the maximum input voltage and the maximum input voltage, the determination circuit 51 ′ may supply the shift register 46 ′ without inverting the large output of the comparator 50 and inverting the small output thereof. The output of the comparator 50 is "H" when the output of the AGC detector 11 is higher than that of the sample-hold circuit 49, and "H" when the output is low. To do. Therefore, the output of the AND gate 48 'in the judgment circuit 51' becomes "H" level as the voltage indicating the maximum point of the AGC voltage one frame before when the AGC voltage changes to small, large and small. Inverter 52
And flip-flop 53 is set. The flip-flop 53 is reset by the output of the NOR gate 33, and the voltage sweep circuit starts sweeping when the output of the NOR gate 33 becomes low level. Therefore, the voltage of the voltage sweep circuit 55 starts to change, and the polarization After the control voltage or pulse width of the inverter 4 starts to change, first the inverter 5
When the output of 2 goes low, the flip-flop 53
Is set. If the output of the AND gate 48 becomes "H" level after the flip-flop 53 is set,
The output of the AND gate 54 becomes high level, and the voltage sweep circuit 55 stops the voltage sweep. If the flip-flop 53 is set at t _{203 as} shown in FIG.
If the output φ ₁₀₂ of the AND gate 48 does not become high level, the sweep voltage is swept again from t _{301 of} FIG. 6 and stops when the output φ ₁₀₂ of the AND gate 48 becomes “H” at t ₃₀₂ . If φ ₁₀₂ becomes “H” after t ₂₀₃ , φ ₁₀₁ stops increasing or decreasing there.

As for the sweep, as shown in FIG. 6, the rising and falling may have the same gradient, or the same effect can be obtained by unidirectional sweeping from 0 ° to 180 °. If the polarizer 4 uses a motor to rotate the probe, a suitable time after t ₃₀₂ , φ ₁₀₁
The output of may be stopped. If the probe motor is used with a pulse motor, φ ₁₀₁ needs to be converted into a pulse width.

With the configuration as described above, the polarization plane can be set at the correct position. Even if there is a peak of the AGC voltage at a position other than the normal position due to the strong interference wave, the sweep of the polarization plane control voltage is stopped at the point where the white peak noise and the black peak noise are the minimum. Does not happen.

EFFECTS OF THE INVENTION As described above, according to the present invention, the plane of polarization can be automatically set to the correct position without being affected by the interfering wave.

[Brief description of drawings]

FIG. 1 is a block diagram of an automatic polarization plane switching device according to an embodiment of the present invention, FIG. 2 is a block diagram of a video signal discriminating circuit, and FIG. 3 is a time chart for explaining the operation of the video signal discriminating circuit. FIG. 4 is a block diagram of a white and black peak noise minimum point detection circuit, FIG. 5 is a block diagram of a voltage sweep stop determination circuit, and FIG. 6 is a time chart for explaining the operation of FIG. 4 …… Polarizer, 8 …… Mixer (tuner), 9 ……
IFAMP, 10 ... FM detector, 11 ... AGC detector, 13 ... Horizontal AFC circuit, 14 ... Peak noise detection circuit, 15 ... Noise counter, 16 ... Polarization plane control voltage generation circuit.

Claims (1)

[Claims] 1. A polarizer for selecting a polarization plane of a television signal having a vertical or horizontal polarization plane transmitted from a satellite, a low noise converter installed immediately after the polarizer, and the converter. A tuner for inputting an output, an intermediate frequency amplifier for inputting the output of the tuner, an FM detection circuit for inputting the output of the intermediate frequency amplifier, and a white peak noise included in a video signal output from the FM detection circuit. Number and the number of black peak noises, and a noise minimum point detection circuit having a means for detecting the minimum points of these peak noise numbers, and the intermediate frequency amplifier that changes with the change of the polarization plane of the polarizer. An image signal discrimination circuit having means for detecting the AGC voltage and means for detecting the maximum point of the AGC voltage, and a signal output from the noise minimum point detection circuit are input. Then, the function of controlling and fixing the polarization plane of the polarizer so that the peak noise number becomes the minimum point, or the signal output from the video signal discriminating circuit is input and the AGC voltage becomes the maximum point. An automatic polarization plane switching device comprising: a polarization plane control circuit having a function of controlling and fixing the polarization plane of a wave device.