JPH0773195B2 - Auto tuning circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an auto-tuning circuit in a television receiver or the like.

[Prior Art and its Problems] Recently, some television receivers are provided with an auto-tuning function for automatically selecting a reception channel in response to an operation of a channel up / down key. This auto-tuning function is provided with a frequency detection circuit and a tuner tuning voltage control circuit. When the up / down key is operated, the tuner tuning voltage control circuit raises / lowers the tuning frequency of the electronic tuning tuner, When is received, the received frequency is detected by the frequency detection circuit and the AFTH signal and AFTL signal are output to adjust the tuner tuning frequency to the optimum value. At this time, when the up key is operated to raise the tuning frequency of the tuner, the AFTH signal is first output from the frequency detection circuit as shown in Fig. 7 (a), and then at a predetermined interval. AFTL signal is output. In this case, the AFTH signal and the AFTL signal are counted by the AFT counter, and the tuning operation is controlled according to the count value. That is, the counter is
"1" at the falling edge of the AFTH signal as shown in Fig. 7 (a)
Count, and count "2" at the next fall of the AFTL signal. When the counter counts "2",
The tuning speed slows down so that the AFTH signal when the above "1" is counted is output due to the tuning, and then "3" is counted at the falling edge, and the tuning returns again here. To do. Then, when the tuning returns to the output position of the AFTL signal at the time of counting "2" and counts "4" at the trailing edge, the tuning is stopped here. This completes the tuning operation when the channel is up.

When the down key is operated, the AFTL signal is first output from the frequency detection circuit as shown in FIG. 7 (b). Therefore, the AFT counter counts "1" at the trailing edge of the AFTL signal and then counts "2" at the trailing edge of the AFTH signal. When the counter counts "2", the tuning speed decreases and the process returns to the next step. At the next fall of the AFTL signal, "3" is counted, and the tuning operation ends here.

As described above, the tuning control signal is output as two AFTH signals and one AFTL signal for one channel. Conventionally, after confirming the output of the AFTH signal and AFTL signal, the above
The tuning point is set at the position where the AFTL signal is output. However, the position just in the center between the AFTH signal and the AFTL signal is the best tuning point, and the tuning position in the conventional tuning circuit is slightly deviated from the best position.

[Object of the Invention] The present invention has been made in view of the above points, and an object thereof is to provide an auto-tuning circuit capable of setting a tuning position to the best point.

[Points of the Invention] The present invention uses an AFTH signal and an AF by auto tuning.
When the TL signal is detected, the reference voltage of the frequency detection circuit is switched to widen the width of the AFTH signal and the AFTL signal to narrow the interval between the two signals, and the tuning position between the AFTH signal and the AFTL signal. This is set.

First Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings. First, the first embodiment will be described with reference to FIGS. FIG. 1 is a block diagram showing a main part of a television receiver. In the figure, 11 is a television receiving antenna, and the electric wave received by this antenna 11 is an electronic tuning tuner.
Input to 12. The electronic tuning tuner 12 selects a predetermined radio wave from the received radio waves according to the tuning signal Vt from the tuner tuning voltage control circuit 16, converts it into an intermediate frequency A, and inputs it to the television linear circuit 13. This TV linear circuit 13 has an intermediate frequency A from the electronic tuning tuner 12.
Is amplified and detected to separate the video signal, the audio signal, and the sync signal, and the intermediate frequency signal B is output.
The video signal output from the television linear circuit 13 is a display circuit (not shown), the audio signal is an audio circuit (not shown),
The intermediate frequency signal B is sent to the frequency detection circuit 14 and the synchronization signal C is sent to the control circuit 15. The frequency detection circuit 14 is
As will be described later in detail, the intermediate frequency signal B from the television linear circuit 13 is detected to create an AFTH signal and an AFTL signal, which are output to the control circuit 15. Further, a channel up / down signal corresponding to the operation of the channel up / down key is input from the key input unit 17 to the control circuit 15. The control circuit 15 outputs a control signal to the display circuit and the audio circuit in synchronization with the synchronization signal C from the television linear circuit 13, and also a switch switching signal D according to the AFTH signal and the AFTL signal.
Is output to the frequency detection circuit 14. That is, the control circuit 15
Has an AFT counter for counting the AFTH signal and the AFTL signal therein and normally holds the switch switching signal D at the "1" signal level, but when the count value of the AFT counter becomes "2". , The tuning speed is reduced and the switch switching signal D is switched to the "0" signal level. In addition, the control circuit 15 outputs a control signal to the tuner tuning voltage control circuit 16 according to the operation of the channel up / down key of the key input unit 17.

Next, details of the frequency detection circuit 14 will be described with reference to FIG. The Vcc power supply is supplied to the frequency detection circuit 14, and this Vcc power supply is divided into the voltages V1, V2, V3, and V4 by the voltage dividing circuit 20 including the resistors R1 to R5. Above resistance R1
The value of ~ R5 is set to, for example, R1: R2: R3: R4: R5 = 2: 1: 1: 1: 2, and V1 = (5/7) Vcc, V2 = (4/7) Vcc, V3 =
(3/7) Vcc, V4 = (2/7) Vcc. Then, the voltages V1 and V2 divided by the voltage dividing circuit 20 are input to the + terminal of the comparator 25 via the analog switches 21 and 22 as comparison reference voltages, and the divided voltages V3 and V4 are analog switches. Comparator 26 via 23, 24
Is input to the negative terminal of as a comparison reference voltage. The analog switches 21 and 24 are on / off controlled by a switch switching signal D sent from the control circuit 15, and the analog switches 22 and 23 are on / off controlled by a switch switching signal D provided via an inverter 27. It Also,
In FIG. 2, 28 is a frequency discriminator, which is a television linear circuit.
The intermediate frequency signal B given from 13 is discriminated to create an AFT signal, and the negative terminal of the comparator 25 and the comparator
Apply to + terminal of 26. The output of the comparator 25 is the AFTH signal, and the output of the comparator 26 is the AFTH signal.
It is sent to the control circuit 15 as a TL signal.

Next, the operation of the above embodiment will be described. Electronic tuning tuner 12
When the arbitrary channel is selected by, the control circuit 15 sends a "1" signal to the frequency detection circuit 14 as the switch changeover signal D. When the switch switching signal D is "1", in the frequency detection circuit 14 shown in detail in FIG. 2, the analog switches 21 and 24 are turned on and the analog switches 22 and 23 are turned off. As a result, the divided voltage V1 output from the voltage dividing circuit 20 is applied as a reference voltage to the comparator 25 via the analog switch 21, and the voltage V4
Is supplied as a reference voltage to the comparator 26 via the analog switch 24. Now, assuming that the up key is operated in the key input unit 17, the control circuit 15
The tuner tuning voltage control circuit 16 sends an up command from the tuner tuning voltage control circuit 16, and the tuner tuning voltage control circuit 16 sends the tuning signal Vt.
To raise the tuning frequency of the electronic tuning tuner 12. Then, when the TV broadcast wave of the next channel is received due to the increase in the tuning frequency,
This broadcast radio wave is converted into the intermediate frequency A and sent from the electronic tuning tuner 12 to the television linear circuit 13, and further converted into the intermediate frequency signal B by the television linear circuit 13 and sent to the frequency detection circuit 14. The frequency detecting circuit 14 discriminates the intermediate frequency signal B by a frequency discriminator 28 and outputs an S-shaped AFT signal as shown in FIG. 3 (a).
This AFT signal is input to the comparators 25 and 26, and when it becomes larger than the reference voltage V1 as shown in FIG.
Is output as an AFTL signal from. When the up key is operated as above, first the comparator 25
The signal is output, and thereafter, at a predetermined interval, that is, when the AFT signal becomes smaller than the reference voltage V3, the AFTL signal is output from the comparator 26 and sent to the control circuit 15.

Then, the control circuit 15 controls the tuning operation by counting the AFTH signal and the AFTL signal sent from the comparators 25 and 26 by the AFT counter. That is,
As shown in FIG. 4 (a), the control circuit 15 first counts "1" at the falling edge of the AFTH signal and then counts "2" at the falling edge of the AFTL signal. When the count value of the AFT counter reaches "2", the control circuit 15 sends a command to the tuner tuning voltage control circuit 16 to reduce the tuning speed and return to the reverse direction, and at the same time, the switch switching signal D from "1" to "0". Switch to. Therefore, in the frequency detection circuit 14, the analog switches 21 and 24 are turned off and the analog switches 22 and 23 are turned on, the voltage V2 output from the voltage dividing circuit 20 is supplied to the comparator 25, and the voltage V3 is supplied to the comparator 26. It is given as a reference voltage. Therefore, the third
AF output from the frequency discriminator 28 as shown in FIG.
When the T signal is higher than the reference voltage V2, the comparator 25
The AFTH signal is output from the comparator 26, and the AFTL signal is output from the comparator 26 in the range where the AFT signal is smaller than the reference voltage V3. That is, the time width of the AFTH signal and AFTL signal becomes wider, and in the center of the tuning control signal signal,
The output of the AFTH signal and the AFTL signal can be switched at a minute interval t. Therefore, when the reference voltages of the comparators 25 and 26 are switched to V2, the AFTL signal is kept being output from the comparator 26 as shown in FIG. 4 (b). In this state, the tuning is returned to the low channel side at low speed as described above.
When the signal is returned to the center position of the signal and the AFT signal becomes larger than the reference voltage V3, the AFTL signal output from the comparator 26 returns to the high level, and then the AFT signal is left at a minute interval t.
When the signal becomes larger than the reference voltage V2, the AFTH signal output from the comparator 25 falls. The fall of the AFTH signal is counted by the AFT counter, and the count value becomes "3". The control circuit 15 controls the tuner tuning voltage control circuit when the count value of the AFT counter becomes “3”.
Give a control command to 16 to reverse the tuning direction to the high channel side. As a result, the AFTL signal falls from the comparator 26 at a minute interval t, and the trailing edge is detected by the AFTL signal.
The T counter counts and the count value becomes "4". In the control circuit 15, the count value of the AFT counter is "4".
Then, a tuning stop command is given to the tuner tuning voltage control circuit 16 to stop the tuning at that position, and the switch switching signal D is returned to the "1" signal level. In this case, the switch switching signal D may be kept in the "0" signal state as it is even after the tuning operation is completed, and may be switched to the "1" signal level when the channel up / down key is operated. As described above, the tuning position of the selected channel can be stopped at the center of the AFT signal, that is, the tuning best point.

Further, when the down key is operated in the key input unit 17, the AFT counter in the control circuit 15 is cleared, and a tuning down command is sent from the control circuit 15 to the tuner tuning voltage control circuit 16, which causes the tuning of the tuner. The down operation is performed. At this time, the switch changeover signal D sent from the control circuit 15 to the frequency detection circuit 14 is at the "1" signal level, and the comparator 25 receives the voltage.
V1 is supplied as a reference voltage via the analog switch 21, and the voltage V4 is supplied to the comparator 26 as a reference voltage via the analog switch 24. Therefore, with the tuning down operation, the AFTL signal is first output from the comparator 26 as shown in FIG. 5 (a), and the AFT counter counts "1" at the trailing edge. At this point, the tuning down operation is continued as it is, so the AFTH signal is then output from the comparator 25, and the content of the AFT counter is incremented to "2" at the falling edge. When the count value of the AFT counter becomes “2”, the control circuit 15 sends a command to the tuner tuning voltage control circuit 16 to reduce the tuning speed and return to the reverse direction (tuning up), and the switch switching signal D
Switch from "1" to "0". Therefore, the frequency detection circuit 14
In, the analog switches 21 and 24 are turned off and the analog switches 22 and 23 are turned on, and the voltage V2 output from the voltage dividing circuit 20 is applied to the comparator 25 and the voltage V3 is applied to the comparator 26 as a reference voltage. As a result, the time width of the AFTH and AFTL signals becomes wider as described above, and the AFTH signal is
AFTL signal output can be switched. Therefore, at the time when the reference voltages of the comparators 25 and 26 are switched to V2, as shown in FIG.
The AFTH signal is kept output. In this state, the tuning is returned to the high channel side at a low speed as described above, but when it is returned to the center of the AFT signal and the AFT signal becomes smaller than the reference voltage V2, the AFTH signal output from the comparator 25 becomes high level. After that, when the AFT signal becomes smaller than the reference voltage V3 after a slight interval t, the AFTL signal output from the comparator 26 falls. The fall of the AFTL signal is counted by the AFT counter, and the count value becomes "3". Control circuit
When the count value of the AFT counter becomes “3”, 15 gives a tuning stop command to the tuner tuning voltage control circuit 16 to stop the tuning at that position, and also returns the switch switching signal D to the “1” signal level. .
As described above, even when the channel is down, the tuning position of the selected channel can be stopped at the center of the AFT signal, that is, the best tuning point.

Second Embodiment of the Invention Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 6 shows the details of the frequency detection circuit 14 in FIG. In the second embodiment, the voltage dividing circuit 20 'is composed of resistors R6, R7, R8 and R9, and the resistor R6 and
The divided voltage V5 between R7 and R7 is applied to the + terminal of the comparator 25 as a reference voltage, and the divided voltage V6 between the resistors R8 and R9 is applied to the-terminal of the comparator 26 as a reference voltage. In this case, the voltage dividing circuit 20 'sets the resistors R6 to R9 in a relationship of, for example, R6: R7: R8: R9 = 2: 1: 1: 2. An analog switch 31 is connected in parallel to the resistor R7, and a switch switching signal D from the control circuit 15 is given to the gate of the analog switch 31 via an inverter 32.

The frequency detection circuit 14 configured as described above is a control circuit.
When the "1" signal is given as the switch changeover signal D from 15, the analog switch 31 is turned off, the divided voltage V5 between the resistors R6 and R7 is given to the comparator 25, and the resistors R6 and R7 are given. The divided voltage V6 during the period is given to the comparator 26 as a reference voltage. In this case, the divided voltage V
5 and V6 correspond to the voltages V1 and V4 in the first embodiment. When a "0" signal is given from the control circuit 15 as the switch switching signal D, the output of the inverter 32 becomes "1", the analog switch 31 is turned on, and both ends of the resistor R7 are short-circuited. Therefore, the Vcc voltage is divided by the resistors R6, R8, R9, and the divided voltages V5, V6 generated across the resistor R8 are supplied to the comparators 25, 26 as reference voltages. The voltages V5 and V6 in this case are the reference voltage V in the first embodiment.
Equivalent to 2, V3. As a result, the frequency detection circuit 14 shown in FIG. 6 can perform the same operation as that of the first embodiment with a simple circuit configuration.

As described in detail above, according to the present invention, the AFTH signal and the AFTL signal are
When a signal is detected, the reference voltage of the frequency detection circuit is switched to widen the width of the AFTH signal and AFTL signal to narrow the interval between both signals and set the tuning position between the AFTH signal and the AFTL signal. By doing so, the tuning position at the time of channel selection can be set to the best point, and the image quality can be improved.

[Brief description of drawings]

1 to 5 show a first embodiment of the present invention. FIG. 1 is a block diagram showing a schematic configuration of the whole, and FIG. 2 is a diagram showing details of a frequency detection circuit in FIG. Third
The figure is a timing chart for explaining the output operation of the AFTH signal and the AFTL signal in the frequency detecting circuit,
5 and 5 are timing charts for explaining the operation of the same embodiment, FIG. 6 is a diagram showing details of the frequency detecting circuit in the second embodiment of the present invention, and FIG. 7 is a conventional auto-tuning circuit. 6 is a timing chart for explaining the operation. 11 …… antenna, 12 …… electronic tuning tuner, 13 …… television linear circuit, 14 …… frequency detection circuit, 15 …… control circuit, 16 …… tuner tuning voltage control circuit, 17 …… key input section, 20, 20 '... voltage divider, 21-24, 31 ... analog switch, 25, 26 ... comparator, 28 ... frequency discriminator.

Claims (1)

[Claims] 1. A voltage dividing means for dividing a constant voltage by a resistor to generate a plurality of reference voltages, a reference voltage switching means for switching a plurality of reference voltages divided by the means according to a switching signal, and a tuning operation. According to the frequency discriminator that outputs the AFT signal from the intermediate frequency signal, the AFT signal output from the frequency discriminator is compared with the reference voltage switched by the reference voltage switching means, and the AFTH signal and the AF
When the tuning direction is reversed by the first and second comparators which output the TL signal at a predetermined interval, the means for reversing the tuning direction by detecting the AFTH signal and the AFTL signal outputted from the comparator. Means for switching the reference voltage supplied from the reference voltage switching means to the first and second comparators so that the AFTH signal and the AFTL signal are at a minute interval, and after the reference voltage is switched by this means, An auto-tuning circuit having means for setting a tuning stop point between the AFTH signal and the AFTL signal.