GB2057214A

GB2057214A - Tuning system

Info

Publication number: GB2057214A
Application number: GB8026960A
Authority: GB
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1979-08-27
Filing date: 1980-08-19
Publication date: 1981-03-25
Also published as: IT8024217A0; IT1132434B; DE3032321A1; GB2057214B; FR2469832A1

Abstract

A tuning system for a television receiver includes a phase locked loop (PLL) (5, 19, 21, 23, 25, 27, 29) and an automatic fine tuning (AFT) means (41) which are selectively enabled to operate to tune the receiver to nonstandard as well as standard radio frequency (RF) carriers which may be provided by cable and master antenna systems. After the selection of a new channel (CHANGE), the operations of the PLL and AFT configurations are sequentially enabled by a mode selection means (43). A first counter means (19, 21) causes said PLL means to tune an RF carrier associated with a selected channel. Signal processing means (11) are responsive to the RF carrier for producing an information response and second counter means (53, 59) are responsive to the sequential enabling of said PLL and AFT means a predetermined number of times to inhibit said information response. A channel selection means (35) may step the tuner to the next channel, or in another embodiment the receiver may be switched off. <IMAGE>

Description

SPECIFICATION Tuning system The present invention relates to tuning systems.

A wide variety of "Search" or "signal seeking" tuning systems for radio and television receivers are known which provide for automatically tuning only those channels which have unacceptable reception characteristics. Such tuning systems typically include a number of signal detectors for determining when a received RF carrier has acceptable reception characteristics.For example, a search type tuning system for a television receiver may include: an AFT (automatic fine tuning) detector for determining when an IF carrier derived from the received RF carrier has a frequency within a predetermined range of its desired value; and ACG (automatic gain control) detector for determining when the received RF carrier has an amplitude greater than a predetermined value; and a synchronization detector to determine when synchronization pulses derived from the received RF carrier has the proper frequency.

Tuning systems are also known which include a memory having memory locations associated with each channel in a tuning range for storing information as to whether the associated station or channel is preferred or not. Such "memory" type tuning systems may be utilized as an alternative to the "search" type tuning systems to select only those channels with acceptable reception characteristics in a given location.

Both "search" and "memory" type tuning systems require a considerable amount of complex and expensive circuitry, in addition to the basic tuning system for tuning each channel in a tuning range, for tuning only those channels with acceptable reception characteristics. Thus, there is a need for a tuning system which requires only a relatively small amount of circuitry in addition to the basic tuning system for tuning only channels with acceptable reception characteristics.

Additionally, there is a need for a tuning system which will automatically turn itself off.

Timers are known for turning electronic equipment on and off, such arrangements are utilized to turn the receivers on at predetermined times when a user wishes to be awakened and to turn the receiver off at predetermined times when stations go "off-the-air". The latter feature is useful as an energy conservation and safety measure should a user fall asleep.

Apparatus are also known for turning off receivers in the absence of any RF carriers with acceptable reception characteristics. Such apparatus employ signal detectors for evaluating properties of certain signals derived from received RF carriers.

Automatic turn-off apparatus of the timer and signal evaluation types require the addition of a considerable amount of special circuitry to receivers. Thus, there is a need for automatic turn-off apparatus which may be incorporated in receivers with only a small amount of additional circuitry.

The present invention is an improvement to the type of electronic tuning system which includes PLL means for tuning a tuner to standard frequencies associated with respective channels, AFT means for tuning the tuner to reduce deviations between the frequency of an IF carrier generated by the tuner and its desired or nominal value that may arise due to, e.g., offsets in the frequencies of received RF carriers, and mode selection means for selectively applying PLL and AFT control signals to the tuner. In this type of electronic tuning system, the operation of the PLL means is enabled after a new channel is selected and the operation of the AFT means is enabled after the PLL means has completed its operation.A first counter means causes saidPLL means to tune an RF carrier associated with a selected channel and signal processing means responsive to the RF carrier produces an information response.

In accordance with the principles of the present invention, second counter means are provided in the above described type of electronic tuning systems for inhibiting the information response when the mode selection means has enabled one of the PLL and AFT means a predetermined number of times.

In the drawings: Figure 1 shows in block diagram form a television receiver including a tuning system in accordance with the principles of the present invention; Figure 2 shows in logic diagram form an implementation of a portion of the tuning system of Figure 1; and Figure 3 shows in block diagram form a television receiver including automatic turn off apparatus in accordance with the principles of the present invention.

A television receiver shown in Figure 1 includes a tuner 1 comprising a radio frequency (RF) unit 3, a voltage controlled local oscillator (VCLO) 5 and a mixer 7 for heterodyning an RF signal provided by RF unit 3 and a local oscillator signal provided by VCLO 5 to generate an intermediate frequency (IF) signal having picture and sound carriers. An IF signal processing unit 9 filters and amplifies the IF signal. A signal processor unit 11 (video processing unit 1 lea and sound processing unit 11 b in Figure 3) develops in a picture tube 13 and speaker 15 respective visual and audible responses from respective IF signal components. RF signals are applied to tuner 1 through an RF signal source 17 which may, e.g., be a master antenna or cable installation.Since such installations may not as strictly regulate (such as by the Federal Communications Commission in the United States) as broadcast stations, the RF signals they provide may have nonstandard frequency carriers which are offset in frequency with respect to respective standard frequency carriers transmitted by broadcast stations.

The tuning system which constitutes the remaining portion of the television receiver shown in Figure 1 generates tuning control voltages for controlling by VCLO 5 and the frequency response of RF unit 3 so that the receiver can be tuned to nonstandard as well as standard frequency RF carriers. The tuning system included is generally of the same type as is disclosed in U.S. patent 4,031,549, hereby incorporated by reference.The tuning system includes: a phase locked loop (PLL) configuration for generating a first tuning control voltage for causing RF unit 3 and VCLO 5 to be tuned to standard frequencies corresponding to the standard frequency RF broadcast carriers associated with elected channels; an AFT configuration for generating a second tuning control voltage for causing RF unit 3 and VCLO 5 to be tuned so as to reduce deviations between the frequency of the picture carrier of the IF signal and its desired or nominal value, e.g., in the United States, 45.75 MHz, which may occur due to the reception of nonstandard frequency RF carriers; and a mode selection apparatus for selectively causing the first and second tuning control voltages to be applied to tuner 1.

The PLL configuration includes: a fixed frequency dividerf . K) 19 and a programmable frequency divider (-N) 21 for dividing the frequency of the local oscillator signal generated by VLCO 5 to derive a frequency-divided version of the local oscillator signal; a crystal oscillator 23; a fixed frequency divider (-:R) 25 for dividing the frequency of the output signal of a crystal oscillator 23 to generate a frequency reference signal; and a phase comparator 27 for generating pulse error signals having polarities and durations respectively representing the sense and magnitude of the phase and/or frequency deviation between the frequency-divided local oscillator signal and the frequency reference signal.

The error pulses are selectively applied to an active low pass filter (LPF) or integrator 29 by the mode selection apparatus to be described below. In response to the error pulses, LPF 29 generates the first tuning control voltage for tuner 1. The operation of the PLL configuration is enabled when the error pulses are applied to LPF 29. During the operation of the PLL configuration, the magnitude of the first tuning control voltage changes in accordance with the phase and/or frequency deviation between the frequency-divided local oscillator signal and the frequency reference signal to reduce the deviation.When the deviation has been minimized, the frequency of the local oscillator signal, fLO, will have a programmed value related to the frequency of the crystal oscillator signal, fxTAL, by the following expression: fLO = NRfxTAL (1) The division factors K and R are selected to determine the operating frequency range of the PLL configuration. Desirably, the factor RfxTAv is made equal to 1 MHz, so that the programmable division factor of divider 21, N, is equal, in MHz, to the frequency of the local oscillator signal.

The value of N is controlled by a control unit 31 in response to binary signals representing in coded format the channel number of the selected channel which are generated by and stored in a channel number register 33 under the control of a channel selection arrangement generally indicated by reference number 35.

The binary signals stored in channel number register 33 are also applied to a channel number display unit 37 and a band decoder 39. Band decoder 39 determines the frequency band in which the selected channel resides from the binary signals representing the channel number of the selected channel. Band decoder 39 generates a VL signal when the selected channel is in the low VHF band, i.e., channels 2-6; a VH signal when the selected channel is in the high VHF band, i.e., channels 7-13; and a U signal when the selected channel is in the UHF band, i.e., channels 14-83. The VL, VH and U signals control the selection of respective inductors (not shown) of tuned circuits (not shown) of RF unit3 and VCLO 5 to control the tuning range of the tuned circuits.Each tuned circuit includes a voltable variable capacitance or varactor diode which determines the center frequency of the tuned circuit in response to the first and second tuning control voltages.

The AFT configuration includes an AFT discriminator 41 of the conventional type for generating an AFT signal having a generally s-shaped amplitude versus frequency characteristic representing the magnitude and sense of deviation of the frequency of the IF picture carrierfrom its desired or nominal value, e.g., 45.75 MHz. The AFT signal is selectively applied to LPF 29 by the mode selection apparatus. In response, LPF 29 generates the second tuning control voltage. The operation of the AFT configuration is enabled when the AFT signal is applied to LPF 29.During the operation of the AFT configuration, the frequency of the local oscillator signal is adjusted from its standard value for the selected channel to correct for any deviations of the frequency of the IF picture carrier from 45.75 MHz due to corresponding offsets of the frequency of the received RF carrier.

The mode selection apparatus includes a mode switch 43 which may comprise a double throw, single pole electronic switching device and a mode control unit 45 for controlling the "position" of mode switch 43.

Mode control unit 45 includes: a flip flop (not specifically shown) for generating a MODE control signal having a first logic level for causing mode switch 43 to apply the error pulses generated by phase comparator 27 to LPF 29 and a second logic level for causing mode switch 43 to apply the AFT signal generated by discriminator 4 to LPF 29; and combinational logic (not specifically shown) for controlling the state of the flip flop in response to signals generated by channel selection arrangement 35 a lock detector 47 and an offet detector 49 in response to the depression of "channel up" or "channel down" pushbuttons, 73, 75.

When a new channel is selected, as will be described below, channel selection arrangement 35 generates a CHANGE pulse. In response to the CHANGE pulse, the MODE control signal is set to its first level. In response to the first level, which will hereinafter be referred to as the PLL enable level, mode switch 43 applies the error signal generated by phase comparator 29 to LPF 29 and thereby enables the operation of the PLL configuration. When the deviation between the frequency divided local oscillator signal and frequency reference signal has been substantially minimized, the pulses of the error signal generated by phase comparator 27 will have relatively short durations. This occurrence is detected by a lock detector 47 which responds by generating a LOCK signal. In response to the LOCK signal, the MODE control signal is set to its second level.In response to the second level, which will hereinafter be referred to as the AFT ENABLE level, mode switch 43 applies the AFT signal generated by discriminator 41 to LPF 29 and thereby enables the operator of the AFT configuration.

At any time after the initiation of the arrangement, should the frequency of the local oscillator signal be offset from the value established during the operation of the PLL configuration by a predetermined amount, e.g., 1.25 MHz, offset detector 49 detects the occurrence and generates an OFFSET signal. In response to the OFFSET signal, the MODE control signal is reset to its PLL level thereby terminating the operation of the AFT configuration and reestablishing the operation of the PLL configuration. Local oscillator frequency offsets greater than 1.25 MHz are to be avoided since such offsets approach the 1.5 MHz separation between the frequency of the picture carrier of the present channel and the frequency of the sound carrier of the lower adjacent channel.

Since certain cable and master antenna installations provide nonstandard frequency RF carriers offset in frequency from respective standard frequency carriers offset in frequency from respective standard frequency carriers by as much as +2.5 MHz and since conventional AFT discriminators which may be employed as AFT discriminator 41 are not typically capable of generating an AFT signal for reliably correcting deviations between the frequency of the IF picture carrier and 45.75 MHz as large as +2.5 MHz, the tuning system includes a "stepping" arrangement 51 for incrementally changing the value of N in response to the OFFSET signal when the operation of the PLL configuration is reinitiated.

Specifically, in response to the first generation of the OFFSET signal during the first AFT operating cycle after a new channel is selected, a step counter 53, coupled to t N control unit 31, is set to a predetermined state which causes the value of N to be increased by 1 with respect to the standard value for the selected channels and the operation of the PLL configuration is reinitiated. Accordingly, the frequency of the local oscillator signal is increased by 1 M Hz with respect to the standard frequency for the selected channel.

Thereafter, when the LOCK signal is again generated, the operation of the AFT configuration is initiated for the second time. In this manner, the tuning system is capable of locating and tuning nonstandard frequency carriers which may be offset from respective standard frequency carriers by as much as +2.25 MHz (i.e., 1+1.25 Mhz).

If no RF carrier is located for the increased value of N, a second OFFSET signal will be generated during the second AFT operating cycle when the frequency of the local oscillator signal is caused to be more than 1.25 MHz from the value established previously under the control of the PLL configuration. In response to the second generation of the OFFSET signal, step counter 53 is set to a state causing the value of N to be decreased by 1 with respect to its standard value for the selected channel and the operation of the PLL configuration is again reinitated. Accordingly, the frequency of the local oscillator signal is decreased by 1 MHz with respect to the standard frequency for the selected channel. Thereafter, when the LOCK signal is again generated, the operation of the AFT configuration is initated for the third time.In this manner, the tuning system is capable of locating and tuning nonstandard frequency carriers which may be offset from respective standard frequency carriers by as much as -2.25 MHz (i.e., -1 -1.25 MHz).

Thus, by first increasing and then decreasing the value of N the tuning system is capable of locating and tuning an RF carrier having a frequency within a range of t2.25 MHz of the standard frequency for the selected channel. It is noted that, the value of N is first increased rather than first decreased to reduce the possibility of tuning the sound carrier of the lower adjacent channel. While in the embodiment of Figure 1, the increments of N are equal to 1, other increments less than the difference between values of N for adjacent channels may be utilized.

The reception of an RF carrier may be temporarily interrupted, e.g., when an airplane passes over the reception area. When the RF carrier is again received, it is desirable that the value of N be the same as it was before the reception was interrupted. Atimer 55 and an AND gate 57 are provided for this purpose.

Specifically, in response to the generation of a CHANGE pulse when a new channel is selected, timer 55, which may comprise a monostable multivibrator, generates a positive going pulse having a duration longer than the time required to complete the three alternate operating cycles of the PLL configuration and the AFT arrangement. The positive going pulse enables AND gate 57 to apply the OFFSET signal to the clock (C) input of step counter 53. After the positive-going pulse terminates, AND gate 57 is disabled from applying the OFFSET signal to step counter 53. As a result once an RF carrier has been located and tuned, the value of N is maintained.

The present tuning system is coupled to signal processing circuitry for producing an information response in response to the tuning of the selected RF carrier. If no RF carrier is located for the selected channel, channel selection arrangement 35 (including elements 33,61,63,65,67,69,71,73 and 75) inhibits the information response for the selected channel and causes the selection of the next channel in sequence.

More specifically, a step decoder 59 determines when the OFFSET signal is generated for the third time during the third operational cycle of the AFT arrangement by examining the state of step counter 53 (as will be explained in more detail with reference to Figure 2) and, in response, generates a high logic level SEARCH signal. The SEARCH signal is applied to channel selector arrangement 35 to cause the contents of channel number register to be increased to the value corresponding to the next higher channel number as will now be described.

Channel number register 33 comprises a presettable up/down counter with "jam" inputs, such as the CD 4029 integrated circuit available from RCA Corporation, Somerville, New Jersey, United States of America (not specifically shown) for each of the two digits of the channel number. When the receiver is turned on, a power up detector 61 determines when a supply voltage generated by the receiver's power supply (not specifically shown) attains a predetermined threshold level and, in response to this occurrence, generates a positive-going POWER UP pulse.The POWER UP pulse causes binary signals representing channel number 02, i.e., the lowest channel number, developed by means of appropriate connections to sources of voltages corresponding to the high and low logic levels within a logic array 63 to be applied to the "jam" (J) inputs of the up/down counters of channel number register 33. In addition, the POWER UP pulse is applied via an OR gate 65 to the set (S) input of a set reset flip flop (FF) 67 causing the latter to be set. In response to the resulting development of a high logic level of the Q output of FF 67, channel number register 33 is enabled to count in increasing order. The POWER UP pulse also causes an OR gate 69 to generate a CHANGE pulse. As a result, the operation of the PLL configuration is initiated with the value of N set to the standard value associated with channel number 02.

If no RF carrier has been located and tuned by the third operational cycle of the AFT arrangement, as earlier noted, an OFFSET signal will be generated during the third AFT operational cycle when N has a value 1 less than the standard value. In response, step counter 53 will be set to its initial state, i.e., the state corresponding to the standard value of N. Step decoder 59 detects this occurrence and generates a positive-going SEARCH pulse. In response to the positive-going SEARCH pulse, an OR gate 71 generates a positive-going CLOCK signal and OR gate 69 generates a CHANGE pulse. The CLOCK pulse is applied to the clock (C) input of channel number register 33 and thereby causes its contents to be increased to a value corresponding to the next higher channel number, i.e., channel 03.Thereafter, the above described operation is repeated for channel number 03 and for successive higher channel numbers until a RF carrier is located and tuned.

After the receiver is turned on and the first RF carrier has been located and tuned in the aforesaid manner, a new higher channel may be selected by a user by momentary depression of a CH. UP (channel up) pushbutton 73 and a new lower channel may be selected by momentary depression of a CH. DN (channel down) pushbutton 75. The depression of pushbutton 73 causes its normally opened contacts to be closed thereby applying a positive voltage +V corresponding to the high logic level to OR gate 65. As a result, a high logic level is applied to the set (S) input of FF 67 and channel number register 33 is enabled to count in increasing channel number order. The depression of pushbutton 75 causes its normally opened contacts to be closed thereby applying voltage +V to the reset (R) input of FF 67.As a result, FF 67 is reset and channel number register 33 is enabled to count in decreasing channel number order. In addition, when either of pushbuttons 73 or 75 is depressed, OR gate 71 generates a CLOCK signal which causes the contents of channel number register 33 to be changed to the next channel number in the order selected and OR gate 69 penetrates a CHANGE signal thereby initiating the operation of the PLL configuration with the standard value of N for the new channel number. Thereafter, the search operation as described above occurs in the order determined by the state of FF 67 until an RF carrier located and tuned.

Logic implementations of step counter 53 and step decoder 59 are shown in Figure 2 in which portions also shown in Figure 1 have the same reference numbers. Step counter 53 includes D (data) flip flops 77 and 79 and a NOR gate configured as shown to cyclically count through three states in response to successive generations of the OFFSET signal. The table below lists the states in the order they are generated and the incremental change in N to which they correspond.

State 0 output of FF 77 0 output of FF 79 Increment 1 0 1 0 2 0 0 +1 3 1 0 -1 Step counter 53 is set to state 1 in response to the CHANGE pulse.

Step decoder 59 includes a S-R (set-reset) FF 84 and an AND gate 86 configured as shown to generate a positive-going SEARCH pulse when the Q output of FF 79 attains the high logic level after the 0 output of FF 77 has attained the high logic level, i.e., in response to the third generation of the OFFSET signal. FF 79 of decoder 55 is reset in response to the CHANGE pulse.

Programmable divider 21 includes counters and comparators (not specifically shown). The comparators determine when N periods of the output signal of fixed divider 19 have occurred. Control unit 31, which may include a ROM (read only memory), sets the value to which the comparators compare the contents of the counters. In response to the 0 output signals of FFs 77 and 79, the value of control unit 31 augments the comparison values for the standard value of N.

Various portions of the tuning system that has been described (exceptforthe portions having to do with the generation and use of the SEARCH signal) may be implemented in the manner disclosed in the aforementioned U.S. patent 4,109,283.

Figure 3 shows a block diagram of a television receiver including automatic turn off apparatus. Elements of Figure 3 having reference numerals similar to elements in Figure 1 operate in a similar manner. As shown in Figure 3 various functions of the receiver may be controllable by means of a remote control system comprising a remote control transmitter 20 and a remote control receiver 22. Specifically, remote control transmitter 20 is a battery powered unit which selectively transmits frequency encoded ultrasonic signals for increasing and decreasing the number of the channel to which the receiver is tuned in response to the depression of the respective ones of four momentary pushbuttons 24a-24d.In addition, the receiver may be turned off by depressing the pushbutton for decreasing the volume until a minimum level is reached; and the receiver may be turned on by depressing the pushbutton for increasing the volume when the receiver is off, as will be more fully described below.

Remote control receiver 22 is powered by a standby power supply 26 and includes an input unit 28 for converting the ultrasonic signals to corresponding electrical signals and a decoder 30 for decoding the frequency encoded electrical signal to generate respective "up" (U) and "down" (D) control signals for a volume control unit 32 and the channel selection unit arrangement 35.

Volume control unit 32 includes an up/down counter (not specifically shown) for storing binary signals representing the volume level and a digital-to-analog converter (not specifically shown) for converting the contents of the up/down counter to a VOLUME gain control voltage. The gain control voltage determines the gain of an output stage (not specifically shown) of sound processing unit 11 band thereby determines the volume level. In response to the depression of the "volume up" or the "volume down" pushbutton, the contents of the up/down counter are increased or decreased and the volume level is changed accordingly.

In addition, when the VOLUME gain control voltage is caused to have an amplitude corresponding to a minimum volume level in response to the depression of the "volume down" pushbutton, a threshold detector 38 causes a relay drive transistor 40 to be nonconductive. As a result, the contacts of a relay 42 are opened and the AC line is decoupled from a main power supply 44 for the signal processing portion 2 of the receiver and the receiver is turned off. When the receiver is off, after the volume gain control voltage is caused to have a predetermined amplitude above that corresponding to the minimum volume level in response to the depression of the "volume up" pushbutton, threshold detector 38 causes relay drive transistor 40 to be conductive. As a result, the contacts of relay 42 are closed and the receiver is turned on.

Channel selection unit 35 includes an up/down counter (not specifically shown) for storing binary signals representing the channel number of the channel to which the receiver is tuned by tuning control system 10.

In response to the depression of the "channel up" or "channel down" pushbuttons, the contents of the channel number counter are increased or decreased and the channel number is changed accordingly.

The remote control portions of the receiver so far described may be implemented in the same fashion as corresponding portions of CTC-93 television receivers with remote control provisions manufactured by RCA Corporation, Indianapolis, Indiana, United States of America. CTC-93 receivers are described in "RCA Service Data", File 1978, C-7 published by the above-mentioned RCA Corporation.

As described below, the PLL and AFT arrangements are advantageously employed in a dual capacity in conjunction with the volume control apparatus to inhibit an information response of the receiver for instance by turning the receiver off when the RF carrier for the selected channel is absent of a carrier, the PLL and AFT configurations are alternately enabled. A circuit responsive to the mode control signal determines when a number of alternate operating cycles of the two configurations has occurred and causes the VOLUME gain control receiver to be decreased to the level at which the receiver is turned off.

As previously noted, it is possible that the reception of an RF carrier may be temporarily interrupted, e.g., when an airline passes over the reception area. It is also possible, although not highly likely, for the reception of the RF carrier for a selected channel to be temporarily interrupted for a short time just after a channel is selected. It is most likely for an RF carrier to be located and tuned with the standard value of N for the selected channel rather than the value of N increased or decreased by 1. Accordingly, counter 53 is returned to, and thereafter maintained at, a state corresponding to the standard value of N for the selected channel in response to a third generation of the OFFSET signal during the predetermined time established by timer 55 in anticipation of the reestablishment of the reception of the RF carrier for the selected channel.

If an RF carrier is located within the +2.25 range, the operation of the AFT configuration will be maintained.

Accordingly, the MODE signal will remain at its AFT or high level. If no RF carrier is located, the operations of the PLL and AFT configurations continue to be alternately reinitiated. Accordingly, the MODE signal will alternately change from its PLL or low level to its AFT or high level. The duration of the PLL or low level of the MODE signal is relatively long compared to the duration of the AFT or high level of the MODE signal since the response time of the AFT configuration is relatively short compared to the predetermined time before mode control unit 45 enables the operation of the AFT configuration after the generation of the LOCK signal.

In another embodiment of the present receiver, apparatus is provided for turning the receiver off should the RF carrier for a selected channel be lost and thereafter remain absent for a predetermined time, e.g., when a broadcast station goes "off-the-air" which advantageously employs the MODE signal. Specifically, the MODE signal is applied to a counter circuit including a capacitor 76 through a resistor 78. If the operation of the AFT configuration is maintained, indicating that an RF carrier is present, an ON/OFF control voltage developed across capacitor 76 is maintained art a high logic level in response to the maintenance of the MODE signal at the high or AFT level.In response to the high logic level ON/OFF control voltage developed across capacitor 76, an INVERTER 80 develops a low logic level at its output which renders a NPN transistor 81 nonconductive. The collector to emitter path of transistor 81 shunts the control line between decoder 30 and the "volume down" input of volume control unit 32. As long as transistor 81 is nonconductive, the voltage at the "volume down" control line is maintained at a high logic level (except by virtue of user control) and the volume level, and correspondingly, the on/off status of the receiver remains unaffected.

If the operation of the AFT configuration is not maintained but alternates with the operation of the PLL configuration, indicating the absence of an RF carrier, the voltage across capacitor 76 begins to decrease.

Since, as noted above, the duration of the low level of the MODE signal is relatively long compared to duration of the high level, capacitor 76 is discharged in response to the alternate generation of the low of PLL level of the MODE signal. If this situation continues for a long time, dependent on the time constants associated with capacitor 76, resistor 78 and the input circuitry of INVERTER 80, capacitor 76 will be discharged and the ON/OFF control voltage is, as a result, caused to be at the low logic level. Thus, capacitor 76 operates effectively as a counter, providing an indication after the PLL and AFT configurations have been enabled a predetermined number of times.

At the point the control voltage is at the low logic level, INVERTER 80 will generate a high logic level and transistor 81 will, as a result, be rendered conductive. In response, the "volume down" line will be caused to be at a low logic level and the VOLUME gain control voltage generated by volume control unit 32 will decrease. When the VOLUME gain control reaches the amplitude corresponding to the minimum volume level, the receiver will be turned off by means of threshold detector 38, relay drive transistor 40 and relay 42 as was previously described.

An initialization network including a diode 83 and an NPN transistor 85 ensure that the ON/OFF control voltage developed across capacitor 76 is at the high logic level when the receiver is initially turned on. A positive supply voltage generated by standby power supply 26 is applied to capacitor 76 through diode 83. If this were not done, capacitor 76 would be initially discharged and transistor 81 would be rendered conductive as soon as the receiver was turned on and, as a result, by the action of conductive transistor 81 and the "volume down" control line, the receiver would again be turned off.

Transistor 85 is rendered conductive when the receiver is turned on when a supply voltage developed by main power supply 44 is applied to its base. As a result, diode 83 is rendered non-conductive because the anode of diode 83 is connected to ground through the conductive collector to emitter path of transistor 85.

Accordingly, the positive supply voltage generated by standby power supply 26 is decoupled from capacitor 76 and the voltage developed across capacitor 76 is thereafter dependent upon the MODE signal.

Thus, there has been described a tuning system of the type in which PLL and AFT configurations are selectively enabled to control a tunerfortuning standard and nonstandard made of a signal manifesting the selective operation of the configurations to cause a new channel to be selected if an RF carrier is not located for a previously selected channel by the end of a predetermined number of alternate operating cycles of the two configurations. In addition, in the described tuning system, dual use is also advantageously made of a counting arrangement for counting the number of times the operation of the AFT configuration is terminated to determine the programmed frequency to be established by the PLL configuration during operating cycles of the PLL configuration following operating cycles of the AFT configuration to determine when a new channel should be selected.

While the tuning system of Figure 1 includes provisions, specifically, increment control unit 51, for handling nonstandard frequency RF carriers which are offset from respective standard frequency carriers by more than the fine tuning range of conventional AFT discriminators, such provisions may be omitted where the offsets are not so large. In this case, the OFFSET signal may be directly employed as the SEARCH signal by applying the OFFSET signal to OR gate 71 is as indicated by phantom conductor 87. With this configuration, a new channel will be selected after the first generation of the OFFSET signal. In addition, other signals manifesting the termination of the AFT operating mode, such as the MODE control signal generated by mode control unit 45, may be employed to cause the contents of channel number register 33 to be changed until an RF carrier is located and tuned. In addition, other signals manifesting the termination of the AFT operating mode, such as the OFFSET signal terminated by offset detector 49 may be employed to cause the receiver to be turned off when the RF carrier for a selected channel is absent for a predetermined time. These and other modifications are intended to be within the scope of the present invention as defined by the following claims.

Claims

1. Apparatus for selectively tuning a receiver to any one of a plurality of RF carriers assiociated with respective channels, comprising: local oscillator means for generating a local oscillator signal; mixer means for combining a selected one of said RF carriers with said local oscillator signal to derive an IF signal having at least one carrier with a nominal frequency value; phase locked loop (PLL) means for selectively controlling said local oscillator means when enabled to operate to cause said local oscillator signal to have a programmed frequency substantially equal to the product of a programmable factor and the frequency of a frequency reference signal; programmable factor control means for determining programmable factor in accordance with a channel to be selected and for generating a CHANGE signal when a new channel is selected;; lock means for generating a LOCK signal when said local oscillator signal has a frequency substantially equal to said programmed frequency; automatic fine tuning (AFT) means for selectively controlling said local oscillator means when enabled to operate to reduce a deviation between the actual frequency of said IF carrier and said nominal frequency value; offset detector means for generating an OFFSET signal when the frequency of said local oscillator signal is caused to be offset from the programmed frequency by a predetermined amount during the operation of said AFT means; mode control means for enabling the operation of said PLL means in response to said CHANGE signal, for enabling the operation of said AFT means in response to said LOCK signal and for again enabling the operation of said PLL means in response to said OFFSET signal; and channel selection means for causing said programmable factor control means to select the programmable factor associated with another channel when said OFFSET signal is generated a predetermined number of times.

2. The apparatus recited in Claim 1 wherein: said predetermined number of times is equal to one.

3. The apparatus recited in Claim 1 wherein: said programmable factor control means is coupled to counter means for counting the number of times said OFFSET signal is generated to change said programmable factor by an increment less than the difference between programmable factors associated with respective adjacent channels when said OFFSET signal is generated a second predetermined number of times less than said first mentioned predetermined number of times; and said channel selection means is also coupled to said counter means for causing said programmable factor control means to select the programmable factor associated with the next channel when said OFFSET signal is generated said first mentioned predetermined number of times.

4. The apparatus recited in Claim 3 wherein: said programmable factor control means increases said programmable factor by said increment in response to a first generation of said OFFSET signal and decreases said programmable factor by said increment in response to a second generation of said OFFSET signal and changes said programmable factor to the value associated with the next channel in response to a third generation of said OFFSET signal.

5. The apparatus recited in Claim 4wherein: said programmable factor control means includes inhibiting means for inhibiting said programmable factor control means from changing said programmable factor to the value in response to the OFFSET signal after a predetermined time longer the time required to tune said receiver to a selected channel.

6. In a receiver, apparatus comprising: local oscillator means for generating a local oscillatorsignal having a frequency capable of being controlled; mixer means for combining an RF carrier and said local oscillator signal to derive an IF signal having at least one carrier with a nominal frequency value; phase locked loop (PLL) means for controlling said local oscillator means when enabled to operate to cause said local oscillator signal to have a programmed frequency substantially equal to the product of a programmable factor and the frequency of a frequency reference signal; channel selection means for determining said programmable factor in accordance with a channel to be selected and for generating a CHANGE signal when a new channel is selected;; lock means for generating a LOCK signal when said local oscillator signal has substantially said programmed frequency; automatic fine tuning (AFT) means for selectively controlling said local oscillator means when enabled to operate to reduce a deviation between the actual frequency of said IF carrier and said nominal frequency value; mode means for selectively enabling the operations of said PLL and AFT means, said mode means enabling the operation of said PLL means in response to said CHANGE signal, said mode means enabling the operation of said AFT means in response to said LOCK signal; offset detector means for generating an OFFSET signal when the frequency of said local oscillator signal is caused to be offset from said programmed frequency by a predetermined amount during the operation of said AFT means;; said mode means enabling the operation of said PLL in response to said OFFSET signal; main power supply means for generating supply voltages for said receiver; main power supply control means for selectively enabling said power supply means to generate said supply voltages and thereby selectively causing said receiver to be in an on or off condition; and mode responsive means coupled to said power supply control means for causing said receiver to be in said off operating condition when said mode means causes the operations of said PLL and AFT means to be alternately enabled a predetermined number of times after the generation of said CHANGE signal.

7. The apparatus recited in Claim 6 wherein: said mode means generates a MODE signal having first and second levels corresponding to the respective operations of said PLL and AFT means; and said mode responsive means includes capacitor means for developing an ON/OFF signal in response to said MODE signal, said ON/OFF signal being applied to said main power supply control means to cause said receiver to be in said off condition when said ON/OFF signal reaches a first predetermined level.

8. The apparatus recited in Claim 7 wherein: said mode responsive means includes initialization means coupled to said capacitor means for causing said ON/OFF signal to have a second predetermined level to cause said receiver to remain in the on condition for a predetermined time after said receiver is initially caused to be in the on condition.

9. The apparatus recited in Claim 8 wherein: said receiver further includes function control means responsive to a function control signal for causing a predetermined analog function of said receiver to be changed in first and second opposite senses; manually operable means for selectively causing said function control signal to be selectively changed to affect said changes of said analog function in said first and second senses; and threshold means coupled to said power supply means for causing said receiver to be in said off condition when said function control signal reaches a third predetermined level; and wherein said mode responsive means includes switch means coupled to said manually operable means for causing said function control signal to be at least at said third predetermined threshold level when said ON/OFF signal reaches said first predetermined level.

10. The apparatus recited in Claim 9 wherein: said function control means inlues includes volume control means for controlling the volume of said receiver in response to said function control signal; said function control signal causes said volume level to be selectively decreased and increased; and said third predetermined level cbrresponds at least approximately to the minimum volume level.

11. The apparatus recited in Claim 10 wherein: said function control means includes remote control transmitter means for selectively transmitting remote control signals related to increases and decreases in the volume level; remote control receiver means for receiving said remote control signals and deriving therefrom said function control signal; and standby power supply means for generating supply voltages for said remote control receiver means when said receiver is in said off condition; and said initialization means includes a second switch means for selectively applying one of said supply voltages generated by said standby power supply means to said capacitor means when said receiver is in said off condition.

12. The apparatus recited in Claim 11 wherein: said second switch means is responsive to one of said supply voltages generated by said main power supply means to interrupt the application of said one of said supply voltages generated by said standby power supply means from said capacitor means when said receiver is in said on condition.

13. In a receiver, apparatus comprising: local oscillator means for generating a local oscillator signal having a frequency capable of being controlled; mixer means for combining an RF signal and said local oscillator signal to derive an IF signal having at least one carrier with a nominal frequency value; phase locked loop (PLL) means for controlling said local oscillator means when enabled to operate to cause said local oscillator signal to have a programmed frequency substantially equal to the product of a programmable factor and the frequency of a frequency reference signal; channel selection means for determining said programmable factor in accordance with selected channel and for generating a CHANGE signal when a new channel is selected; lock detector means for generating a LOCK signal when said local oscillator signal has locked to said programmed frequency; automatic fine tuning (AFT) means for selectively controlling said local oscillator means when enabled to operate to reduce a deviation between the actual frequency of said IF carrier and said nominal frequency value; offset detector means for generating an OFFSET signal when the frequency of said local oscillator signal is caused to be offset from said programmed frequency by a predetermined amount during the operation of said AFT means; mode control means for selectively enabling the operations of said PLL and AFT means, said mode control means enabling the operation of said PLL means in response to said CHANGE signal, said mode control means enabling the operation of said AFT means in response to said LOCK signal, said mode control means again enabling the operation of said PLL in response to said OFFSETsignal; signal processing means producing an information response in response to said IF signal; and mode responsive means coupled to said signal processing means for inhibiting said information response when said mode means causes the operations of said PLL and AFT means to be alternately enabled a predetermined number of times after the generation of said CHANGE signal.

14. The apparatus recited in Claim 13furtherincluding: main power supply means for generating supply voltages for said receiver; main power supply control means for selectively enabling said main power supply means to generate said supply voltages and thereby selectively causing said receiver to be in an on or off condition; and threshold detector means coupled to said main power control means for causing said receiver to be in said off condition when said information response has been inhibited.

15. The apparatus recited in Claim 14, wherein: said signal processing means produces an audible response.

16. Tuning apparatus substantially as hereinbefore described with reference to Figures 1, 2 or 3 of the accompanying drawings.