JPS6134315B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an apparatus for receiving an information signal, comprising:
The present invention relates to a device used to stabilize the signal amplitude.

An embodiment of the present invention will be described below with reference to the drawings. Here, it is assumed that a 4-bit (any number of 2 or more bits is fine) start pulse of "0" and "1" is transmitted at the beginning of the transmitted information signal, and the frequency component (fundamental wave) of this signal is This will be explained as 3.0MHz. The amplitude of this start pulse is the same as that of the following information.

First, in Figure 1, 1 is the tuner of the television receiver, 2 is the VIF circuit, 1 is the video detection circuit, and 4 is the tuner of the television receiver.
are sync separation circuits, which are the same as those in ordinary television receivers. 5 is one of the main parts of this device, and is an amplifier circuit for amplifying the start pulse as shown in FIG. 4A;
is a circuit that generates a gate pulse to extract the 20th H (and 283rd H) of the multiplexed information signal using the horizontal and vertical synchronizing signals. The amplifier circuit 5 is controlled by the output of the gate pulse generation circuit 6, and its output is taken out only at the 20th H portion.

Further, the signal is converted into a waveform as shown in FIG. This sample-and-hold circuit 7 is, for example, a sample-and-hold circuit using a closed-lobe, buffer-type FET,
The DC bias obtained by rectifying the signal in Fig. 4H is applied between t ₈ and _{t 9}
sample over the next field.
It is held until the 20th H (or the 283rd H) and generates a gain control voltage that can be considered constant at least during the 20th H.

8 is an amplifier whose gain is controlled by this;
The main parts of this device are formed by these 5, 7, and 8.
9 is a processing circuit for displaying information signals, which is obtained from a digital memory, a control circuit, and the like.

The output of the processing circuit 9, that is, the information video signal, is mixed with the television video signal in the mixing circuit 10, and only the information characters or the television screen and the information characters are displayed on the cathode ray tube 12. Video amplifier circuit 1
1 is its driving circuit.

Now, the received signal is as shown in Figure 2 A,
If you enlarge the signal part, it will look like the one shown in Figure B.

For example, if the highest frequency component is the same as the start pulse, there will be a difference in amplitude between the 3.0 MHz 1-bit part and the lower frequency component part, as shown in B, and a correct waveform as shown in C in the same figure will be reproduced. is difficult to obtain. L in B is the slice level, and this level L does not change even if the amplitude of the signal changes. Therefore, if the amplitude changes, the width of the obtained pulse changes, making data sampling difficult.

Therefore, in this apparatus, the circuit configuration shown in FIGS. 3 and 5 is used to automatically perform gain control using the received signal as shown in FIG. 4A. In FIG. 3, first, a delayed pulse clamp pulse generation circuit 15 as shown in FIG. 4B is used to generate a delayed pulse, which is slightly delayed from the trailing edge of the horizontal synchronizing signal using an integrating circuit or the like. This circuit may be a monomultivibrator. This will clamp the detection output. The clamp position is
From _t3 to _t4 in FIG. 4, it is between the trailing edge of the sync signal and the trailing edge of the back pouch _t6 .

The signal A is slightly amplified by the amplifier circuit 13, clamped by the clamp pulse B by the clamp circuit 14, and further, only the 20th information signal portion is extracted by the 20th H sampling circuit 16. Bandwidth amplifier 17 then tuned to the fundamental frequency of the start pulse 3.0MHz
wave, and obtain a sinusoidal output as shown in Figure 4E.
This is sliced by the slicing circuit 18, and the flip-flop 19 is set from the first falling edge _t8 of the output. The flip-flop 19 applies the output of the gate pulse generating circuit 6 to its J terminal so that it operates only at the 20th H.

Furthermore, 2 is a delay circuit which generates a gate pulse as shown in FIG. 4D every H to control the band amplifier 17. The flip-flop 19 is set at t ₈ and reset at t ₉ when the counter 21 counts the rise of the output signal F of the slice circuit 18 up to the third bit. Therefore, the Q terminal output of the flip-flop 19 becomes as shown in FIG. 4G. 22 is a sample hold circuit;
23 is a DC amplifier circuit.

FIG. 5 shows a more detailed circuit diagram of this circuit and its operation will be explained. 24 is a coupling capacitor, 25 and 26 are resistors that provide base bias for the transistor 27, 27 is a variable gain transistor that constitutes the amplifier 13, 28 is a collector resistor, 29 is for DC feedback, and resistor 30 is a capacitor 31, 32 This resistor also prevents the input impedance of the transistor 27 from becoming extremely small even if it is bypassed by the resistor. 3
3 is a clamp circuit 14 for the output of the transistor 27.
31 is an electrolytic capacitor, 3
2 is a magnetic capacitor for high frequency characteristic compensation. 3
4 is a collector load resistance, which is selected to be larger than the resistor 30.

35 is a transistor that is switched depending on the base input level, and when the collector current increases and a short circuit occurs between C and E, the capacitor 3
Since transistors 1 and 32 are grounded, transistor 2
7 gain becomes larger. Capacitor _37C and coil _37L resonate at the aforementioned fundamental frequency of 3.0MHz, and extract only the start pulse component. 39
is the tuning capacitor, 38 is the bypass capacitor, 4
0.41 is a resistor that provides base bias for the transistor 42, 42 is a transistor for band amplification,
43 is the emitter resistor, and the output taken out from the 20th H is delayed by a mono multivibrator 20 _M.
At the falling edge of the signal shown in Fig. 4C, the flip-flop 20
_F is set, and its output signal is of the opposite polarity to that shown _{in FIG} .

44 is the tuning capacity of the transformer 45, and the tuning frequency and bandwidth are the same as those of _37L , _37C and 39. 46 and 47 are resistors that determine the base bias of the transistor 49, 48 is a bypass capacitor, 50 is a collector load resistance of the transistor 49, 51 is its emitter resistance, and 52 is a transistor that constitutes a differential amplifier for the slice circuit together with the transistor 49. , 53 are load resistors 54, 55, and 56 of the transistor 52, which determine the slice level of the differential amplifier, and are determined by adjusting the variable resistor 55 to a value that slices at the center of the amplitude of the signal E shown in FIG. .

Since the output of the transistor 52 becomes the signal shown in _{FIG .} Set it to low level and start counting from the next rising pulse of signal F at _t8 . 61 is an inverter for counting the rising edge of signal F. Counting the rise of the 3rd bit at t ₉ , NAND
Since the two inputs of gate 62 are both high, its output goes negative from _t9 , resetting flip-flop 19, so that its Q output is as shown in FIG.
The flip-flop 20F is also reset and its output becomes the inverted version of the signal D. Therefore, the waveform of signal E does not appear at the output of transistor 42 after _t9 . This is to remove the waveform after _t9 , since the signal after the start pulse is data and it is not determined whether it is "0" or "1", so the waveform at the end of signal E will not be constant. be.

As described above, as the Q output of flip 19,
A gate pulse as shown in FIG. 4G can be obtained. This can be used to gate the output of the transistor 42, that is, the signal E. However, in order to detect amplitude fluctuations, the transformer 45 is provided with a tertiary winding, and after double-wave rectification is performed by the double-wave rectifier circuit 58, the gate is gated. 59, the output is as shown in FIG. 4H. The DC voltage obtained by integrating this in the integrating circuit 60 is proportional to the amplitude of the start pulse in the signal A. 63 is an operational amplifier, and 64.65 is a FET that forms a sample-and-hold switch. During sampling (t ₈ to t ₉ ), signal G makes FET 64 conductive, and FET 95 is cut off, charging the capacitor 66 from t ₈ onwards. is cut off by the FET 64 and the charge stored in the capacitor 66 is held. t ₉
After that, FET65 becomes conductive. 67 is also an operational amplifier. 63 to 72 are examples of well-known sample and hold circuits.

The output of the operational amplifier 67 is applied to the transistor 35 to control the amplification degree of the transistor 27. That is, by controlling the gain of the transistor 27 with the amplitude of the start pulse, the input signal to the clamp circuit 14 is made to have a constant amplitude. That is, the amplitude of the information signal such as additional characters is made constant by this gain control. Therefore, the slice output also does not fluctuate, allowing stable reception.

Note that even if sampling is performed for a short period of time from t ₈ to _{t 9} , if the capacitance of the capacitor 66 and other constants are appropriately selected, the base bias of the transistor 35 can be kept constant within the range of the 20th H or the 21st and 22nd H. It is easy to do.

Furthermore, in this device, the first slice circuit 9' for the information processing circuit 9 for additional characters and the like and the second slice circuit consisting of the transistors 49 and 52 are separately provided. Even if there is a fluctuation in the input amplitude or slice level, an upward pulse of the signal F is obtained as long as the transistors 49 and 52 are not offset, and only the pulse width changes, so that the above-described operation is performed reliably. Also, between t ₉ and t ₁ , the output of the operational amplifier 67 reaches the desired DC level and reaches 1H.
Needless to say, it can be maintained for some time or longer.

As described above, according to the present invention, even if the amplitude of the received signal fluctuates when receiving an information signal, it can always be stabilized, and accurate reception can be achieved through stable slicing operation. It is something that can be done.

[Brief explanation of the drawing]

FIGS. 1 and 3 are block diagrams of an automatic gain control device according to an embodiment of the present invention, and FIGS.
B, C and Figure 4 A, B, C, D, E, F,
G and H are waveform diagrams for explaining the operation of the device,
FIG. 5 is a detailed circuit diagram of the main parts of the device. 5...Amplification circuit, 6...Gate pulse generation circuit, 7...Sample hold circuit, 8...Amplifier, 9...Processing circuit, 9'...Slice circuit.

Claims (1)

[Claims] 1. Detects and samples and holds amplitude fluctuations in the start pulse added to the beginning of the multiplexed information signal during the vertical retrace period of the television signal, and samples and holds the amplitude fluctuation only during the period when the information signal is being sent. In an automatic gain control device that performs automatic gain control to keep the amplified output constant, the means for detecting and sample-holding amplitude fluctuations of the start pulse includes a filter that passes only the fundamental wave component of the start pulse; A sample and hold circuit that samples and holds a signal representing the amplitude fluctuation of the start pulse created from the output of the filter and outputs it as a control voltage for the automatic gain control, and a slice circuit for processing the information signal are provided separately. a slicing circuit that slices the output of the filter, and a circuit that generates a gate pulse for causing the sample and hold circuit to perform a sampling operation only during the period of the start pulse based on the output of the separately provided slide circuit. An automatic gain control device characterized by: