JPH0645886A - Pulse width modulating circuit - Google Patents

Abstract

PURPOSE:To use digital data as it is to perform pulse width modulation by comparing the numerical value of output data from a counter and that of digital data with each other and outputting the result as a pulse width modulation signal. CONSTITUTION:Digital data D1 is switched when a counter 3 counts 0, and data is changed from 0 to 16. A comparator 5 compares output data D2 of an adder 4 and digital data D1 with each other and outputs the result. An adder 5 adds one as addition data to the data of the counter 3; and when the output of the adder 5 is one, data value 16 of digital data D1 is larger than output data D2 of the adder 4, and an output signal 6 of the comparator 5 is changed from the low level to the high level. When output data of the counter 16 is 16, that is, when output data D2 of the adder 4 is 17, output data D2 is larger than digital data D1, and the output signal of the comparator 5 is changed from the high level to the low level. That is, the output level width of the comparator 5 is determined by data D1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation circuit, and more particularly to a circuit for performing pulse width modulation with digital data.

[0002]

2. Description of the Related Art An example of a conventional pulse width modulation circuit is shown in FIG. This circuit has a triangular wave generator 8 and an analog comparator 9 for comparing the output signal of the triangular wave generator 8 and the analog signal 7 input from the input terminal. And
The analog level of the analog input signal 7 and the level of the triangular wave output by the triangular wave generator 8 are compared with the analog comparator 9. As a result, when the analog signal level is higher than the triangular wave level, the comparator outputs a high level. In the opposite case, the comparator outputs a low level. The state is shown in FIG. When the level of the analog input signal becomes higher than the triangular wave, the PWM signal becomes high level. in this case,
It can be seen that the higher the level of the analog input signal is, the longer the high level of the PWM signal is, and the pulse width is modulated according to the level of the analog input signal.

[0003]

In this conventional pulse width modulation circuit, since the analog input signal and the level of the triangular wave are compared, when the pulse width modulation is performed by the digital data, the digital data is once converted into the analog signal. Need to be converted to. For this reason, a digital-analog converter is required and the circuit scale increases. Further, since the analog circuit is added, there is a problem that the characteristics tend to change over time, and the characteristics depend on the power supply voltage and the temperature. It is an object of the present invention to provide a pulse width modulation circuit that enables pulse width modulation using digital data as it is.

[0004]

SUMMARY OF THE INVENTION According to the present invention, a counter that counts clocks and outputs a count-up signal when a required number is counted, an adder that adds a constant to count output data from the counter, and an adder And a comparator for comparing the magnitude of the numerical values of the output data of the comparator and the digital data and outputting the result as a pulse width modulation signal.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. Here 500KH _Z a cycle of the pulse width modulation, the clock frequency
50 mH _Z, the number of bits of the digital data of 7 bits,
The minimum step of pulse width modulation is 1%. In the following description, the numerical values enclosed in parentheses are binary numbers.
In the figure, 3 is a counter for counting the clock signal 2 and outputs data to the adder 4 when the clock signal 2 is counted from 0 to 99. The adder 4 adds the addition data “1” to the data from the counter 3 and outputs it to the 7-bit comparator 5. The other side of the comparator 5 has digital data signals 1 (0000000) to (111).
1111) is input. Then, the comparator 5 compares the digital data signal 1 with the signal from the comparator 5, and outputs the PWM signal 6 as a result. The logic of the comparator 5 outputs a high level when the data D1 of the digital data signal 1 and the output data D2 of the adder 4 are D1 ≧ D2, and D1
When <D2, low level is output.

A time chart under these conditions is shown in FIG. The operation will be described with reference to this time chart. The counter 3 is changed from 0 (0000000) to 99 (1 by the clock signal 2).
Count up to 100011. The output data of the adder 4 is obtained by adding 1 of the addition data to the data of the counter 3 and outputs 1 (000001) to 100 (1100100). The digital data D1 is switched when the counter 3 becomes zero. Here, the case where the data 20 is changed to 16 is shown.

The comparator 5 compares the output data D2 of the adder 4 with the data D1 of the digital data signal 1 and outputs it.
When the output of the adder 4 becomes 1, the data value 16 of the data D1 of the digital data signal becomes larger than the output data D2 of the adder 4, so the output signal 6 of the comparator 5 changes from low level to high. Change to a level. After that, the output data of the counter 3 is 15, that is, the output data D of the adder 4
The comparator 5 maintains a high level from 2 to 16. The output data of the counter 3 is 16, that is, the output data D of the adder 4
When 2 becomes 17, the output data of the adder 4 becomes larger than the data D1 of the digital data signal, so that the output signal 6 of the comparator 5 changes from the high level to the low level.

As described above, the width at which the output of the comparator 5 becomes high level is determined by the data D1 of the digital data signal. That is, a pulse width modulator can be realized. If the value of the addition data is changed to 10, the output of the adder 4 is 1
Since it changes from 0 (0001010) to 109 (1101101), the same effect as adding an offset to digital data can be provided.

FIG. 5 is a diagram showing a second embodiment of the present invention. Here, the output data of the counter 3 of the first embodiment and the magnitude of the duty data 10 are configured to be compared by the second comparator 11. The second comparator 11 outputs a high level when the output data of the counter 3 is smaller than the duty data 10, and outputs a low level when the output data of the counter 3 has a value equal to or larger than the duty data 10. To do. Then, the output of the second comparator 11 and the data of the same comparator 5 as in the first embodiment are ANDed by the AND circuit 12 and the output thereof is used as the PWM signal 6. That is, this circuit has the effect of validating the output of pulse width modulation only when the duty data 10 is larger than the output data of the counter 3, and forcing the output signal to the low level otherwise. That is, the duty data 10 limits the effective time of the pulse width modulation. In other words, the maximum duty of the pulse width modulation can be defined.

[0010]

As described above, according to the present invention, since the output of pulse width modulation is obtained after comparing the digital data with the data output from the counter, the digital-analog converter becomes unnecessary. Further, since all the circuits can be configured by digital circuits, there is an effect that if the clock is stable, it is irrelevant to power supply voltage, temperature dependence, and secular change.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 3 is a circuit diagram of an example of a conventional pulse width modulation circuit.

FIG. 4 is a waveform diagram for explaining pulse width modulation of the circuit of FIG.

FIG. 5 is a circuit diagram of a second embodiment of the present invention.

[Explanation of symbols]

 1 Digital Data Signal 2 Clock 3 Counter 4 Adder 5 Comparator 10 Duty Data 11 Second Comparator 12 AND Circuit

Claims (1)

[Claims] 1. A counter that counts clocks and outputs a count-up signal when a required number is counted,
It is equipped with an adder that adds a constant to the count output data from this counter, and a comparator that compares the output data of this adder and the numerical value of the digital data and outputs the result as a pulse width modulation signal. Pulse width modulation circuit.