JPH0645513A - Thick film hybrid integrated circuit device - Google Patents
Thick film hybrid integrated circuit deviceInfo
- Publication number
- JPH0645513A JPH0645513A JP21723492A JP21723492A JPH0645513A JP H0645513 A JPH0645513 A JP H0645513A JP 21723492 A JP21723492 A JP 21723492A JP 21723492 A JP21723492 A JP 21723492A JP H0645513 A JPH0645513 A JP H0645513A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- capacitor
- electrode
- circuit pattern
- thick film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、厚膜混成集積回路装
置(以下、単にハイブリッドIC装置と称す)に関し、
特にその厚膜混成集積回路基板に形成される電気回路の
うち、コンデンサを介して行なう電気的結合の改良を図
ったものに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thick film hybrid integrated circuit device (hereinafter simply referred to as a hybrid IC device),
In particular, the present invention relates to an electric circuit formed on the thick film hybrid integrated circuit substrate, in which electric coupling performed through a capacitor is improved.
【0002】[0002]
【従来の技術】図7は従来のハイブリッドIC装置にお
ける基板上の回路パターンの、コンデンサを介して行な
う電気的結合の様子を示す構成図である。図において、
1は基板5の表面に搭載される部品の1つであるチップ
型積層コンデンサであり、例えば2mm×1mmの大きさを
有し、0.5 〜0.8mm の高さを有している。20a,20
bはこのコンデンサ1の両端に形成された電極、3a,
3bはコンデンサ1を搭載するために基板5の表面上に
設けられた導体パターンであり、コンデンサ1の電極2
0a,20bが半田付けされるランド部は例えば2mm角
の大きさを持っており、スルーホール4に接続されるラ
ンド部は例えば1mm角の大きさを持っている。また、導
体パターン3aのスルーホール4と電極20aとをつな
ぐ部分は1〜2mmの長さを持っている。2. Description of the Related Art FIG. 7 is a configuration diagram showing a state of electrical coupling of a circuit pattern on a substrate in a conventional hybrid IC device through a capacitor. In the figure,
Reference numeral 1 denotes a chip type multilayer capacitor which is one of the components mounted on the surface of the substrate 5, and has a size of, for example, 2 mm × 1 mm and a height of 0.5 to 0.8 mm. 20a, 20
b is electrodes formed on both ends of this capacitor 1, 3a,
3b is a conductor pattern provided on the surface of the substrate 5 for mounting the capacitor 1, and the electrode 2 of the capacitor 1
The land portion to which 0a and 20b are soldered has a size of, for example, 2 mm square, and the land portion connected to the through hole 4 has a size of, for example, 1 mm square. The portion connecting the through hole 4 of the conductor pattern 3a and the electrode 20a has a length of 1 to 2 mm.
【0003】4は導体パターン3aとアース電極6とを
電気的に接続するためのスルーホール、5はアルミナセ
ラミック等の絶縁体で形成された、厚膜混成集積回路の
基板であり、例えば4cm×2cmの大きさを有し、1〜2
mmの厚みを有している。6は基板5の裏面に形成され
た、放熱用のフィンを兼ねるアース電極であり、基板5
と同様の大きさで、例えば2〜3mmの厚みを有してい
る。7はこのハイブリッドIC装置とその外部回路との
電気的接続を行うための電極リードであり、導体パター
ン3bと電気的に接続されている。Reference numeral 4 is a through hole for electrically connecting the conductor pattern 3a and the ground electrode 6, and 5 is a substrate of a thick film hybrid integrated circuit formed of an insulator such as alumina ceramic, for example, 4 cm × It has a size of 2 cm and is 1-2
It has a thickness of mm. Reference numeral 6 denotes a ground electrode formed on the back surface of the substrate 5, which also serves as a fin for heat dissipation.
It has the same size as, and has a thickness of 2 to 3 mm, for example. Reference numeral 7 denotes an electrode lead for electrically connecting the hybrid IC device and its external circuit, which is electrically connected to the conductor pattern 3b.
【0004】この従来装置の基板5は、その焼成の前段
階で型にはめて、スルーホールになるべき貫通孔を形成
し、その後焼成を行なうことにより得られる。次に、基
板5の表面に銀等の導体パターン3a,3bを形成する
際に、上記貫通孔に導体を流し込み、導体パターン3
a,3bとスルーホール4とを同時に形成する。次に、
基板5の裏面に銅等で形成されたアース電極6を半田付
けし、さらに電極リード7を導体パターン3と半田付け
することにより完成する。The substrate 5 of this conventional device is obtained by forming a through hole to be a through hole in a mold before the firing, and then firing. Next, when the conductor patterns 3a and 3b made of silver or the like are formed on the surface of the substrate 5, the conductor is poured into the through holes to form the conductor pattern 3
The a and 3b and the through hole 4 are simultaneously formed. next,
The ground electrode 6 made of copper or the like is soldered to the back surface of the substrate 5, and the electrode lead 7 is soldered to the conductor pattern 3 to complete the process.
【0005】そしてさらに、基板5の導体パターン3
a,3bにコンデンサ1を半田付けすることにより、コ
ンデンサ1が実装され、これにより、電極リード7が導
体パターン3b,コンデンサ1,導体パターン3a,ス
ルーホール4を介してアース電極6に電気的に接続され
る。Further, the conductor pattern 3 on the substrate 5
The capacitor 1 is mounted by soldering the capacitor 1 to a and 3b, whereby the electrode lead 7 is electrically connected to the ground electrode 6 through the conductor pattern 3b, the capacitor 1, the conductor pattern 3a, and the through hole 4. Connected.
【0006】[0006]
【発明が解決しようとする課題】従来のハイブリッドI
C装置は以上のように構成されているので、電極リード
7とアース電極6との電気的接続を、コンデンサ1を介
して行なうには、コンデンサ1を搭載するための導体パ
ターン3a,3bおよびスルーホール4を基板5上に形
成しなければならず、回路パターンが大きくなってしま
うという問題点があった。[Problems to be Solved by the Invention] Conventional Hybrid I
Since the C device is configured as described above, in order to electrically connect the electrode lead 7 and the ground electrode 6 via the capacitor 1, the conductor patterns 3a and 3b for mounting the capacitor 1 and the through-holes are provided. The hole 4 must be formed on the substrate 5, resulting in a large circuit pattern.
【0007】この発明は、上記のような問題点を解消す
るためになされたもので、コンデンサを介して電気的接
続を行なう際に、その回路パターンを縮小することがで
きるハイブリッドIC装置を得ることを目的とする。The present invention has been made in order to solve the above problems, and provides a hybrid IC device capable of reducing the circuit pattern when electrically connecting via a capacitor. With the goal.
【0008】[0008]
【課題を解決するための手段】この発明に係るハイブリ
ッドIC装置は、基板に貫通させた穴にコンデンサを挿
入してこれを埋設し、かつコンデンサの電極と基板の回
路パターンを金線等によって電気的に接続するようにし
たものである。In a hybrid IC device according to the present invention, a capacitor is inserted into a hole penetrating a substrate to embed it, and an electrode of the capacitor and a circuit pattern of the substrate are electrically connected by a gold wire or the like. They are connected to each other.
【0009】また、この発明に係るハイブリッドIC装
置は、コンデンサと一体に形成された板状の電極によ
り、コンデンサと基板の回路パターンとを直接電気的に
接続するようにしたものである。Further, the hybrid IC device according to the present invention is configured such that the capacitor and the circuit pattern of the substrate are directly electrically connected by the plate-like electrode integrally formed with the capacitor.
【0010】さらに、この発明に係るハイブリッドIC
装置はその基板として多層基板を用いるようにしたもの
である。Further, the hybrid IC according to the present invention
The device uses a multi-layer substrate as its substrate.
【0011】[0011]
【作用】この発明におけるハイブリッドIC装置におい
ては、コンデンサの電極と基板の回路パターンおよびア
ース電極との電気的接続が、コンデンサ自身を基板に形
成された貫通孔に埋込んで実装することにより達成され
るので、従来の構造における、コンデンサを取付けるた
めの導体パターンが不要となり、回路パターンの縮小が
可能となる。In the hybrid IC device according to the present invention, the electrical connection between the electrode of the capacitor and the circuit pattern of the substrate and the ground electrode is achieved by mounting the capacitor itself by embedding it in a through hole formed in the substrate. Therefore, the conductor pattern for mounting the capacitor in the conventional structure becomes unnecessary, and the circuit pattern can be reduced.
【0012】また、この発明におけるハイブリッドIC
装置においては、コンデンサの電極を板状の電極とする
ことにより、コンデンサと基板表面の配線パターンとを
接続する金線等のワイヤリング工程が不要となる。The hybrid IC according to the present invention
In the apparatus, the plate-shaped electrodes are used as the electrodes of the capacitors, so that the wiring process for connecting the capacitors to the wiring pattern on the surface of the substrate is not required.
【0013】さらに、この発明におけるハイブリッドI
C装置においては、基板を多層基板としたので、多層基
板を用いた厚膜混成集積回路装置においても、コンデン
サを介して基板の最上層と最下層を接続する際の回路パ
ターンの縮小が可能となる。Further, the hybrid I according to the present invention
In the C device, since the substrate is a multi-layer substrate, even in a thick film hybrid integrated circuit device using the multi-layer substrate, it is possible to reduce the circuit pattern when connecting the uppermost layer and the lowermost layer of the substrate via a capacitor. Become.
【0014】[0014]
【実施例】実施例1.以下、この発明の一実施例を図に
ついて説明する。図1はこの発明の一実施例による厚膜
混成集積回路装置を示す。図において、1は基板5に埋
設される円柱状のコンデンサであり、例えば1〜2mmの
直径を有し、基板5の厚みと同程度の、1〜1.5mm の高
さを有している。2a,2bはこのコンデンサ1の両端
に形成された丸型の電極、3はコンデンサ1の表面側の
電極2aと電気的に接続される、基板5の表面上に設け
られた導体パターン、5はコンデンサ1等の種々の電子
部品が搭載される厚膜混成集積回路基板、5aはこの基
板5の表面から裏面に達するように形成された、コンデ
ンサ1を基板5に埋設するための穴、6は基板5の裏面
に半田付けされたアース電極、7はこのハイブリッドI
C装置とその外部回路との電気的接続を行うための電極
リードであり、導体パターン3と電気的に接続されてい
る。8はコンデンサ1の一方の電極2aと導体パターン
3とを電気的に接続するための金線である。なお、この
実施例では、円柱状のコンデンサとしたが、多角柱状の
コンデンサでも同様の効果が得られる。EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a thick film hybrid integrated circuit device according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a cylindrical capacitor embedded in a substrate 5, which has a diameter of, for example, 1 to 2 mm and a height of 1 to 1.5 mm, which is approximately the same as the thickness of the substrate 5. 2a and 2b are round electrodes formed on both ends of the capacitor 1, 3 is a conductor pattern provided on the surface of the substrate 5, which is electrically connected to the electrode 2a on the surface side of the capacitor 1, A thick film hybrid integrated circuit substrate 5a on which various electronic components such as the capacitor 1 are mounted is formed so as to reach from the front surface to the back surface of the substrate 5, a hole for burying the capacitor 1 in the substrate 5, and 6 The ground electrode 7 soldered to the back surface of the substrate 5 is the hybrid I
It is an electrode lead for electrically connecting the C device and its external circuit, and is electrically connected to the conductor pattern 3. Reference numeral 8 is a gold wire for electrically connecting the one electrode 2a of the capacitor 1 and the conductor pattern 3 to each other. It should be noted that although a cylindrical capacitor is used in this embodiment, a similar effect can be obtained with a polygonal capacitor.
【0015】この実施例の基板5は、その焼成の前段階
で型にはめてコンデンサ埋設用の穴になるべき貫通孔を
形成し、その後焼成を行なうことにより得られる。次
に、基板5の表面に銀等の導体パターン3を形成し、基
板5の裏面に銅等で形成されたアース電極6を半田付け
し、さらに電極リード7を導体パターン3と半田付けす
ることにより完成する。The substrate 5 of this embodiment is obtained by forming a through hole to be a hole for burying a capacitor in a mold before the firing, and then firing. Next, the conductor pattern 3 made of silver or the like is formed on the front surface of the substrate 5, the ground electrode 6 made of copper or the like is soldered on the back surface of the substrate 5, and further the electrode lead 7 is soldered to the conductor pattern 3. Is completed by.
【0016】そしてさらに、基板5に形成された、コン
デンサ埋設用の穴5aに半田材を埋め込み、コンデンサ
1を挿入し全体を加熱することにより、半田材が溶融し
てコンデンサ1の電極2bとアース電極6との溶着が行
なわれる。その後、基板5に埋設されたコンデンサ1
の、基板表面に露出した側の電極2aとパターン3とを
金線8等で接続することにより、電極リード7とアース
電極6とがコンデンサ1を介して電気的に接続される。Further, a solder material is embedded in a hole 5a for burying a capacitor formed in the substrate 5, the capacitor 1 is inserted and the whole is heated, so that the solder material is melted and the electrode 2b of the capacitor 1 and ground. Welding with the electrode 6 is performed. After that, the capacitor 1 embedded in the substrate 5
By connecting the electrode 2a on the side exposed on the substrate surface to the pattern 3 with a gold wire 8 or the like, the electrode lead 7 and the ground electrode 6 are electrically connected via the capacitor 1.
【0017】なお、コンデンサ1の溶着用の半田とアー
ス電極の半田付け用の半田とはその融点が異なるため、
コンデンサ1を溶着する際の加熱によってアース電極6
が外れることはない。Since the solder for welding the capacitor 1 and the solder for soldering the ground electrode have different melting points,
The ground electrode 6 is heated by heating when welding the capacitor 1.
Does not come off.
【0018】また、コンデンサの溶着用の半田付けは、
アース基板の取付け用の半田付けと同時に行なうように
してもよい。Further, the soldering for welding the capacitor is
It may be performed at the same time as soldering for mounting the ground substrate.
【0019】このように、本実施例における、コンデン
サ1を介した電極リード7とアース電極6との電気的接
続は、電極パターン3を金線8で、基板5に貫通させた
穴5aに挿入されたコンデンサ1の上側の電極2aに接
続し、かつ、コンデンサ1の下側の電極2bを半田付け
等によってアース電極6に接続したことにより、これを
実現したものである。As described above, in the present embodiment, the electrical connection between the electrode lead 7 and the ground electrode 6 via the capacitor 1 is performed by inserting the electrode pattern 3 with the gold wire 8 into the hole 5a penetrating the substrate 5. This is realized by connecting the upper electrode 2a of the capacitor 1 and the lower electrode 2b of the capacitor 1 connected to the ground electrode 6 by soldering or the like.
【0020】従って、この実施例によれば、電極パター
ンのうち、基板表面と裏面とを電気的に接続するための
スルーホールとコンデンサの電極とを接続するための電
極パターンが不要となるため、厚膜混成集積回路装置に
おける基板表面と裏面とを、コンデンサを介して接続す
る際に、その回路パターンの縮小が可能となる。Therefore, according to this embodiment, of the electrode patterns, the through hole for electrically connecting the front surface and the back surface of the substrate and the electrode pattern for connecting the electrode of the capacitor are unnecessary. When connecting the front surface and the back surface of the substrate in the thick film hybrid integrated circuit device via a capacitor, the circuit pattern can be reduced.
【0021】実施例2.図2を用いて、本発明の他の実
施例を説明する。図2の構造は、上記実施例1における
コンデンサ1の上側の電極の形状を、板状に長く延ばす
ことによって、導体パターンとコンデンサ1とを、金線
等を用いることなく電気的に接続させたものである。Example 2. Another embodiment of the present invention will be described with reference to FIG. In the structure shown in FIG. 2, the shape of the upper electrode of the capacitor 1 in the first embodiment is elongated in a plate shape so that the conductor pattern and the capacitor 1 are electrically connected without using a gold wire or the like. It is a thing.
【0022】即ち、この実施例においては、実施例1と
同様にして完成された基板5に、これに形成された、コ
ンデンサ埋設用の穴5aに半田材を埋め込み、コンデン
サ1をその板状電極2cが基板5表面と接触するまで挿
入し全体を加熱することにより、半田材が溶融してコン
デンサ1の電極2bとアース電極6の溶着が行なわれ
る。これにより、コンデンサ1の板状電極2cとパター
ン3とが自動的に接続されることとなり、電極リード7
とアース電極6とがコンデンサ1を介して電気的に接続
される。That is, in this embodiment, a solder material is embedded in a hole 5a for burying a capacitor, which is formed in the substrate 5 completed in the same manner as in the first embodiment, and the capacitor 1 is attached to its plate electrode. By inserting 2c until it comes into contact with the surface of the substrate 5 and heating the whole, the solder material is melted and the electrode 2b of the capacitor 1 and the ground electrode 6 are welded. As a result, the plate electrode 2c of the capacitor 1 and the pattern 3 are automatically connected, and the electrode lead 7
And the ground electrode 6 are electrically connected via the capacitor 1.
【0023】なお、この板状の電極2cは上記実施例1
におけるコンデンサ1の丸型電極2aに、これとは別体
の板状電極を予め半田付けする等によって形成すること
ができる。The plate-shaped electrode 2c is used in the first embodiment.
The circular electrode 2a of the capacitor 1 can be formed by previously soldering a plate-shaped electrode, which is a separate body, from the circular electrode 2a.
【0024】この実施例では、例えば2mm×1mmの大き
さを有する板状の電極2cを有するコンデンサ1を用い
たことにより、実施例1における金線8は不要となる。
またこの板状電極がコンデンサを挿入する際のストッパ
となるので、その組立が容易となる効果もある。In this embodiment, since the capacitor 1 having the plate-shaped electrode 2c having a size of 2 mm × 1 mm is used, the gold wire 8 in the first embodiment becomes unnecessary.
Further, since the plate-like electrode serves as a stopper when inserting the capacitor, there is also an effect that the assembling thereof becomes easy.
【0025】実施例3.図3を用いて、本発明のさらに
他の実施例を説明する。図3の構造は、上記実施例2に
おける基板からアース電極を除去するとともに、上記実
施例2における板状電極2c付きのコンデンサ1を基板
5裏面から挿入し、その際、板状電極2cの基板5側の
面に半田を載置しておき、全体を加熱することにより板
状電極2cと基板5裏面のアースパターンとを半田で溶
着し、その後、基板5表面の導体パターンとコンデンサ
1の丸型の電極2bとを金線8等で接続するようにした
ものである。Example 3. Still another embodiment of the present invention will be described with reference to FIG. In the structure shown in FIG. 3, the ground electrode is removed from the substrate in the second embodiment, and the capacitor 1 with the plate electrode 2c in the second embodiment is inserted from the back surface of the substrate 5, while the substrate of the plate electrode 2c is inserted. The solder is placed on the surface on the side of 5 and the entire plate is heated to weld the plate-like electrode 2c and the ground pattern on the back surface of the substrate 5 with the solder, and then the conductor pattern on the surface of the substrate 5 and the circle of the capacitor 1 are welded. The mold electrode 2b is connected by a gold wire 8 or the like.
【0026】この実施例によれば、基板裏面にアース電
極を持たないものにおいても、基板表面と裏面とをコン
デンサを介して接続する際に、その回路パターンの縮小
が可能となる。またコンデンサの板状電極が、これを挿
入する際のストッパとなるので、その組立が容易となる
効果もある。According to this embodiment, even in the case where the back surface of the substrate does not have the ground electrode, the circuit pattern can be reduced when the front surface and the back surface of the substrate are connected via the capacitor. In addition, since the plate electrode of the capacitor serves as a stopper when inserting the capacitor, there is also an effect that the assembling thereof becomes easy.
【0027】なお、この実施例においても基板裏面にア
ース電極を設けるようにしてもよく、この場合、コンデ
ンサを挿入した後、基板裏面とアース電極とを半田付け
する工程があるため、板状電極と基板裏面とを半田付け
する工程は、これを省略することが可能である。In this embodiment as well, the ground electrode may be provided on the back surface of the substrate. In this case, since there is a step of soldering the back surface of the substrate and the ground electrode after inserting the capacitor, the plate electrode is formed. This can be omitted in the step of soldering the substrate and the back surface of the substrate.
【0028】実施例4.図4を用いて、本発明のさらに
他の実施例を説明する。図4の構造は、上記実施例1な
いし上記実施例3における基板を、予めコンデンサ埋設
用の穴5aが形成された、最上層51,中間層52,最
下層53からなる多層基板5とし、その裏面にアース電
極6を半田付けし、基板5に形成された、コンデンサ埋
設用の穴5aに半田材を埋め込み、コンデンサ1を挿入
し全体を加熱することにより、半田材が溶融してコンデ
ンサ1の電極2bとアース電極6の溶着が行なわれる。
その後、基板5に埋設されたコンデンサ1の、基板表面
に露出した側の電極2aとパターン3とを金線8等で接
続することにより、電極リード7とアース電極6とがコ
ンデンサ1を介して電気的に接続される。Example 4. Still another embodiment of the present invention will be described with reference to FIG. In the structure of FIG. 4, the substrate in the first to third embodiments is a multilayer substrate 5 including a top layer 51, an intermediate layer 52, and a bottom layer 53 in which the holes 5a for burying capacitors are formed in advance. The ground electrode 6 is soldered to the back surface, the solder material is embedded in the capacitor embedding hole 5a formed in the substrate 5, the capacitor 1 is inserted, and the whole is heated. The electrode 2b and the ground electrode 6 are welded.
After that, by connecting the electrode 2a on the side exposed on the substrate surface of the capacitor 1 embedded in the substrate 5 and the pattern 3 with a gold wire 8 or the like, the electrode lead 7 and the ground electrode 6 are connected via the capacitor 1. It is electrically connected.
【0029】図において、各層の基板51,52,53
が図1ないし図3のものと同様の厚みを有する多層基板
5であり、最上層部51の回路パターンはコンデンサ1
の電極2aと金線8を介して電気的に接続され、基板5
の最下層部53に半田付けされたアース電極6はコンデ
ンサ1の丸型電極2bと半田付けにより接続され、この
ことにより、多層基板5の最上層部51の回路パターン
と最下部53に半田付けされたアース電極6とはコンデ
ンサ1を介して相互に電気的接続がなされた構造とな
る。In the figure, the substrates 51, 52, 53 of each layer are shown.
Is a multilayer substrate 5 having a thickness similar to that of FIGS. 1 to 3, and the circuit pattern of the uppermost layer portion 51 is the capacitor 1
Is electrically connected to the electrode 2a of
The ground electrode 6 soldered to the lowermost layer portion 53 of the above is connected to the circular electrode 2b of the capacitor 1 by soldering, whereby the circuit pattern of the uppermost layer portion 51 of the multilayer substrate 5 and the lowermost portion 53 are soldered. The grounded electrode 6 is electrically connected to the grounded electrode 6 through the capacitor 1.
【0030】この実施例によれば、最上層部の回路パタ
ーンと最下層部の回路パターンとの複雑な接続が可能な
多層基板においても、コンデンサをその貫通孔に埋設し
て実装することが可能であり、これにより、コンデンサ
を最上層部に表面実装する場合に必要となる、最上層部
の回路パターンと最下層部の回路パターンとを接続する
スルーホールや、このスルーホールとコンデンサとを接
続するための電極パターンが不要となり、回路パターン
の縮小が可能となる。According to this embodiment, the capacitor can be embedded in the through hole and mounted even in a multi-layer substrate in which the circuit pattern of the uppermost layer and the circuit pattern of the lowermost layer can be connected in a complicated manner. Therefore, the through hole that connects the circuit pattern of the uppermost layer and the circuit pattern of the lowermost layer, which is necessary when the capacitor is surface-mounted on the uppermost layer, and this throughhole and the capacitor are connected. The electrode pattern for doing so becomes unnecessary, and the circuit pattern can be reduced.
【0031】なお、この多層基板5の中層部の基板52
はその基板5の最上層部51の回路パターン同士や最上
層部の回路パターンと最下層部53の回路パターンとを
スルーホールを介して電気的に接続するためのものであ
り、穴5aに相当する部分には回路パターンは形成され
ていない。The intermediate layer substrate 52 of the multilayer substrate 5
Is for electrically connecting the circuit patterns of the uppermost layer portion 51 of the substrate 5 or the circuit pattern of the uppermost layer portion and the circuit pattern of the lowermost layer portion 53 through through holes, and corresponds to the hole 5a. No circuit pattern is formed in the part to be filled.
【0032】実施例5.図5を用いて、本発明のさらに
他の実施例を説明する。図5の構造は、上記実施例1な
いし上記実施例3における基板を多層構造にするととも
に、その最下層の基板にアース電極6を半田付けしてお
き、この状態で、一方の端面に板状電極2cを有するコ
ンデンサ1を多層基板5の最上層基板51の側から最下
層基板53に向けて、穴5aに挿入する。穴5aには予
め半田材が充填されており、この状態で全体を加熱する
ことにより、半田材が溶融してコンデンサ1の電極2b
とアース電極6との溶着が行なわれる。これにより最上
層基板51表面の導体パターンとコンデンサ1の板状電
極2cとが自動的に接続される。Example 5. Still another embodiment of the present invention will be described with reference to FIG. In the structure shown in FIG. 5, the board in each of the first to third embodiments has a multi-layered structure, and the ground electrode 6 is soldered to the lowermost board, and in this state, one end face has a plate shape. The capacitor 1 having the electrode 2c is inserted into the hole 5a from the uppermost layer substrate 51 side of the multilayer substrate 5 toward the lowermost layer substrate 53. The hole 5a is filled with a solder material in advance. By heating the whole in this state, the solder material is melted and the electrode 2b of the capacitor 1 is melted.
And the ground electrode 6 are welded. As a result, the conductor pattern on the surface of the uppermost substrate 51 and the plate electrode 2c of the capacitor 1 are automatically connected.
【0033】図において、各層の基板51,52,53
が図1ないし図3のものと同様の厚みを有する多層基板
5であり、最上層部51の回路パターンはコンデンサ1
とその板状電極2c直接電気的に接続され、基板5の最
下層部53に半田付けされたアース電極6はコンデンサ
1の丸型電極2bと電気的に接続され、このことによ
り、多層基板5の最上層部51の回路パターンと最下部
53に半田付けされたアース電極6とはコンデンサ1を
介して相互に電気的接続がなされた構造となる。In the figure, the substrates 51, 52, 53 of each layer are shown.
Is a multilayer substrate 5 having a thickness similar to that of FIGS. 1 to 3, and the circuit pattern of the uppermost layer portion 51 is the capacitor 1
And the plate-shaped electrode 2c thereof are directly electrically connected to each other, and the ground electrode 6 soldered to the lowermost layer portion 53 of the substrate 5 is electrically connected to the round electrode 2b of the capacitor 1, whereby the multilayer substrate 5 The circuit pattern of the uppermost layer 51 and the ground electrode 6 soldered to the lowermost portion 53 are electrically connected to each other via the capacitor 1.
【0034】この実施例によれば、最上層部の回路パタ
ーンと最下層部の回路パターンとの複雑な接続が可能な
多層基板においても、コンデンサをその貫通孔に埋設し
て実装することが可能であり、これにより、コンデンサ
を最上層部に表面実装する場合に必要となる、最上層部
の回路パターンと最下層部の回路パターンとを接続する
スルーホールや、このスルーホールとコンデンサとを接
続するための電極パターンが不要となり、回路パターン
の縮小が可能となる。According to this embodiment, the capacitor can be embedded in the through hole and mounted even in a multi-layer substrate in which the circuit pattern of the uppermost layer and the circuit pattern of the lowermost layer can be connected in a complicated manner. Therefore, the through hole that connects the circuit pattern of the uppermost layer and the circuit pattern of the lowermost layer, which is necessary when the capacitor is surface-mounted on the uppermost layer, and this throughhole and the capacitor are connected. The electrode pattern for doing so becomes unnecessary, and the circuit pattern can be reduced.
【0035】また、その最上層部の回路パターンとコン
デンサの電極との接続を、コンデンサの板状電極にて行
なうようにしたので、最上層部に関しては、この両者の
接続のための特別なワイヤリング工程が不要となり、ま
たこの板状電極がコンデンサを挿入する際のストッパと
なるので、組立が容易となる効果もある。Further, since the circuit pattern of the uppermost layer and the electrode of the capacitor are connected by the plate electrode of the capacitor, special wiring for connecting the both is applied to the uppermost layer. This eliminates the need for steps, and since the plate electrode serves as a stopper when inserting the capacitor, there is an effect that the assembly becomes easy.
【0036】実施例6.図6を用いて、本発明のさらに
他の実施例を説明する。図6の構造は、上記実施例1な
いし上記実施例3における基板を多層構造にするととも
に、一方の端面に板状電極2cを有するコンデンサ1を
多層基板5の最下層基板53の側から最上層基板51に
向けて、穴5aに挿入し、その際、板状電極2cの最下
層基板53側に半田を載置しておき、全体を加熱するこ
とにより板状電極2cと基板5裏面のアースパターンと
を半田で溶着し、基板5表面の導体パターンとコンデン
サ1の丸型電極2bとを金線8等で接続するようにした
ものである。Example 6. Still another embodiment of the present invention will be described with reference to FIG. In the structure shown in FIG. 6, the substrates in the above-described first to third embodiments have a multi-layer structure, and the capacitor 1 having the plate-shaped electrode 2c on one end face is formed as the uppermost layer from the lowermost substrate 53 side of the multilayer substrate 5. It is inserted into the hole 5a toward the substrate 51, and at that time, the solder is placed on the lowermost layer substrate 53 side of the plate electrode 2c, and the whole is heated to ground the plate electrode 2c and the back surface of the substrate 5. The pattern is welded with solder, and the conductor pattern on the surface of the substrate 5 and the round electrode 2b of the capacitor 1 are connected by a gold wire 8 or the like.
【0037】図において、各層の基板51,52,53
が図1ないし図3のものと同様の厚みを有する多層基板
5であり、最上層部51の回路パターンはコンデンサ1
の電極2bと金線8を介して電気的に接続され、基板5
の最下層部53の回路パターンはコンデンサ1の板状電
極2cと電気的に接続され、このことにより、多層基板
5の最上層部51の回路パターンと最下部53の回路パ
ターンはコンデンサ1を介して相互に電気的接続がなさ
れた構造となる。In the figure, the substrates 51, 52, 53 of each layer are shown.
Is a multilayer substrate 5 having a thickness similar to that of FIGS. 1 to 3, and the circuit pattern of the uppermost layer portion 51 is the capacitor 1
Of the substrate 5 electrically connected to the electrode 2b of
Is electrically connected to the plate electrode 2c of the capacitor 1, so that the circuit pattern of the uppermost layer 51 and the circuit pattern of the lowermost part 53 of the multilayer substrate 5 are connected via the capacitor 1. The structure is such that they are electrically connected to each other.
【0038】この実施例によれば、最上層部の回路パタ
ーンと最下層部の回路パターンとの複雑な接続が可能な
多層基板においても、コンデンサをその貫通孔に埋設し
て実装することが可能であり、これにより、コンデンサ
を最上層部に表面実装する場合に必要となる、最上層部
の回路パターンと最下層部の回路パターンとを接続する
スルーホールや、このスルーホールとコンデンサとを接
続するための電極パターンが不要となり、回路パターン
の縮小が可能となる。According to this embodiment, the capacitor can be embedded in the through hole and mounted even in the multi-layer substrate in which the circuit pattern of the uppermost layer and the circuit pattern of the lowermost layer can be connected in a complicated manner. Therefore, the through hole that connects the circuit pattern of the uppermost layer and the circuit pattern of the lowermost layer, which is necessary when the capacitor is surface-mounted on the uppermost layer, and this throughhole and the capacitor are connected. The electrode pattern for doing so becomes unnecessary, and the circuit pattern can be reduced.
【0039】また、その最下層部の回路パターンとコン
デンサの電極との接続を、コンデンサの板状電極にて行
なうようにしたので、最下層部に関しては、この両者の
接続のための特別なワイヤリング工程が不要となり、ま
たこの板状電極がコンデンサを挿入する際のストッパと
なるので、組立が容易となる効果もある。Further, since the circuit pattern of the lowermost layer portion and the electrode of the capacitor are connected by the plate electrode of the capacitor, the special wiring for the connection between the lowermost layer portion and the electrode of the capacitor is made. This eliminates the need for steps, and since the plate electrode serves as a stopper when inserting the capacitor, there is an effect that the assembly becomes easy.
【0040】なお、この多層基板5の中層部の基板はそ
の基板5の最上層部の回路パターン同士や最上層部の回
路パターンと最下部の回路パターンとをスルーホールを
介して電気的に接続するためのものであり、穴5aに相
当する部分には回路パターンは形成されていない。The middle-layer substrate of the multi-layer substrate 5 is electrically connected to the circuit patterns of the uppermost layer of the substrate 5 or to the circuit patterns of the uppermost layer and the lowermost circuit pattern through through holes. The circuit pattern is not formed in the portion corresponding to the hole 5a.
【0041】また、この実施例においても、基板裏面に
アース電極を設けるようにしてもよく、この場合、コン
デンサを挿入した後、基板裏面とアース電極とを半田付
けする工程があるため、板状電極と基板裏面とを半田付
けする工程は、これを省略することが可能である。Also in this embodiment, the ground electrode may be provided on the back surface of the substrate. In this case, since there is a step of soldering the back surface of the substrate and the ground electrode after inserting the capacitor, there is a plate shape. This can be omitted in the step of soldering the electrode and the back surface of the substrate.
【0042】[0042]
【発明の効果】以上のように、この発明に係る厚膜混成
集積回路装置によれば、コンデンサを厚膜混成集積回路
基板に形成した貫通孔に埋め込み、その電極を金線等を
用いて基板の導電体に接続するようにしたので、コンデ
ンサを取付けるための導体パターンが不要となり、回路
パターンの縮小が可能となる。As described above, according to the thick film hybrid integrated circuit device of the present invention, the capacitor is embedded in the through hole formed in the thick film hybrid integrated circuit board, and its electrode is formed by using a gold wire or the like. Since it is connected to the conductor, the conductor pattern for mounting the capacitor is not necessary, and the circuit pattern can be reduced.
【0043】また、この発明に係る厚膜混成集積回路装
置によれば、コンデンサの電極を基板の導電体に達する
大きさのものとすることにより、コンデンサと導電体と
を直接接触させるようにしたので、金線等の接続工程が
不要となる。Further, according to the thick film hybrid integrated circuit device of the present invention, the capacitor and the conductor are brought into direct contact with each other by making the electrode of the capacitor large enough to reach the conductor of the substrate. Therefore, the step of connecting a gold wire or the like is unnecessary.
【0044】さらに、この発明に係る厚膜混成集積回路
装置によれば、基板を多層基板とするようにしたので、
多層基板を用いた厚膜混成集積回路装置においても、コ
ンデンサを介して基板の最上層と最下層を接続する際の
回路パターンの縮小が可能となる。Further, according to the thick film hybrid integrated circuit device of the present invention, since the substrate is a multi-layer substrate,
Also in a thick film hybrid integrated circuit device using a multilayer substrate, it is possible to reduce the circuit pattern when connecting the uppermost layer and the lowermost layer of the substrate via a capacitor.
【図1】この発明の一実施例によるハイブリッドIC装
置を示す構造図である。FIG. 1 is a structural diagram showing a hybrid IC device according to an embodiment of the present invention.
【図2】この発明の他の実施例によるハイブリッドIC
装置を示す構造図である。FIG. 2 is a hybrid IC according to another embodiment of the present invention.
It is a structural diagram which shows an apparatus.
【図3】この発明のさらに他の実施例における、多層基
板を使用したハイブリッドIC装置を示す構造図であ
る。FIG. 3 is a structural diagram showing a hybrid IC device using a multilayer substrate according to still another embodiment of the present invention.
【図4】この発明のさらに他の実施例における、多層基
板を使用したハイブリッドIC装置を示す構造図であ
る。FIG. 4 is a structural diagram showing a hybrid IC device using a multilayer substrate according to still another embodiment of the present invention.
【図5】この発明のさらに他の実施例における、多層基
板を使用したハイブリッドIC装置を示す構造図であ
る。FIG. 5 is a structural diagram showing a hybrid IC device using a multilayer substrate in still another embodiment of the present invention.
【図6】この発明のさらに他の実施例における、多層基
板を使用したハイブリッドIC装置を示す構造図であ
る。FIG. 6 is a structural diagram showing a hybrid IC device using a multilayer substrate according to still another embodiment of the present invention.
【図7】従来のハイブリッドIC装置を示す構造図であ
る。FIG. 7 is a structural diagram showing a conventional hybrid IC device.
1 コンデンサ 2a,2b,2c コンデンサの電極 3 導体パターン 4 スルーホール 5,51,52,53 基板 6 アース電極 7 電極リード 8 金線 1 Capacitor 2a, 2b, 2c Capacitor Electrode 3 Conductor Pattern 4 Through Hole 5, 51, 52, 53 Substrate 6 Earth Electrode 7 Electrode Lead 8 Gold Wire
Claims (3)
もにその近傍に基板表面から裏面に達する貫通孔が形成
された厚膜混成集積回路基板と、 その両端にそれぞれ電極が形成され、上記基板の貫通孔
に挿入されることにより上記基板に埋設されるコンデン
サと、 該コンデンサの電極と当該電極に対応する側の上記基板
の導電体とを接続する導電性ワイヤとを備えたことを特
徴とする厚膜混成集積回路装置。1. A thick film hybrid integrated circuit substrate, wherein a conductor is formed on each of a front surface and a back surface of the thick film hybrid integrated circuit device, and a through hole reaching from the substrate surface to the back surface is formed in the vicinity thereof, Electrodes are formed at both ends and are embedded in the substrate by being inserted into the through holes of the substrate, and a conductor that connects the electrode of the capacitor and the conductor of the substrate on the side corresponding to the electrode. Thick film hybrid integrated circuit device comprising a conductive wire.
体との電気的接続を、上記導電性ワイヤに代えて、上記
導電体に達する大きさを有するコンデンサの電極によっ
て行うことを特徴とする請求項1記載の厚膜混成集積回
路装置。2. The electrode of the capacitor and the conductor of the substrate are electrically connected by an electrode of the capacitor having a size reaching the conductor instead of the conductive wire. Item 3. The thick film hybrid integrated circuit device according to item 1.
する請求項1または2記載の厚膜混成集積回路装置。3. The thick film hybrid integrated circuit device according to claim 1, wherein the substrate is a multi-layer substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21723492A JPH0645513A (en) | 1992-07-22 | 1992-07-22 | Thick film hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21723492A JPH0645513A (en) | 1992-07-22 | 1992-07-22 | Thick film hybrid integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0645513A true JPH0645513A (en) | 1994-02-18 |
Family
ID=16700956
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21723492A Pending JPH0645513A (en) | 1992-07-22 | 1992-07-22 | Thick film hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0645513A (en) |
-
1992
- 1992-07-22 JP JP21723492A patent/JPH0645513A/en active Pending
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