JPH0644611B2 - Non-volatile semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention uses a non-volatile transistor as a memory cell. Data writing is performed electrically and erasing is performed by irradiating ultraviolet rays. The present invention relates to a nonvolatile semiconductor memory.

(Prior Art) Nonvolatile semiconductor memory capable of erasing data is EPRO
M (Erasable and Programmable Read Only Memory)
Among them, one in which data is erased by irradiation of ultraviolet rays is particularly called a UV-EPROM. In this UV-EPROM, a double gate non-volatile transistor in which a floating gate electrode (floating gate electrode) and a control gate electrode (control gate electrode) are stacked on a channel region between source and drain regions is used as a memory cell. Has been done.

FIG. 6 is an equivalent circuit diagram of a memory cell array portion of a conventional UV-EPROM using the memory cell having such a structure. In the figure, 50 are memory cells each made up of the above-mentioned nonvolatile transistors.
The 50s are arranged in a matrix. The drains of the memory cells 50 arranged in the same row in the row direction, which is the horizontal direction in the figure, are commonly connected to one of the plurality of bit lines 51 and arranged in the same row. The sources of the memory cells 50 are commonly connected to any of the plurality of ground lines 52. The control gate electrodes of the memory cells 50 arranged in the same column in the column direction, which is the vertical direction in the figure, are commonly connected to any of the plurality of row lines 53.

Thus, in a conventional EPROM, a 1-bit memory cell
Each of the memory cells 50 is connected to the corresponding bit line 51, ground line 52 and row line 53 by using one nonvolatile transistor.

That is, in the conventional UV-EPROM, three wirings including a bit line, a ground line and a row line are required for each bit. Moreover, the drain of each cell consists of a diffusion region,
The bit line is composed of a metal wiring such as aluminum, and it is necessary to form a contact when connecting each cell to the corresponding bit line. The contact formation position usually requires a larger area than the wiring width.
Therefore, there is a problem that it is difficult to realize a high-density UV-EPROM in the related art. In addition, the manufacturing yield decreases as the number of contacts increases.

(Problems to be Solved by the Invention) As described above, conventionally, three wirings are required for each bit and it is necessary to form a contact for each bit, which realizes high density. It is inhibiting. Therefore, an object of the present invention is to provide a non-volatile semiconductor memory that can achieve high density by reducing the number of wirings and the number of contacts.

[Structure of the Invention] (Means for Solving the Problems) A nonvolatile semiconductor memory of the present invention comprises a nonvolatile transistor having a floating gate electrode and a control gate electrode, both electrodes being formed in a self-aligned manner. A plurality of series circuits in which two or more memory cells are connected in series and are arranged in a matrix, and one end of each of the series circuits arranged in the same column among the plurality of series circuits is commonly connected. A plurality of rows which are provided in common to the bit lines and the series circuits arranged in the same row among the plurality of series circuits and which are respectively connected to the control gate electrodes of the memory cells forming the series circuits. And selectively supplying a voltage to the bit line and the row line to select a line and a memory cell in the series circuit of the plurality of series circuits. And supplying a first voltage to the row line to which the selected memory cell is connected, and the remaining row to which other memory cells in one series circuit including the selected memory cell are connected. Each line is provided with a second voltage, and the other row lines are provided with a third voltage for preventing the memory cells connected to them from operating.

(Operation) In the nonvolatile semiconductor memory of the present invention, a high voltage is applied to the row line connected to the control gate electrode of the non-selected cell at the time of writing and reading data and the row connected to the control gate electrode of the selected cell. A voltage lower than this is applied only to the line. A read voltage is applied to the bit line when reading data, and a voltage according to the write data is applied to the bit line when writing data.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of a memory cell array portion when the present invention is applied to a UV-EPROM. In the figure, 10 is a series circuit composed of four memory cells 11 connected in series. Each memory cell 11 in each series circuit 10 has a source and drain region, a floating gate electrode provided on the channel region between the source and drain regions, and a control gate electrode provided on the floating gate electrode. Consisting of 2
It is composed of a heavy gate type non-volatile transistor.
Further, a plurality of these series circuits 10 are arranged in a matrix, and one end of each series circuit 10 has a plurality of bit lines 12 ₁ , 12 ₂ , ...
It is connected to either of 12 _N and the other end is 0V
Is connected to any one of a plurality of ground lines 13 ₁ , ... 13 _M to which the voltage is applied. Further, the control gate electrodes of each of the four memory cells 11 in the series circuit 10 have four row lines 14 respectively.
_{11, 14 21, ... 14 41} ~14 1M, 14 2M, ... 14 are connected to respective _4M, each of these four row lines 14 _1, 14 _2, ... 14 ₄ is a horizontal direction in FIG. Multiple series circuits arranged in rows
Wired in common for 10.

Each of the above four row lines 1411, 1412, 1413, 1414, ... 141M, 14
An output voltage from a row decoder (not shown) is supplied to 1M, 141M, and 141M.

An element structure in the case where a UV-EPROM having such a circuit structure is actually realized on a semiconductor chip is shown in a pattern plan view of FIG. 2, and a cross-sectional structure taken along a line II ′ in FIG. Each is shown in the sectional view of the figure. In this UV-EPROM, for example, a P-type silicon semiconductor substrate is used as the substrate 20. In the surface region of the substrate 20, N ⁺ type regions 21 serving as the source and drain regions of the four memory cells 11 forming each of the series circuits 10 are separately formed by a diffusion method or the like. And in FIG. 2, N ⁺ -type region 21A located respectively at the top and bottom, 21B are shared by the series circuit 10 adjacent to each other, these N ⁺ -type region 21
A and 21B are used as the ground line 13. Further, each N ⁺ type region located between the above N ⁺ type regions 21A and 21B.
Each metal wiring 23 made of, for example, aluminum is connected to 21C through a contact hole 22, respectively. Each of these metal wirings 23 is used as the bit line 12. Further, between each N ⁺ type region 21, an electrode 24 which is made of a first-layer polycrystalline silicon layer and electrically floated is formed via an insulating film. These electrodes 24 form the floating gate electrodes of each memory cell 11. Further, in FIG. 2, an electrode 25 composed of a second-layer polycrystalline silicon layer is formed over a plurality of electrodes 24 arranged in the lateral direction via an insulating film.
These electrodes 25 form the control gate electrode of each memory cell 11 and the row line 14.

That is, in this memory, each series circuit 10 is configured by four memory cells 11 connected in series, one end of each series circuit 10 is connected to the bit line 12 formed of the multi-layer wiring 23, and the other end is N ^+. In addition to being connected to the ground line 13 formed of the mold region 21A or 21B, the control gate electrode of each memory cell 11 is connected to the row line 14 constituted by the electrode 25.

Here, as shown in FIGS. 2 and 3, the width of the electrode 24 constituting the floating gate electrode and the electrode 25 constituting the control gate electrode, that is, the electrode 24 in the direction orthogonal to the extension direction of the electrode 25, The dimensions of 25 are the same and both electrodes 24, 25 are arranged to overlap each other, so that both electrodes 24, 25 are formed in a so-called self-aligned manner.

Next, the operation of the memory configured as described above will be described.

Generally, the operation modes of the UV-EPROM include data read mode, write mode and erase mode. First, the operation in the data read mode will be described with reference to the timing chart of FIG. Of the four row lines 14 connected to the series circuit 10 including the cell to be selected in this mode,
A voltage of about 2V to 5V is applied only to the row line to which the control gate electrode of the selected cell is connected, and a voltage of about 5V to 10V is applied to the remaining three row lines. In addition,
The other four row lines are all set to OV. Here, for example, the series circuit 10 containing the cells to be selected is connected to the bit line 12 ₁ and four row lines 14 _{11 to} 14 ₄₁ , and the cells to be selected are connected to the row line 14 _21. When it is
4 only to the row line 14 _{11-14 41} of which row line 14 ₂₁ voltage of about 2V~5V is applied, the remaining three row lines 5V~10V
A certain amount of voltage is added. Here, the threshold voltage of each memory cell 11 is set in advance according to the write state in the data write mode operation, and the voltage of 2V to 5V is lower than the lower threshold voltage of the cell in the erased state, for example. The voltage is high and lower than the high threshold voltage after “1” is written, and the voltage of 5V to 10V is “1”.
Is sufficiently higher than the high threshold voltage after being written. Therefore, such a voltage is applied to the four row lines 14 _{11 to} 14 _41.
Is applied to the three row lines 14 except the row line 14 _21.
11, 14 _31, 14 ₄₁ to the control gate electrode 3 of the memory cells connected 11 becomes sufficiently turned on. On the other hand, the selected cell to the row line 14 ₂₁ control gate electrode is connected on in accordance with the threshold voltage, the off state is determined.

On the other hand, each cell in the unselected series circuit connected to the row line to which the voltage of 0V is applied does not operate and its state does not change.

In this data read mode, the corresponding bit line
A read voltage of 2 V is applied to 12 ₁ . Here are lower threshold voltage of the selected cell, if it is a voltage in the on state of the row lines 14 _21, the read voltage of 2V applied to bit line 12 ₁ via the series circuit 10 It is discharged to the ground line 13 _{1 of} 0V. On the other hand, if the threshold voltage of the selected cell is set high and remains in the off state even when the voltage of the row line 14 ₂₁ is applied, the read voltage of 2 V applied to the bit line 12 ₁ is maintained as it is. To be done. In this way, the voltage of the bit line 12 differs depending on whether the threshold voltage of the selected cell is high or low. By amplifying the potential difference by a sense amplifier circuit (not shown) connected to the bit line 12, a logical "1", The judgment of "0" is performed. The voltage applied to the row line 14 connected to the non-selected cell is 5V to 10V.
However, it is usually preferable to set the voltage to about 8 V from the viewpoint of characteristics and reliability.

Next, the operation in the data write mode will be described with reference to the timing chart of FIG. 4 row lines connected to the series circuit 10 containing the cells to be selected in this mode
Among the fourteen, a voltage of 10V is applied only to the row line to which the control gate electrode of the selected cell is connected, and a voltage of 20V is applied to the remaining three row lines. In addition, each other 4
The row lines of the book are all set to 0V. Here, for example, as in the read mode, the series circuit 10 including the cells to be selected is connected to the bit line 12 ₁ and the four row lines 14 _{11 to} 14 ₄₁ , and the cells to be selected are selected. If There it is assumed that is connected to the row line 14 _21, four being the row line 14 ₁₁ voltage to 14 ₄₁ among the row lines 14 ₂₁ only 10V is applied, 20V voltage of the remaining three row lines Is applied. Further, two kinds of different voltages on the basis of the write data to the bit line 12 ₁ corresponding in this data write mode is applied. For example, when writing "1" data, a voltage of 10V is applied to the bit line 12 _1, and when writing "0" data, a voltage of 0V is applied to the bit line 12 ₁ .

Here, since the voltage of 20 V applied to the three row lines 14 ₁₁ , 14 ₃₁ , and 14 ₄₁ excluding the row line 14 ₂₁ is supplied to the control gate electrode, the three memory cells 11 each operate as a triode. , Bit line 12 ₁ in the source / drain region of the selected cell
The voltages of the ground line 13 ₁ and the ground line 13 ₁ are applied almost as they are. At this time, if the voltage of 10V to the bit line 12 ₁ is applied, electrons move toward the drain region from the source region of the selected cell. Then, an electric field is concentrated on the depletion layer generated especially near the drain region, and the electrons are accelerated thereby, and sufficient energy is given from the surface of the substrate 20 in FIG. 3 to cross the energy barrier of the insulating film. Such electrons are called hot electrons, and these electrons are attracted to the control gate electrode of the selected cell set to a high voltage of 10 V, jump into the floating gate electrode, and are trapped there. As a result,
The floating gate electrode of the selected cell is negatively charged, and its threshold voltage rises and rises. On the other hand, if the voltage of 0V to the bit line 12 ₁ is applied, electrons travel as described above does not occur, the threshold voltage remains original low state.

The data erasing mode is called an electron emission mode and is performed by irradiating all the cells 11 with ultraviolet rays. Electrons injected into the floating gate electrode in the data write mode are excited by ultraviolet rays and are emitted to the control gate electrode or the substrate over the barrier of the insulating film. This lowers the threshold voltage of each cell.

As described above, in the memory of the above embodiment, data can be read and written bit by bit. Moreover, in forming the memory cell array, conventionally, one bit line was required for each bit, but in the above embodiment, four memory cells are connected in series to use four bit lines. Only one bit line is needed per cell. For this reason,
The number of wires can be significantly reduced as compared with the conventional one. Also, the number of contact holes for the bit lines can be reduced as compared with the conventional case. Therefore, in this embodiment, a high density UV-EPROM can be easily realized. In addition, since the number of contacts is reduced, the manufacturing yield can be expected to be significantly improved.

It is needless to say that the present invention is not limited to the above embodiment and various modifications can be made. For example, in the above-mentioned embodiment, only the row line to which the selected cell is connected among the four row lines 14 in the data read mode is 2V-5V.
A voltage in the range of V is applied, and 5V to 1 is applied to the remaining three row lines.
The case of applying a voltage in the range of 0 V has been described, but these voltages are set to "1" of the memory cell 11,
It should be set according to the threshold voltage corresponding to "0". In addition, the 2V read voltage applied to the bit line 12 can be varied as desired. The read voltage is preferably set as low as possible in order to suppress the so-called soft write phenomenon (weak writing in the read mode).

Further, in the above embodiment, 4 in the data write mode.
Only the row line to which the selected cell is connected among the row lines 14 of the book 10
The case where a voltage of V is applied and a voltage of 20 V is applied to the remaining three row lines has been described. This is because a sufficient amount of electrons are injected into the floating gate electrode of the selected cell,
In addition, a high voltage that allows the non-selected cells to operate as a triode is sufficient.

In the memory of the above embodiment, the case where four memory cells are connected in series to form the series circuit 10 has been described.
The number of wirings may be two or more, and the number of wirings can be further reduced by using, in addition to four, eight, 16 or 32 memory cells connected in series. For example, if eight memory cells are connected in series to form the series circuit 10, the degree of integration is more than double that of the conventional memory. Further, with the improvement in the degree of integration, the price can be significantly reduced.

Furthermore, in the above-described embodiment, the case where the row line 14 is made of polycrystalline silicon has been described. However, this may be made of refractory metal silicide, for example, molybdenum silicide, titanium silinside, or refractory metal only. Good.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a non-volatile semiconductor memory capable of realizing high density by reducing the number of wirings.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell array portion of a memory according to an embodiment of the present invention, FIG. 2 is a pattern plan view showing an element structure when the circuit of FIG. 1 is realized on a semiconductor chip, and FIG. Is a sectional view of a part of the element shown in FIG. 2, FIGS. 4 and 5 are timing charts of the above-mentioned memory, and FIG. 6 is an equivalent circuit diagram of the memory cell array portion of the conventional memory. 10 …… series circuit, 11 …… memory cell, 12 …… bit line,
13 ... Ground wire, 14 ... Row wire, 20 ... Board, 21, 21A, 21
B, 21C ... N ⁺ type region, 22 ... Contact hole, 23
…… Metal wiring, 24,25 …… Electrodes.

Claims (5)

[Claims] 1. A plurality of memory cells, each of which has a floating gate electrode and a control gate electrode, both electrodes being formed in a self-aligned manner and which is composed of a non-volatile transistor, are connected in series and arranged in a matrix. Of the plurality of series circuits, a bit line to which one end of each of the series circuits arranged in the same column is commonly connected, and a plurality of series circuits arranged in the same row. A plurality of row lines that are provided in common to the series circuits and that are respectively connected to the control gate electrodes of the memory cells that form each of the series circuits, and one of the plurality of series circuits that is one of the series circuits. Voltage is selectively supplied to the bit line and the row line to select the memory cell of the memory cell, and the first voltage is supplied to the row line to which the selected memory cell is connected. , A second voltage is supplied to each of the remaining row lines to which the other memory cells in the one series circuit including the selected memory cell are connected, and each of the other row lines is connected to them. And a means for supplying a third voltage such that the memory cell does not operate. 2. The nonvolatile semiconductor memory according to claim 1, wherein the second voltage is set higher than the first voltage and the third voltage is set to 0V. 3. The nonvolatile semiconductor memory according to claim 1, wherein each of the plurality of row lines is made of polycrystalline silicon. 4. The nonvolatile semiconductor memory according to claim 1, wherein each of the plurality of row lines is made of a refractory metal silicide. 5. The nonvolatile semiconductor memory according to claim 1, wherein each of the plurality of row lines is made of a refractory metal.