JPH0644194A - Parallel processor device - Google Patents

Abstract

PURPOSE:To flexibly set an area concerning the fetching and transmission of data of a parallel processor with simple configuration. CONSTITUTION:ROM 9 where control data is stored is accessed as the output of a counter 4 which counts the order of data to be fetched or transmitted as an address and the data fetch judging circuits 10-1 to 10-n or data transmission judging circuit 11-1 to 11-n of the respective processors 1-1 to 1-n are driven by the output value and it is judged whether the processor 1-1 to 1-n fetches data or transmits data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for fetching and sending data from each processor of a parallel processor device. The present invention relates to a parallel processor device capable of flexibly performing area setting for data acquisition and transmission with a simple configuration.

[0002]

2. Description of the Related Art In a conventional parallel processor device, for example, a plurality of processors 1-1 to 1-n shown in FIG.
There is a type in which necessary portions as shown in FIG. 4A are respectively fetched and processed, and the processing result is sent to the data output bus 3 at a required timing as shown in FIG. 4B.

In such processing, as shown in FIG. 5, in the case of data acquisition, the order of data flowing on the data input bus 2 and the order of data to be transmitted on the data output bus (not shown) are set. For the counting horizontal and vertical counters 4-1 and 4-2, a minimum value register 5 and a maximum value register 6 indicating a horizontal range, and a minimum value register 7 and a maximum value register 8 indicating a vertical range. , The horizontal counter 4-1 and the minimum value register 5, the maximum value register 6 and the comparators 12-1 and 12
Value of horizontal register 5 ≤ x ≤ register 6 by -2
The vertical counter 4-2 and the minimum value register 7, the maximum value register 8 and the counters 4-1 given by the values of the vertical register 7 ≦ y ≦ the value of the register 8 by the comparators 12-3 and 12-4. In the case of the data in the range of the value x of the counter 4-2 and the value y of the counter 4-2, it is realized by opening and taking in the gate 13. Similarly, in the data transmission, the transmission timing to the data output bus (not shown) is counted by the counter and determined by the minimum value register 7, the maximum value register 8, the comparators 12-3 and 12-4 and the output gate (not shown). Was there.

[0004]

According to such a conventional data fetching and sending method, there is no problem as long as there is one rectangle as shown in FIGS. 4 (a) and 4 (b). If the capture is not rectangular or you try to specify two or more areas, the above-mentioned methods for capture and transmission will complicate the maximum / minimum value registers, comparators, etc. There is a problem that it takes a few minutes.

The present invention solves such a problem, and an object of the present invention is to provide a parallel processor device capable of flexibly performing area setting for data fetching and sending with a simple configuration.

[0006]

According to a first aspect of the present invention, in a parallel processor device in which a plurality of processors are connected in parallel to a data input bus and each processor is provided with a data fetch determination circuit, the data input bus is It is provided with a counter for counting the order of the flowing data, and a ROM in which the output of this counter is used as an address input and the logic for taking in decision is written in advance. The taking in decision circuit is translated into the read output value of the ROM. It is characterized in that it includes means for judging whether or not to take in the data on the data input bus according to the logic.

In a second aspect of the present invention, a plurality of processors are connected to a data output bus in parallel, and each processor calculates the order of data flowing through the data output bus in a parallel processor device having a data transmission determination circuit. And a ROM in which the logic of the transmission determination is written in advance by using the output of this counter as an address input, and the data transmission determination circuit is configured to operate according to the translated logic obtained in the read output value of the ROM. It is characterized in that it includes means for judging whether or not to send out data on the data output bus.

RAM or PROM instead of the ROM
Can be provided.

[0009]

The memory (for example, ROM) in which the control data is stored is accessed by using the output of the counter for counting the order of the data to be fetched or transmitted as an address. Pre-translated decision logic is written here.

The read output value drives the data acquisition determination circuit or the data transmission determination circuit of each processor to determine whether the processor acquires or transmits the data.

As a result, the processing on the processor side is simplified, and it becomes possible to control fetching or sending dot by dot according to the order of the data on the input or output bus, and by changing the value of the memory. With a simple circuit, the range of acquisition or transmission can be made into any shape including a rectangle, and it is possible to easily specify two or more areas.

Further, if RAM or PROM is used as the memory, it is possible to dynamically change the range of fetching and sending while keeping the shape and the number in an arbitrary shape.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

According to the embodiment of the present invention, a plurality of processors 1-1 to 1-n are connected in parallel to a data input bus 2 and a data output bus 3, and a data fetch determination circuit is provided to each of the processors 1-1 to 1-n. And a counter 4 for counting the order of the data flowing through the data input bus 2 and the data output bus 3 and a logic for judging in advance the output of this counter 4 as an address input. And a ROM in which a plurality of data acquisition determination circuits 10-1 to 10-n are provided.
Includes means for judging whether or not to take in the data on the data input bus 2 according to the translated logic obtained in the read output value of the ROM 9, and the data transmission judging circuit 11-
1 to 11-n include means for deciding whether or not to output data on the data output bus 3 according to the translated logic obtained in the read output value of the ROM 9. A RAM or a PROM can be provided instead of the ROM 9.

Next, the operation of the embodiment of the present invention thus constructed will be described.

The operations of the processors 1-1 to 1-n to fetch necessary data from the data flowing on the data input bus 2 are performed in the same manner as in the prior art, but the order of the data flowing on the data input bus 2 is as follows. The output of the counter 4 which counts is supplied as the address of the ROM 9 which stores the fetch control data.

As for the contents of the ROM 9, one word (n bits) to be read corresponds to the fetch control data of each of the processors 1-1 to 1-n. For example, if it is fetched when the control data is 1, it is as shown in FIG. At addresses t and t
Depending on the control data read at +1, the processor 1-1 is at t, and the processor 1-n is at t + 1.
So as to capture the data on the data input bus 2 of each processor 1-1 to 1-n.
1 to 10-n are driven so that the data on the data input bus 2 can be taken in by the required processors 1-1 to 1-n. The processing results of the processors 1-1 to 1-n are selectively sent to the data output bus 3, but the output of the counter 4 for counting the order of the data sent to the data output bus 3 stores the sending control data. It is supplied as a ROM address. One word (n bits) read from the ROM drives the data transmission determination circuits 11-1 to 11-n of the processors 1-1 to 1-n, and the processor 1-1 required for the data output bus 3 is provided. It is possible to send the processing results of ~ 1-n.

[0018]

As described above, according to the present invention, the processing on the processor side can be simplified and the control of fetching or sending dot by dot can be performed in accordance with the order of data on the input or output bus. , RO as memory
By changing the value of M, the range of acquisition and transmission can be made into any shape including rectangle by a simple circuit,
There is an effect that it is possible to easily specify two or more areas.

A rewritable RA in place of the ROM
By providing the M or PROM, there is an advantage that the range of fetching and sending can be dynamically changed while keeping an arbitrary shape and number.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of control data in the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

FIG. 4A and FIG. 4B are views for explaining data acquisition and transmission in a conventional example.

FIG. 5 is a diagram illustrating an operation in the case of data input in the conventional example.

[Explanation of symbols]

 1-1 to 1-n processor 2 data input bus 3 data output bus 4, 4-1, 4-2 counter 5, 7 minimum value register 6, 8 maximum value register 9 ROM 10-1 to 10-n data acquisition determination Circuits 11-1 to 11-n Data transmission determination circuit 12-1 to 12-4 Comparator 13 Gate

Claims (3)

[Claims] 1. A parallel processor device in which a plurality of processors are connected in parallel to a data input bus, and each processor has a data fetch determination circuit, and a counter for counting the order of data flowing through the data input bus, And a ROM in which the logic of the fetch determination is written in advance by using the output of the counter as an address input, and the fetch determination circuit is configured to read the data on the data input bus according to the translated logic obtained in the read output value of the ROM. A parallel processor device including means for determining whether or not to take in. 2. A parallel processor device in which a plurality of processors are connected in parallel to a data output bus, each processor having a data transmission determination circuit, and a counter for calculating the order of data flowing through the data output bus, And a ROM in which the logic of the transmission determination is written in advance by using the output of the counter as an address input, and the data transmission determination circuit is arranged on the data output bus according to the translated logic obtained as the read output value of the ROM. A parallel processor device including means for determining whether or not to send data. 3. A RAM or a PRO in place of the ROM.
The parallel processor device according to claim 1, wherein M is provided.