JPH0640543B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0640543B2 JPH0640543B2 JP58222034A JP22203483A JPH0640543B2 JP H0640543 B2 JPH0640543 B2 JP H0640543B2 JP 58222034 A JP58222034 A JP 58222034A JP 22203483 A JP22203483 A JP 22203483A JP H0640543 B2 JPH0640543 B2 JP H0640543B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate
- film
- drain
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体装置の製造方法に係り、特にドレイン
耐圧およびホツトキヤリア耐圧の高いＬＤＤ（Ligh tly
Doped Drain）構造をもつMOSFETの製造に好適な半導体
装置の製造方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an LDD (Ligh tally) having high drain breakdown voltage and photocarrier breakdown voltage.
The present invention relates to a semiconductor device manufacturing method suitable for manufacturing a MOSFET having a Doped Drain structure.
従来ＬＤＤ構造のMOSFETの製造には、ゲート電極の加工
後、ＳｉＯ２膜もしくはＰＳＧ（リン硅酸ガラス）膜を
全表面に被着し、それを異方性ドライエツチしてゲート
側壁にＳｉＯ２もしくはＰＳＧを残存させる方法を用い
ていた。しかし、この場合ソース・ドレイン領域上にあ
つたゲート絶縁膜と同じ膜厚のＳｉＯ２がエツチングさ
れＳｉ基板が直接イオン衝撃を受ける。このためＳｉ表
面が損傷を受け、ソース・ドレインの接合のリーク電流
が増加するという問題があつた。さらに、素子分離領域
のＳｉＯ２もエツチングされ、寄生容量が増大する欠点
があつた。Conventionally, in the manufacture of a MOSFET having an LDD structure, after processing a gate electrode, a SiO 2 film or a PSG (phosphosilicate glass) film is deposited on the entire surface, and anisotropic dry etching is performed to form SiO 2 or SiO 2 on a gate sidewall. The method of leaving PSG was used. However, in this case, SiO 2 having the same film thickness as the gate insulating film on the source / drain regions is etched and the Si substrate is directly subjected to ion bombardment. As a result, the Si surface is damaged and the leak current at the source / drain junction increases. In addition, SiO 2 in the element isolation region is also etched, resulting in an increase in parasitic capacitance.
本発明の目的は、上記従来の問題を解決し、Ｓｉ基板が
直接イオン衝撃を受けることなく、ＬＤＤ構造を実現
し、ソース・ドレイン接合のリーク電流が十分小さい半
導体装置の製造方法を提供することである。An object of the present invention is to solve the conventional problems described above, to provide an LDD structure without directly receiving an ion bombardment on a Si substrate, and to provide a method for manufacturing a semiconductor device having a sufficiently small leak current at a source / drain junction. Is.
本発明は、従来不可能であつたシリコン窒化膜のＳｉＯ
２に対する高選択な異方性エツチングが、Ｃ，Ｈ，Ｆを
含み、Ｆ対Ｈの比がほぼ２以下であるガスを反応ガスに
するドライエツチングで可能であるという新規な知見に
基づいてなされたものであり、ＣＨ３ＦもしくはＣＨ２
Ｆ２を用いれば極めて好ましい結果が得られる（これら
のガスを単独もしくは混合して使用できることはいうま
でもない）。この高選択、異方性エツチングを用いるこ
とにより、ドライエツチングにおいてＳｉ基板を直接イ
オン衝撃することなく、ＬＤＤ構造を実現でき、したが
ってソース・ドレイン接合のリーク電流を低減できる。The present invention is not possible with the conventional silicon nitride film made of SiO 2.
Highly selective anisotropic etching for 2, C, H, includes F, made on the basis of the novel finding that ratios of F to H are possible dry Etsu quenching of the reaction gas of the gas is approximately 2 or less CH 3 F or CH 2
Very good results are obtained with F 2 (it goes without saying that these gases can be used alone or in combination). By using this highly selective and anisotropic etching, the LDD structure can be realized without direct ion bombardment of the Si substrate in dry etching, and therefore the leak current of the source / drain junction can be reduced.
本発明の一実施例を第１図により説明する。第１図(a)
に示すように、ｐ型１０Ω・cmのＳｉ基板(1)上に通常
の半導体製造工程により、素子分離領域には0.6μｍの
厚い熱酸化膜(2)を選択的に形成し、能動領域には20nm
の薄い熱酸化膜(3)を形成した。その後、全表面に、Ｗ
(4)を0.3μｍスパツタ蒸着し、さらにその上にＰＳＧ
（リン硅酸ガラス(5)をＣＶＤ（化学気相蒸着）した。
その後、第１図(a)に示すように、通常の写真蝕刻法に
より、ゲート電極パターンを形成した、ＰＳＧおよびＷ
はそれぞれ、ＣＨＦ３ガス、ＳＦ６ガスを用いてドライ
エツチングした。またＷ上にＰＳＧを設けたのは、ソー
ス・ドレインのイオン打ち込みの際チヤネリングにより
ゲート下にｎ型不純物が導入されるのを防止するためで
ある。つぎにリンを加速電圧１００kV、打ち込み量３×
1013cm-2の条件でイオン打ち込みし、ソース・ドレイン
領域に低濃度のｎ型不純物層(6)を形成する。その後、
第１図(b)に示すように全面にＳｉ３Ｎ４(7)をＣＶＤ法
で0.3μｍの厚さに形成した。しかる後ＣＨ２Ｆ２ガス
を用いてＳｉ３Ｎ４を異方性エツチし、ゲート側壁にＳ
ｉ３Ｎ４(8)を残存させた。エツチングは、0.3μｍのＳ
ｉ３Ｎ４をエツチングする時間の10％オーバーに行なつ
たが、このときのソース・ドレインの上の薄いＳｉＯ２
(3)の膜厚減少量は約１nmにすぎなかつた。したがつ
て、ソース・ドレインのＳｉが直接イオン衝撃されるこ
とがなく、Ｓｉ基板が損傷を受けることがなかつた。ま
たイオン打ち込みのチヤネリング防止のＰＳＧ膜(5)も
３nmしか膜厚減少しなかつた。次に、ヒ素を加速電圧８
０kV、打ち込み量５×1015cm-2の条件でイオン打ち込み
し、ソース・ドレイン領域の高濃度ｎ型不純物層(9)を
形成した。その後通常の半導体製造工程に従い、パツシ
ベーション膜としてＰＳＧ(10)を被着し、コンタクト穴
加工、およびＡ電極配線(11)を行なつて、ＬＤＤ構造
を持つＭＯＳ−ＦＥＴを製作した。An embodiment of the present invention will be described with reference to FIG. Fig. 1 (a)
As shown in Fig. 3, a 0.6μm thick thermal oxide film (2) is selectively formed in the element isolation region on the Si substrate (1) of p-type 10Ω · cm by the normal semiconductor manufacturing process, and the active region is formed. Is 20 nm
A thin thermal oxide film (3) was formed. After that, W on all surfaces
(4) is 0.3μm sputtered and PSG is deposited on it.
(Phosphorus silicate glass (5) was subjected to CVD (chemical vapor deposition).
Then, as shown in FIG. 1 (a), PSG and W were formed with a gate electrode pattern by an ordinary photo-etching method.
Were dry-etched using CHF 3 gas and SF 6 gas, respectively. Further, PSG is provided on W to prevent n-type impurities from being introduced under the gate due to channeling at the time of source / drain ion implantation. Next, phosphorus is used at an acceleration voltage of 100 kV and an implantation amount of 3 ×
Ions are implanted under the condition of 10 13 cm -2 to form a low concentration n-type impurity layer (6) in the source / drain regions. afterwards,
As shown in FIG. 1 (b), Si 3 N 4 (7) was formed on the entire surface by CVD to a thickness of 0.3 μm. After that, Si 3 N 4 is anisotropically etched using CH 2 F 2 gas, and S is deposited on the side wall of the gate.
i 3 N 4 (8) was left. Etching is 0.3 μm S
The etching time for i 3 N 4 was over 10%, but the thin SiO 2 on the source / drain at this time was over.
The thickness reduction amount of (3) was only about 1 nm. Therefore, the Si of the source / drain was not directly bombarded with ions, and the Si substrate was not damaged. Moreover, the film thickness of the PSG film (5) for preventing ion implantation channeling was reduced by only 3 nm. Next, arsenic is accelerated at an acceleration voltage of 8
Ion implantation was performed under the conditions of 0 kV and an implantation amount of 5 × 10 15 cm -2 to form a high concentration n-type impurity layer (9) in the source / drain regions. Then, according to a normal semiconductor manufacturing process, PSG (10) was deposited as a passivation film, contact hole processing and A electrode wiring (11) were performed to manufacture a MOS-FET having an LDD structure.
本発明の製造方法で製作したＭＯＳ−ＦＥＴは、従来の
ソース・ドレインを１回のイオン打ち込みで形成した構
造のＭＯＳＦＥＴに対し、ゲートのチヤネル長1.5μｍ
の素子で約２Ｖのドレインでレークダウン電圧の向上が
図られた。ドレインとＳｉ基板の接合のリーク電流は、
従来のゲート側壁にＳｉＯ２またはＰＳＧを残存させた
場合ソース・ドレインのＳｉ基板が直接イオン衝撃され
ることにより、ドレイン電圧５Ｖで８×10-11Ａであつ
たのに対し、本実施例に示した素子では、５×10-12Ａ
以下となつた。したがつて、リーク電流は１桁以上低減
できた。The MOS-FET manufactured by the manufacturing method of the present invention has a gate channel length of 1.5 μm as compared with the conventional MOSFET having a structure in which the source and drain are formed by one-time ion implantation.
In the device of No. 2, the rake voltage was improved with a drain of about 2V. The leakage current of the junction between the drain and the Si substrate is
When SiO 2 or PSG is left on the side wall of the gate in the related art, the Si substrate of the source / drain is directly bombarded with ions, resulting in 8 × 10 −11 A at a drain voltage of 5 V. In the element shown, 5 × 10 -12 A
The following. Therefore, the leak current could be reduced by one digit or more.
実施例２ 第２図(a)に示すように、ｐ型10Ω・cmのＳｉ基板(51)
上に通常の半導体製造工程により、素子分離領域には0.
6μｍの厚い熱酸化膜(52)を選択的に形成し、能動領域
には20nmの薄い熱酸化膜(53)を形成した。その後、前表
面にＷ(54)を0.3μｍスパツタ蒸着し、更にその上にＰ
ＳＧ（リン硅酸ガラス）(55)をＣＶＤ法により0.1μｍ
蒸着した。その後第２図(a)に示すように通常の写真蝕
刻法により、ゲート電極パターンを形成した。この時、
ＰＳＧはＣＨＦ３ガスを用いてドライエツチした。ま
た、ＷはＳＦ６ガスを用いてドライエツチしたが、この
エツチングは0.3μｍのＷをエツチングする時間の10％
オーバに行なつた結果ＰＳＧに対しＷが片側で0.1μｍ
細くなつた。オーバエツチ時間の調整により、このＷの
細りは加減できる。次に第２図(b)に示すように全面に
Ｓｉ３Ｎ４(57)をＣＶＤ法で0.3μｍの厚さに形成し
た。しかる後ＣＨ２Ｆ２ガスを用いてこのＳｉ３Ｎ４を
異方性エツチし、ＰＳＧの庇の下のゲート側壁のＳｉ３
Ｎ４(58)を残存させた〔第２図(c)〕。エツチングは、
0.3μｍのＳｉ３Ｎ４をエツチングする時間の50％オー
バに行ない、ＰＳＧの庇の下部のＳｉ３Ｎ４(58′）の
みを残すようにした。この時、ソース・ドレイン上の薄
いＳｉＯ２(3)は５nm程しか減少せず、Ｓｉが直接イオ
ン衝撃されることもなかつた。次にヒ素を加速電圧80k
V、打ち込み量５×1015cm-3の条件でイオン打ち込み
し、ソース・ドレイン領域の高濃度不純物層(59)を形成
した〔第２図(d)〕。次に、第２図(e)に示すように、ソ
ース・ドレイン上の薄いＳｉＯ２(53)をドライエツチで
除去し、熱処理をして、そのダメージを回復させた。こ
の時の条件は９５０℃１０分のＮ２アニールであつた。
この後、全面に１００nmのＰｔをスパツタ蒸着し、４５
０℃の熱処理で、ソース・ドレイン上に白金シリサイド
（ＰｔＳｉ）(62)を形成した。その後、王水を用いて、
酸化膜、及び未反応のＰｔのみ除去した。その後、通常
の半導体製造工程に従い、パツシベーシヨン膜としてＰ
ＳＧ(60)を被着し、コンタクト穴加工、及びＡ電極配
線(61)を行なつて、第２図(f)の如きＭＯＳ−ＦＥＴを
製作した。Example 2 As shown in FIG. 2 (a), a p-type 10 Ω · cm Si substrate (51)
Due to the normal semiconductor manufacturing process above, 0.
A 6 μm thick thermal oxide film (52) was selectively formed, and a 20 nm thin thermal oxide film (53) was formed in the active region. After that, 0.3 μm of W (54) was deposited on the front surface by sputtering, and P
SG (phosphorus silicate glass) (55) is 0.1 μm by CVD method.
It was vapor-deposited. Thereafter, as shown in FIG. 2 (a), a gate electrode pattern was formed by a usual photo-etching method. At this time,
PSG was dry etched using CHF 3 gas. Also, W was dry-etched using SF 6 gas, but this etching is 10% of the etching time of 0.3 μm W.
As a result of overshooting, W is 0.1 μm on one side of PSG
Natsuta thin. By adjusting the overetch time, the thinness of W can be adjusted. Next, as shown in FIG. 2 (b), Si 3 N 4 (57) was formed on the entire surface by CVD to a thickness of 0.3 μm. Thereafter CH 2 F 2 gas with the Si 3 N 4 anisotropically Etsuchi, Si gate sidewall under the eaves of the PSG 3
N 4 (58) was left behind [Fig. 2 (c)]. Etching is
The etching time was 50% over 0.3 μm of Si 3 N 4 so that only Si 3 N 4 (58 ′) under the eaves of the PSG was left. At this time, the thin SiO 2 (3) on the source / drain was reduced only by about 5 nm, and Si was not directly bombarded with ions. Arsenic is then accelerated to 80k
Ions were implanted under the conditions of V and an implantation amount of 5 × 10 15 cm −3 to form a high concentration impurity layer (59) in the source / drain regions [FIG. 2 (d)]. Next, as shown in FIG. 2 (e), the thin SiO 2 (53) on the source / drain was removed by dry etching and heat treatment was performed to recover the damage. The condition at this time was N 2 annealing at 950 ° C. for 10 minutes.
After that, 100 nm Pt is sputter-deposited on the entire surface, and 45
By heat treatment at 0 ° C., platinum silicide (PtSi) (62) was formed on the source / drain. After that, using aqua regia,
Only the oxide film and unreacted Pt were removed. After that, according to a normal semiconductor manufacturing process, P is used as a passivation film.
By depositing SG (60), processing a contact hole, and performing A electrode wiring (61), a MOS-FET as shown in FIG. 2 (f) was manufactured.
本実施例によれば、ゲート上のＰＳＧの庇が、エツチン
グのストツパとなつてその下部のＳｉ３Ｎ４を残すた
め、0.1μｍ程度の薄いサイドウオールを確実に形成で
きた。また、オーバエツチも十分に行なえるので、ウエ
ハ面内ばらつきも小さく抑える事ができた。According to the present example, the eaves of PSG on the gate act as an etching stopper and leave Si 3 N 4 underneath it, so that a thin sidewall of about 0.1 μm could be reliably formed. Further, since overetching can be sufficiently performed, the variation within the wafer surface can be suppressed to be small.
こうして作つたＭＯＳ−ＦＥＴは、シート抵抗が３Ω／
ロ以下に抑えられ、また0.1μｍのオフセツトがあるた
め、実効ゲート長が1.0μｍと短い所で動作可能であ
り、高速化がはかれた。The MOS-FET thus made has a sheet resistance of 3Ω /
B) It can be operated at a place where the effective gate length is as short as 1.0 μm because it is suppressed to less than or equal to 0.1 μm and the offset is 0.1 μm.
実施例３ 第３図(a)に示すようにｐ型１０ΩcmのＳｉ基板１０１
上に通常の半導体製造工程により、素子分離領域には0.
6μｍの厚い熱酸化膜１０２を選択的に形成し、能動領
域には、非常に薄いＳｉＯ２（約２nm）１０３および５
０nmのＳｉ３Ｎ４１０４の２層絶縁膜を形成した。その
後、全面に多結晶Ｓｉを約0.3μｍの厚さに堆積させ、
通常の写真蝕刻法により所定の形状に加工した１０５。
この後多結晶Ｓｉのまわりに約１０nmのＳｉＯ２１０６
を形成し、この状態で、リンを加速電圧１００kV、打ち
込み量３×1013cm-2の条件でイオン打ち込みし、ソース
・ドレイン領域に低濃度のｎ型不純物層１０７を形成す
る。その後、第３図(b)に示すように、全面にＳｉ３Ｎ
４１０８をＣＶＤ法で0.3μｍの厚さに形成した。しか
るのち、ＣＨ２Ｆ２ガスを用いて、Ｓｉ３Ｎ４を異方性
エツチし、第３図(c)に示すように、ゲート側壁にＳｉ
３Ｎ４１０８を残存させた。エツチングは、基板上のＳ
ｉ３Ｎ４を完全に除去するため0.35μｍのＳｉ３Ｎ４を
エツチングする時間の１０％オーバーに行なつたが、こ
の時の多結晶ＳｉのまわりのＳｉＯ２１０６の膜厚減少
は約２nm、Ｓｉ基板上のＳｉＯ２１０３の膜厚減少は約
１nmにすぎず、多結晶ＳｉおよびＳｉ基板が直接イオン
衝撃されることがなく、損傷を受けることがなかつた。
第３図(d)に示すように、次にヒ素を加速電圧80kV、打
ち込み量５×1015cm-2の条件でイオン打ち込みし、ソー
ス・ドレイン領域の高濃度ｎ型不純物層１０９を形成し
た。その後、通常の半導体製造工程に従い、パツシベー
シヨン膜として、ＰＳＧ１１０を被着し、コンタクト穴
加工、およびＡ電極配線１１１を行なつて、ＬＤＤ構
造をもつＭＮＯＳ ＦＥＴを製作した。このようにして
製作されたＭＮＯＳ ＦＥＴは、前の実施例と同様な高
耐圧化が実現でき、高性能のメモリを実現できた。Example 3 As shown in FIG. 3 (a), a p-type 10 Ωcm Si substrate 101
Due to the normal semiconductor manufacturing process above, 0.
A 6 μm thick thermal oxide film 102 is selectively formed, and a very thin SiO 2 film (about 2 nm) 103 and 5 is formed in the active region.
A two-layer insulating film of 0 nm Si 3 N 4 104 was formed. After that, polycrystalline Si is deposited on the entire surface to a thickness of about 0.3 μm,
105 is processed into a predetermined shape by a usual photo-etching method.
After this, about 10 nm of SiO 2 106 is deposited around the polycrystalline Si.
Then, phosphorus is ion-implanted under the conditions of an accelerating voltage of 100 kV and an implantation amount of 3 × 10 13 cm -2 to form a low-concentration n-type impurity layer 107 in the source / drain regions. Then, as shown in FIG. 3 (b), Si 3 N is formed on the entire surface.
4 108 was formed to a thickness of 0.3 μm by the CVD method. After that, Si 3 N 4 is anisotropically etched using CH 2 F 2 gas, and Si is formed on the gate sidewall as shown in FIG. 3 (c).
3 N 4 108 was left. Etching is S on the board
i 3 N 4 but the has fallen completely rows 10% over the time of etching the 0.35μm the Si 3 N 4 for the removal, reduction in film thickness of the SiO 2 106 around the polycrystalline Si at that time was about 2nm The thickness reduction of SiO 2 103 on the Si substrate was only about 1 nm, and the polycrystalline Si and Si substrate were not directly bombarded with ions and were not damaged.
As shown in FIG. 3 (d), arsenic was then ion-implanted under the conditions of an acceleration voltage of 80 kV and an implantation amount of 5 × 10 15 cm -2 to form a high-concentration n-type impurity layer 109 in the source / drain regions. . Then, according to a normal semiconductor manufacturing process, PSG110 was deposited as a passivation film, contact holes were processed, and A electrode wiring 111 was performed to manufacture a MNOS FET having an LDD structure. The MNOS FET manufactured in this manner can realize a high breakdown voltage as in the previous embodiment and can realize a high-performance memory.
上記説明から明らかなように、本発明によれば、Ｓｉ３
Ｎ４をＳｉＯ２に対し高選択で異方性ドライエツチし
て、ゲートなどの導電体パターンの側部にＳｉ３Ｎ４を
残すことができるので、Ｓｉ基板を直接イオン衝撃する
ことがない。したがつて、ソース・ドレイン領域のＳｉ
基板が損傷を受けないので、それらの接合のリーク電流
を低減できる効果がある。また、特にＷなどの高融点金
属のチヤネリング防止膜としてＳｉＯ２やＰＳＧを用い
る場合には、それらの膜厚が減少することがないため、
チヤネリング防止に必要な最小限の膜厚にすることがで
き、ゲートの加工寸法の精度を向上できるという効果も
ある。As is clear from the above description, according to the present invention, Si 3
Since N 4 can be anisotropically dry-etched with high selectivity with respect to SiO 2 to leave Si 3 N 4 on the side portion of a conductor pattern such as a gate, the Si substrate is not directly bombarded with ions. Therefore, Si in the source / drain region
Since the substrate is not damaged, there is an effect that the leak current of those junctions can be reduced. Further, especially when SiO 2 or PSG is used as a channeling prevention film of a refractory metal such as W, the film thickness of those films does not decrease.
There is also an effect that the minimum film thickness necessary for preventing channeling can be obtained, and the accuracy of the processing size of the gate can be improved.
このような効果は、Ｓｉ３Ｎ４のドライエツチングを、
Ｃ，ＨおよびＦなる組成を有し、Ｆ対Ｈの比がほぼ２以
下のガスを反応ガスとして用いたために得られたもので
あり、ＣＨ３ＦおよびまたはＣＨ２Ｆ２を用いれば、と
くに好ましい結果が得られる。Such an effect is obtained by performing dry etching of Si 3 N 4 ,
It was obtained because a gas having a composition of C, H and F and an F to H ratio of about 2 or less was used as a reaction gas, and when CH 3 F and / or CH 2 F 2 was used, Good results are obtained.
第１図乃至第３図は、それぞれ本発明の異なる実施例を
説明するための工程図である。 １……Ｓｉ基板、２……ＳｉＯ２、３……ＳｉＯ２、４
……タングステン、５……ＰＳＧ膜、６……低濃度ｎ型
不純物層、７……Ｓｉ３Ｎ４、８……Ｓｉ３Ｎ４、９…
…高濃度ｎ型不純物層、１０……ＰＳＧ膜、１１……ア
ルミニウム。1 to 3 are process drawings for explaining different embodiments of the present invention. 1 ... Si substrate, 2 ... SiO 2 , 3 ... SiO 2 , 4
... Tungsten, 5 ... PSG film, 6 ... Low-concentration n-type impurity layer, 7 ... Si 3 N 4 , 8 ... Si 3 N 4 , 9 ...
... High-concentration n-type impurity layer, 10 ... PSG film, 11 ... Aluminum.
Claims (2)
程と、該ゲート酸化膜上に所望の形状を有し、上面にシ
リコンを含む酸化膜を有するゲート電極を形成する工程
と、該ゲート電極をマスクとしてソース及びドレイン用
の第１の不純物領域を該半導体基板表面に形成する工程
と、その後該半導体基板上に該ゲート酸化膜よりも厚い
シリコン窒化膜を形成する工程と、該シリコン窒化膜を
有する該半導体基板を、ＣＨ２Ｆ２ガスを反応ガスとし
て該ゲート電極の側壁に形成された該シリコン窒化膜、
該ゲート電極の上部に形成された該シリコンを含む酸化
膜及び該ゲート酸化膜を残し、他の領域に形成されたシ
リコン窒化膜をドライエッチングする工程と、該ゲート
電極と該ゲート電極の側壁に形成された該シリコン窒化
膜とをマスクとして該第１の不純物領域よりも高濃度の
第２の不純物領域を形成する工程とを有することを特徴
とする半導体装置の製造方法。1. A step of forming a gate oxide film on a semiconductor substrate, a step of forming a gate electrode having a desired shape on the gate oxide film and having an oxide film containing silicon on the upper surface, and the gate. Forming a first impurity region for source and drain on the surface of the semiconductor substrate by using the electrode as a mask; thereafter forming a silicon nitride film thicker than the gate oxide film on the semiconductor substrate; The semiconductor substrate having a film, the silicon nitride film formed on the side wall of the gate electrode using CH 2 F 2 gas as a reaction gas,
A step of dry-etching the silicon-containing oxide film formed on the gate electrode and the silicon oxide film formed in other regions, leaving the gate oxide film and the gate oxide film on the sidewalls of the gate electrode and the gate electrode; And a step of forming a second impurity region having a concentration higher than that of the first impurity region by using the formed silicon nitride film as a mask.
電極の側面にも形成されていることを特徴とする特許請
求の範囲第１項記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide film containing silicon is also formed on a side surface of the gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58222034A JPH0640543B2 (en) | 1983-11-28 | 1983-11-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58222034A JPH0640543B2 (en) | 1983-11-28 | 1983-11-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60115229A JPS60115229A (en) | 1985-06-21 |
| JPH0640543B2 true JPH0640543B2 (en) | 1994-05-25 |
Family
ID=16776044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58222034A Expired - Lifetime JPH0640543B2 (en) | 1983-11-28 | 1983-11-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0640543B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2753368B2 (en) * | 1990-03-16 | 1998-05-20 | 株式会社日立製作所 | Etching method |
| KR100403992B1 (en) * | 2001-04-18 | 2003-11-03 | 주성엔지니어링(주) | Manufacturing method of semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5846645A (en) * | 1981-09-14 | 1983-03-18 | Toshiba Corp | Manufacture of semiconductor device |
-
1983
- 1983-11-28 JP JP58222034A patent/JPH0640543B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60115229A (en) | 1985-06-21 |
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