JPH0611074B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, particularly a device using a refractory metal silicide for a gate electrode and wiring of a MOS transistor and its integrated circuit. .

[Conventional technology]

FIG. 2 is a cross-sectional view of a semiconductor substrate for explaining a conventional method for manufacturing a refractory metal silicide electrode and a wiring film in a MOS transistor. In Figure 2 (a),
Reference numeral 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, and 4 is polycrystalline silicon. After patterning as shown in FIG. 2 (a), second conductivity type impurities are ion-implanted, and heat treatment for annealing the ion-implanted layer is further performed to form the source / drain impurity layers 5a, 5b.
Are formed (FIG. 2 (b)). Next, as shown in FIG. 2 (c), a silicon oxide film 6 is formed by the CVD method or the like. Thereafter, the entire surface is etched by the reactive ion etching method to form the side wall of the silicon oxide film as shown in FIG. 2 (d). And Fig. 2 (e)
As shown in, the titanium film 7 is formed by a sputtering method, a vapor deposition method, a CVD method, or the like. This is annealed at a temperature of about 600 ° C., and as shown in FIG. 2 (f), only the contact portion between titanium and silicon is reacted to form a titanium silicide film 8. Next, H ₂ O: H ₂ O ₂ : NH ₄ OH = 5:
The unreacted titanium 7 is selectively removed by using a 1: 1 solution as an etching solution, as shown in FIG. 2 (g). After this,
Annealing is performed at 800 ° C. to reduce the sheet resistance of the titanium silicide film 8.

In FIG. 3, arsenic-implanted P-type silicon substrate (surface impurity concentration 8 × 10 ²⁰ / cm ³ : broken line in the figure) and not implanted (surface impurity concentration 1 × 10 ¹⁵ / cm ³ : Titanium film is formed on the solid line in the figure) by the sputtering method.
The backscattering spectrum at the time of silicidation at 50 degreeC is shown. From this figure, when the underlying silicon substrate has a high-concentration impurity layer, that is, what is indicated by the broken line in the figure, the silicon does not spread in the surface direction (right side in the figure) and the silicide reaction is suppressed. I understand. The same applies to phosphorus and the like. From this, it is understood that the silicide reaction strongly depends on the surface impurity concentration of the underlying silicon.

[Problems to be solved by the invention]

By the way, the polycrystalline silicon 4 is usually implanted with impurities such as phosphorus at a high concentration (surface impurity concentration 8 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / cm ³ ) for stabilization of the threshold voltage. . On the other hand, the surface impurity concentration of the source / drain impurity layers 5a and 5b is about 1 to 2 × 10 ²⁰ / cm ³ . As described above, since the surface impurity concentrations of the polycrystalline silicon and the silicon substrate are different by about 5 to 10 times, the film thickness of the obtained silicide is smaller on the polycrystalline silicon than on the silicon substrate, as described above. As a result, there is a problem that the titanium silicide film on polycrystalline silicon has a higher resistance.

The present invention has been made in order to solve the above problems, and provides a method for manufacturing a semiconductor device in which the resistance of silicide on polycrystalline silicon and the resistance of silicide on a silicon substrate can be reduced to substantially the same level. Is intended.

[Means for solving problems]

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a gate electrode made of polysilicon into which impurity ions are introduced on a silicon substrate, and ion implantation so that the impurity concentration of the gate electrode is approximately equal to that of the gate electrode. Ion implantation into the entire surface and heat treatment to form source / drain regions, a step of forming a silicon oxide film on the entire surface and etching to form sidewalls on the gate electrode, and after forming a refractory metal layer on the entire surface A step of forming a refractory metal silicide film by heat treatment and a step of performing heat treatment by removing the unreacted refractory metal layer by etching are provided.

[Action]

In the present invention, since the surface impurity concentrations of the polycrystalline silicon and the silicon substrate are substantially equal, the silicide reaction rates are also equal, and the silicides obtained on the polycrystalline silicon and the silicon substrate are approximately equal and have low resistance. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
In FIG. 1A, 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, and 4 is polycrystalline silicon.
However, the concentration of surface impurities such as phosphorus for stabilizing the threshold voltage of the polycrystalline silicon 4 is set to about 1 × 10 ²⁰ / cm ³ . Next, impurities of the second conductivity type are ion-implanted, and further heat treatment for annealing the ion-implanted layer is performed to form the source and drain impurity layers 5a and 5b having a surface impurity luminance of about 1 × 10 ²⁰ / cm ^3. It is formed (Fig. 1 (b)). At this time, since ions are also implanted into the polycrystalline silicon 4,
The surface impurity concentration of the polycrystalline silicon 4 is 2 × 10 ²⁰ / cm
It becomes ³ . Thereafter, as shown in FIG. 1 (c), a silicon oxide film 6 is formed by the CVD method or the like. Next, the entire surface is etched by the reactive ion etching method to form the side wall of the silicon oxide film as shown in FIG. 1 (d). Then, as shown in FIG. 1 (e), the titanium layer 7 is formed by sputtering, vapor deposition, CVD, or the like.
To form. Anneal this at a temperature of about 600 ℃,
As shown in FIG. 1 (f), the titanium silicide film 8 is formed by reacting only the contact portion between titanium and silicon. At this time, the surface impurity concentration of the polycrystalline silicon 4 is 2 × 10 ^20.
/ Cm ³ , and the surface and impurity concentration of the source and drain impurity layers 5 a and 5 b is 1 × 10 ²⁰ / cm ^3, which are almost equal to each other, the titanium silicide film 8 thus formed has almost the same thickness. Will be equal. Next, H ₂ O: H ₂ O ₂ : N
A solution of H ₄ OH = 5: 1: 1 is used as an etching solution to selectively remove only the unreacted titanium 7 as shown in FIG. 1 (g). Then, annealing is performed at 800 ° C. to reduce the sheet resistance of the titanium silicide film 8.

In this embodiment, since the surface impurity concentrations of the polycrystalline silicon and the silicon substrate are made substantially equal, the thickness of the titanium silicide film 8 obtained is almost the same on the polycrystalline silicon and the silicon substrate. It has a low resistance to the same extent.

In the above embodiment, the surface impurity concentration is 1 × 2 × 10 ^20.
/ Cm ³ , but the difference in surface impurity concentration between polycrystalline silicon and silicon substrate is within 3 times, or both are 1
It is sufficient if it is not more than × 10 ²⁰ / cm ³ , and the same effect as that of the above-mentioned embodiment can be obtained.

Further, in the above embodiment, the case where titanium is used as the refractory metal has been described, but any of tantalum, tungsten and molybdenum may be used.

〔The invention's effect〕

As described above, according to the method of manufacturing a semiconductor device of the present invention, the step of forming a gate electrode made of polysilicon into which impurity ions have been introduced on a silicon substrate, and a concentration substantially equal to the impurity concentration of the gate electrode. Ion implantation is carried out on the entire surface with an ion implantation amount so that after heat treatment,
Forming a drain region, forming a sidewall on the gate electrode by etching after forming a silicon oxide film on the entire surface, forming a refractory metal layer on the entire surface, and forming a refractory metal silicide film by heat treatment Since the unreacted refractory metal layer is removed by etching and the step of performing heat treatment is provided, there is an effect that the sheet resistance of the formed silicide film can be reduced to almost the same level.

[Brief description of drawings]

1 (a) to 1 (g) show a MOS according to an embodiment of the present invention.
For explaining a method of manufacturing a refractory metal silicide electrode / wiring film in a p-type transistor, FIG. 2 (a) to FIG.
(g) is a diagram for explaining the conventional manufacturing method, and FIG. 3 is a backscattering spectrum diagram for explaining that the silicide reaction rate varies depending on the surface impurity concentration difference of the underlying silicon. 1 ... Silicon substrate, 4 ... Polycrystalline silicon, 5a, 5
b ... second conductivity type impurity layer, 7 ... titanium film, 8 ...
Titanium silicide film. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (5)

[Claims] 1. A step of forming a gate electrode made of polysilicon into which impurity ions have been introduced on a silicon substrate, and ion-implanting the entire surface with an ion implantation amount so as to have a concentration substantially equal to the impurity concentration of the gate electrode. , A step of forming a source / drain region after heat treatment, a step of forming a side wall on the gate electrode by etching after forming a silicon oxide film on the entire surface, and a step of forming a refractory metal layer over the entire surface and then performing a heat treatment on the refractory metal silicide film And a step of removing the unreacted refractory metal layer by etching and performing a heat treatment. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the surface impurity concentration of the polycrystalline silicon electrode / wiring and the silicon substrate is 1 × 10 ²⁰ / cm ³ or less. 3. A patent characterized in that the surface impurity concentration of the polycrystalline silicon electrode / wiring and the silicon substrate is 1 × 10 ²⁰ × cm ³ or more, and one surface impurity concentration is within 3 times of the other. A method of manufacturing a semiconductor device according to claim 1. 4. The method of manufacturing a semiconductor device according to claim 1, wherein arsenic, phosphorus, antimony or a mixture thereof is used as the impurity. 5. The method of manufacturing a semiconductor device according to claim 1, wherein titanium, tantalum, tungsten, or molybdenum is used as the refractory metal.