JPH0637647A - Error correcting and decoding device - Google Patents

Abstract

PURPOSE:To decrease the number of the exclusive logical sum circuits of a multiplying circuit, and to attain a high speed operation by letting a constant on a Galois body be alpha<j>-fold by which the coefficient of an error numeric value polynomical is multiplied, and properly selecting the value of (j). CONSTITUTION:The constants for multiplication at a first multiplying means 7 are changed from alpha<0>, alpha<-1>, alpha<-2>,..., alpha<-1+1> to alpha<j>, alpha<j-1>, alpha<j-2>..., alphaj<->t<+1>, and the value of (j) is selected so that the circuit scale of the means 7 can be the minimum. At that time, the entire constants for multiplication at a second arithmetic means 8 are also multiplied by alpha<j>, so that the same result can be obtained by a division at the arithmetic means 12, and the circuit scale can be reduced. And also, the number of circuits of the means 7 and 8 can be decreased, and the high speed operation can be attained. And also, the constants for multiplication at the means 8 are changed to alpha<i>, alpha<i-2>, alphai-4,..., alphai<-2>s<+2>, and the value of (i) is selected so that the circuit scale of the means 8 can be the minimum, so that the circuit scale can be reduced, and a decoding delay can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction decoding device using a Reed-Solomon code, and more particularly to an error numerical value calculation circuit and an error position calculation circuit.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing the structure of a commonly used error correction decoding apparatus. In the figure, 51 is an input terminal, 52 is a buffer memory, 53 is a syndrome calculation circuit, and 54 is a position polynomial / numerical polynomial calculation circuit. , 55 is a Chien search circuit, 56 is an error numerical value calculation circuit, 57 is an error correction circuit, and 58 is an output terminal. Received signals Y ₀ , Y ₁ , ... Y _n-1 are input from the input terminal 51, and the syndrome calculation circuit 53 calculates the syndrome from the received signal. The syndrome is supplied to the position polynomial / numerical polynomial calculation circuit 54, and the coefficients of the error position polynomial and the error number polynomial are calculated. The Chien search circuit 55 finds the root of the error locator polynomial and derives the error location. The error numerical value calculation circuit 56 obtains the error magnitude at the error position from the error locator polynomial and the coefficient of the error value polynomial. The error correction circuit 57 receives the received signal from the buffer memory 52, corrects the error having the magnitude calculated by the error numerical value calculation circuit 56 generated at the error position determined by the Chien search circuit 55, and outputs the decoding result to the output terminal 58. Output from.

FIG. 4 is a block diagram showing an example of a conventional error numerical value calculation circuit 56. In the following, the generator polynomial in Reed-Solomon code with t symbol error correction is

[0004]

[Equation 3]

The code of will be described. Note that s (used in the later section) for t is s = [(t + 1) / 2]. However, [] is a Gaussian symbol, and a real number (t + 1) / 2
Means that the integer part of is s. In FIG.
101-1 to 101-t are first input terminals, 102-1
102-s are second input terminals, 103 is a third input terminal, 104-1 to 104-t are first storage means, 105
-1 to 105-s is the second storage means, 106 is the third storage means, 107-1 to 107-t is the first multiplication means, 1
08-1 to 108 s are second multiplication means, 109 is a third multiplication means, 110 is a first addition means, 111 is a second addition means, and 112 is an operation means for calculating an error value,
Reference numeral 113 is an output terminal.

In the position polynomial / numerical polynomial calculation circuit 54, the coefficients of the error numerical polynomial of t symbols calculated by the Euclidean algorithm or the Berlekamp algorithm are respectively input to the first input terminals 101-1 to 101-1 in descending order. It is input from -t and stored in the first storage means 104-1 to 104-t, respectively.
The odd-order coefficients of the error position polynomial of (t + 1) symbols are input from the second input terminals 102-1 to 102-s in order from the lowest order, and the second order
The storage means 105-1 to 105s are stored. Further, the constant α ^1-m on the Galois field is input from the third input terminal 103 and stored in the third storage means 106.

First multiplication means 107-1 to 107-t
Are constants α ⁰ , α ^-1 , α ^-2 , ... on the Galois field, respectively.
This is a multiplication circuit for multiplying α ^{− (t−1)} by the second multiplication means 1
08-1 to 108-s are constants α on the Galois field, respectively.
^.. .alpha..sup.- ² , .alpha..sup.- ⁴ , ... .alpha..sup .- ^(s-2) are multiplication circuits, and the third multiplication means 106 is a multiplication circuit which multiplies a constant .alpha. On the Galois field. The contents of the first, second, and third storage means are multiplied by the first, second, and third multiplication means at each clock, and the multiplication results are stored in the original storage means. The contents of the storage means change every clock. First storage means 104-1 to 104-t
The contents stored in are added by the first addition means 110 and input to the arithmetic means 112 on the Galois field. The contents stored in the second storage units 105-1 to 105-s are added by the second addition unit 111 and input to the calculation unit 112. The contents stored in the third storage unit 106 are directly input to the calculation unit 112.

In the calculation means 112, the first addition means 11
A multiplication operation on the Galois field is performed on the output of 0 and the output of the third storage unit 106, the output of the second addition unit 111 is divided by the result of the multiplication operation, and the result of the division is output terminal 113. Output to.

[0009]

The error numerical value calculation circuit in the conventional error correction decoding apparatus is configured as described above, and the constant multiplied by the first multiplication means is α ⁰ ,
It is fixed to α ^-1 , α ^-2 , ... And the constants for multiplication by the second multiplication means are fixed to α ⁰ , α ^-2 , α ^-4 , ... It was not possible to select a constant to be multiplied so that the circuit that constitutes the multiplication is as simple as possible. Therefore, the number of stages of the two-input one-output exclusive OR circuit constituting the constant multiplication means on the Galois field becomes large, and the operation is delayed, so that it cannot operate with a high-speed clock. Further, since the arithmetic means 112 performs the arithmetic operation twice, that is, the multiplication operation and the division operation on the Galois field, the circuit scale becomes large and the decoding delay becomes large. Further, in the calculation by the Euclidean algorithm, the dividend polynomial is A
(X), where B (x) is the divisor polynomial, A (x) ÷ B
(X) = Q ₀ (x) Remainder R ₀ (x) ... (1) is calculated. If R ₀ (x) = 0, it is determined that there is no error, and R ₀
If (x) is not 0, the remainder and divisor are exchanged and B
(X) ÷ R ₀ (x) = Q ₁ remainder R ₁ (x) (2)
Is performed, and such a computation is repeated to perform so-called Euclidean mutual division computation. However, since this computation is conventionally performed by software, there is a problem that the processing time becomes long.

The present invention has been made to solve the above problems, and can reduce the circuit scale of the multiplication means in the error numerical calculation circuit, reduce the number of stages of the exclusive OR circuit, and further reduce the Euclidean circuit. An object of the present invention is to provide an error correction decoding device in which the number of times a multiplication operation is performed is reduced by improving the operation speed by an algorithm to enable a high speed operation and sharing the means for performing a chain search operation.

[0011]

An error correction decoding device according to the present invention has first storage means for storing coefficients of error numerical polynomials as initial values and contents stored in the first storage means. On the other hand, the constants α ^j , α ^j-1 , α ^j-2 , α ^j-3 , ^...
The first multiplication means for multiplying .., and means for predetermining the value of j so that the number of two-input one-output exclusive-OR circuits forming the first multiplication means is minimized, And means for storing the multiplication result of the first multiplication means in the first storage means.

Further, second storage means for storing odd-order coefficients of the error locator polynomial as initial values, and odd-order coefficients of the error locator polynomial with respect to the contents stored in the second storage means. The constants α ⁱ , α on the Galois field in ascending order
The second multiplication means for multiplying ^i-2 , α ^i-4 , α ^i-6 , ... And the minimum number of two-input one-output exclusive OR circuits constituting the second multiplication means And a means for storing the multiplication result of the second multiplication means in the second storage means.

Further, when the generator polynomial is expressed by a constant expression, the coefficient of the error numerical polynomial is stored as an initial value.
Storage means, a second storage means for storing odd-order coefficients of the error locator polynomial as initial values, and a Galois order in which the order of the error value polynomial is low with respect to the contents stored in the first storage means. Constants on the body α ^j , α ^j-1 , α ^j-2 , α
First multiplication means for multiplying ^j-3 , ..., Means for storing the multiplication result of the first multiplication means in the first storage means, and means for calculating k by k = j + m-1 And the constants α ^k , α ^k-2 , α ^k-4 , α ^k-6 on the Galois field in ascending order of odd order of the error locator polynomial with respect to the contents stored in the second storage means. , And so on, and a means for storing the multiplication result of the second multiplication means in the second storage means.

Further, when the generator polynomial is expressed by a constant expression, the coefficient of the error numerical polynomial is stored as an initial value.
Memory means, second memory means for storing odd-order coefficients of the error locator polynomial as initial values, and odd-order coefficients of the error locator polynomial with respect to the contents stored in the second memory means. Constants on Galois field in ascending order α ⁱ , α ^i-2 , α
Second multiplication means for multiplying ^i-4 , α ^i-6 , ..., Means for storing the multiplication result of the second multiplication means in the second storage means, and k = i + m-1 a means for calculating k and constants α ^k , α ^k-1 , α ^k-2 , α ^k on the Galois field in order of increasing order of the error numerical polynomial with respect to the contents stored in the first storage means. ^-3 , ... Multiplying the first multiplication means, and means for storing the multiplication result of the first multiplication means in the first storage means.

Further, the second storage means and the second multiplication means are shared by the storage means and the multiplication means of the Chien search circuit.

The present invention also provides an arithmetic unit suitable for Euclidean mutual arithmetic. This arithmetic unit is provided with an order difference counter that counts the order difference between the divisor polynomial and the dividend polynomial when performing division of the polynomial, and by changing the value input to the storage means by the value of the order difference counter, The outputs of the storage unit for storing the coefficient and the storage unit for storing the coefficient of the dividend polynomial are not exchanged and are always constant.

Further, the error position calculating means is provided with a product-sum calculating means on the Galois field having the same configuration as the product-sum calculating means for performing multiplication and addition on the Galois field in the Euclidean algorithm calculating means.

Further, a storage means for storing an element of the erasure position on the Galois field is provided, and a Euclidean algorithm operation means and an error locator polynomial calculation means capable of calculating the erasure position polynomial and the modified syndrome polynomial are provided.

[0019]

In the present invention, the constants to be multiplied by the first multiplication means are α ⁰ , α ^-1 , α ^-2 , ..., α
^{The value of j is changed} from ^{-t + 1} to α ^j , α ^j-1 , α ^j-2 , ..., α ^{j-t + 1} so that the circuit scale in the first multiplication means becomes the smallest. Is selected. In this case, if all the constants to be multiplied in the second multiplication means are also multiplied by α ^j , the same result can be obtained by the division in the calculation means,
The circuit scale can be reduced, and the number of circuit stages of the multiplication means can be reduced to enable high speed operation.

Further, the constants to be multiplied in the second multiplication means are changed to α ⁱ , α ^i-2 , α ^i-4 , ..., α ^{i-2s + 2} , and the circuit in the second multiplication means is changed. By selecting the value of i so that the scale becomes the smallest, the circuit scale is reduced and the decoding delay is also reduced.

Further, by appropriately selecting the constant to be multiplied in the first multiplying means and the constant to be multiplied in the second multiplying means, the multiplying operation in the calculating means becomes unnecessary.

Further, the circuit scale is reduced by sharing the second storage means and the second multiplication means with the storage means and the multiplication means of the Chien search circuit.

Further, the Euclidean mutual division computing device according to the present invention stores the degree difference between the divisor polynomial and the dividend polynomial in the counter when performing the division of the polynomial, and saves the dividend polynomial except when the counter value is 0. When the counter value is 0, the storage means storing the coefficient is rewritten with the coefficient of the remainder polynomial, and when the counter value is 0, the storage means storing the coefficient of the divisor polynomial is rewritten with the coefficient of the remainder polynomial. By doing so, the storage means for storing the coefficient of the error number polynomial is always fixed.

In the error locator polynomial calculation means,
By providing the product-sum calculation means having the same configuration as the product-sum calculation means in the Euclidean algorithm calculation means, the Euclidean algorithm calculation means and the error locator polynomial calculation means are operated at the same time, and the error locator polynomial and the error value polynomial are calculated at the same time. This enables high-speed error correction decoding.

Further, by inputting the contents of the storage means for storing the disappearance position as an element on the Galois field to the Euclidean algorithm operation means, the correction syndrome can be calculated, and the contents of the storage means for storing the disappearance position are stored. Since the erasure locator polynomial can be calculated by inputting it to the error locator polynomial calculation means, both the error and the erasure can be corrected by performing a normal operation for obtaining the error locator polynomial and the error value polynomial.

[0026]

EXAMPLES Example 1. Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a first embodiment of the present invention. In the figure, 1-1 to 1-t are first input terminals, 2-1 to 2-s are second input terminals, and 3 is Third
Input terminals 4-1 to 4-t are first storage means 5-1.
~ 5-s is the second storage means, 6 is the third storage means, 7-
1 to 7-t are first multiplying means, 8-1 to 8-s are second multiplying means, 9 is third multiplying means, 10 is first adding means, 11 is second adding means, Reference numeral 12 is a calculation means, and 13 is an output terminal. Portions in FIG. 1 having the same names as those in FIG. 4 have the same configuration and operate in the same manner, so duplicated description will be omitted. The difference between FIG. 1 and FIG. 4 is that the first multiplication means 7-1 to 7-t and the second multiplication means 8-1 to 8-
The constants to be multiplied in s are α ^j and α, respectively.
^j-1 , α ^j-2 , ..., α ^{j-t + 1} , and α ^j , α
^The only difference is that it is changed to ^j-2 , α ^j-4 , ..., α ^{j-2s + 2} . The value of j is determined so that the exclusive OR circuit that constitutes the first multiplication means is minimized. This decision can easily be made by trial and error. For example,

[0027]

[Equation 4]

In t = 8 and m = 0, the primitive polynomial p (x) is p (x) = x ⁸ + x ⁴ + x ³ + x ² +1
Therefore, assuming that α is the root of the primitive polynomial, the total number of the two-input one-output exclusive-OR circuits constituting the first multiplication means 107-1 to 107t is 89 in the case of the configuration of FIG. The total number of the two-input one-output exclusive OR circuits constituting the multiplication units 108-1 to 108-s is 38, but if j = 4 in FIG. 1, the first multiplication units 7-1 to 7-1. 7
The total number of exclusive OR circuits forming −t is 49, and the total number of exclusive OR circuits forming the second multiplication circuits 8-1 to 8-s is 24. The output of the first adding means 10 is (α ^j ) ^{q to} the output of the first adding means 110.
(Q is the number of repetitions of multiplication) multiplied by
Since the output of the adding means 11 is obtained by multiplying the output of the second adding means 111 by (α ^j ) ^q , the division result in the calculating means 12 is the same.

Example 2. Second multiplication means 8-1 to 8-s
As most smaller total number of exclusive OR circuit forming the constant over a Galois field ^{multiplying, α i, α i-2} ,
The value of i in α ^i-4 , ... α ^{i-2s + 2} may be determined. In this case, the constants multiplied by the first multiplication means 7-1 to 7-t are α ⁱ , α ^i-1 , α ^i-2 , ... α ^{i-t + 1} .

Example 3. 2 is a block diagram showing a third embodiment of the present invention, in which the same reference numerals as those in FIG. 1 denote the same or corresponding parts, 14-1 to 14-s are second multiplication means, and 15 is division on a Galois field. It is a means. Second multiplication means 14-1
.About.14-s, constants to be multiplied by α ^k , α ^k-2 ,
Let α ^k-4 , ... α ^{k-2s + 2,} and k = j + between j and k
If the relationship of m-1 is maintained, it can be proved that the multiplication by the contents of the third memory circuit 6 in FIG. 1 may be omitted.

Example 4. In the invention shown in FIG. 2, the value of j is first determined and k is determined by k = j + m−1 so as to reduce the number of exclusive OR circuits forming the first multiplication means. In order to reduce the number of exclusive OR circuits forming the multiplication unit of 2, i is first determined and k = i
From + m-1 to k, α ^k , α ^k-1 , α ^k-2 , ...
It is also possible to use α ^{k-t + 1} as a constant for multiplication in the first multiplication means.

Example 5. FIG. 3 is a block diagram showing a fifth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 2 designate the same or corresponding parts, and 16-1 to 16-r are fourth input terminals, 17-1 to 17. -R is the fourth storage means, 18-1
18-r is a fourth multiplication means, 19 is a third addition means,
Reference numeral 20 is a fourth adding means, and 21 is an output terminal. Here, r represents [(t + 2) / 2].

Of the coefficients of the error locator polynomial of (t + 1) symbols, even-order coefficient r symbols are input from the fourth input terminals 16-1 to 16-r in order from the lowest order, and the It is stored in the storage means 17-1 to 17-r. The contents stored in the fourth storage means 17-1 to 17-r are synchronized with the clock and the fourth multiplication means 18-1.
.About.18-r respectively α ^{k + 1} , α ^k-1 , α ^k-3 ,
.... multiplying by .alpha..sub.k ^{-2r + 3} , and fourth multiplying means 18-1
To 18-r are output to the fourth storage means 17-1.
~ 17-r. Fourth storage means 17-1 to 17-1
The contents stored in 7-r are added by the third adding means 19, and the output of the third adding means 19 is added by the output of the second adding means 11 and the fourth adding means 20.
That is, the second storage means 5 and the second multiplication means 14 of the circuit of FIG. 3 are shared by the error numerical value calculation circuit 56 and the Chien search circuit 55.

According to the theory of the Chien search operation, the output of the output terminal 21 being 0 means that an error has been detected, and the output of the output terminal 13 at that time represents an error value.

Example 6. As a prior art showing hardware suitable for Euclidean algorithm operation, there is an Euclidean algorithm operation apparatus disclosed in JP-A-3-172027, "Error correction processing apparatus". Figure 6
FIG. 1 is a block diagram showing this prior art, in which 601-1 to 601-n and 602-1 to 602 are shown.
-(N + 1) is a storage unit for storing a residue polynomial (also a dividend polynomial) and a coefficient of the divisor polynomial, 603
Is a multiplication means on the Galois field, 604 is a division means on the Galois field, 605 is an addition means on the Galois field, 606 and 607 are the contents of the storage means 601-1 to 601-n and the storage means 60.
2-1 to 602- (n + 1) contents are exchanged with each other, and exchange means composed of a selector circuit, 608 and 609 issue commands to the exchange means 606 and 607 to select the output of the storage means, and further, the Euclidean algorithm. The operation command means including a counter circuit that manages the remainder order for determining the end of the, and the signal lines 610 and 611 are storage means 601-1 to 601-n and storage means 602, respectively.
It is a timing clock signal line when the shift operation of −1 to 602- (n + 1) is performed.

Next, the operation of the apparatus shown in FIG. 6 will be described. In the following, the syndrome is S _i (i = 0, 1, ...
.., 15) and the design distance is 17, the decoding operation of the Reed-Solomon code will be described. Here, when the content of the counter 608 that stores the degree of the remainder polynomial becomes 7 or less, the operation is aborted midway, and the Euclidean algorithm arithmetic operation is ended. First, the coefficients of the dividend polynomial are set in the storage means 601-1 to 601-n in order of the order such that the highest-order coefficient is stored in the storage means 601-n. Further, the coefficients of the divisor polynomial are set in the storage units 602-1 to 602- (n + 1) in order of the order so that the highest-order coefficient S ₁₅ is stored in the storage unit 602- (n + 1). In addition, the degree 15 of the divisor polynomial is set in the counter 608, and 0 is set in the counter 609.

When the content stored in the storage means 602- (n + 1) is 0, the storage means 602- (n + 1)
Storage means 602-1 to 60 until the contents of
Shift the contents stored in 2- (n + 1) to the right,
The operation of counting down the content of the counter 608 and counting up the content of the counter 609 is repeated.

When the content stored in the storage means 602- (n + 1) is not 0, the selector 606 selects the content of the storage means storing the coefficient of the dividend polynomial,
The selector 607 selects the contents of the storage means that stores the coefficient of the divisor polynomial. When the coefficients of the dividend polynomial are stored in the storage means 601-1 to 601-n, the storage means 602-1 to 602- (n +) are stored in the signal line 610.
When stored in 1), the clock signal (value of the counter 609 + 2) is given to the signal line 611. Then, the value of the counter 608 is decremented by 1, and the value of the counter 609 is set to 0. As a result, the coefficient of the remainder polynomial is stored in the storage unit that stores the coefficient of the dividend polynomial.

When the next division operation is performed, the division polynomial in the previous division operation becomes the dividend polynomial and the remainder polynomial becomes the division polynomial, and the same arithmetic operation as above is performed. The remainder polynomial at the end of the Euclidean algorithm calculation operation becomes the error numerical polynomial.

However, in the error correction decoding device shown in FIG. 6, the processing time can be shortened as compared with the case of the conventional software, but depending on the number of times the storage means storing the coefficient of the error numerical polynomial performs the polynomial division, Storage means 601-1 to 601-n or storage means 602-1 to 602-1
Since it is uncertain which is 602- (n + 1), it is necessary to switch the selector and read it to the storage means for performing the Chien search and perform the Chien search operation according to the number of times the polynomial division is performed. Therefore, a device that controls the selector depending on the number of times the polynomial is divided is required. Further, since the error correction decoding device of FIG. 6 does not have the function of correcting the erasure error, the erasure correction cannot be performed and the error correction capability is not improved.

Sixth Embodiment The invention described in the sixth and subsequent embodiments is an error correction decoding device which always keeps the storage means of the divisor polynomial and the dividend polynomial constant and can always read the value from one of the storage means when performing the Chien search. For the purpose of obtaining the erasure position and having a storage means for storing the erasure position, by inputting the contents of the erasure position storage means to the Euclidean algorithm computing means and the error locator polynomial calculating means, both the error and the erasure are stored. The present invention relates to an error correction decoding device that enables correction.

An embodiment of the Euclidean mutual division apparatus of the present invention will be described below with reference to the drawings. An error correction decoding device for a Reed-Solomon code having a design distance of d will be described below. In FIG. 7, 61-1 to 61- (d-1)
Is a storage means for storing the coefficient of the divisor polynomial, which is tentatively called the first storage means, and stores the coefficient in the descending order of the dividend polynomial in the order of the coefficient storage means 61- (d-1), 61- ( d
2), ..., 61-1 are stored in this order. Also, 6
Reference numerals 2-1 to 62- (d-1) are storage means for storing the coefficients of the divisor polynomial, which is tentatively referred to as second storage means, and the coefficients are stored in the memory means 62 in descending order of the divisor polynomial. −
(D-1), 62- (d-2), ..., 62-1 are stored in this order.

63 is a multiplication means on the Galois field composed of an AND gate and an EXOR gate, and 64 is a ROM and A
Division means on the Galois field composed of an ND gate and EXOR gate, 65 is addition means on the Galois field composed of EXOR gates, 66 and 67 are storage means 61-1 to 61- (d- 1) and 62-
1-62- (d-1) is a selector circuit for switching the input, and the switching of the selector circuit is performed at the same time as the switching of the calculation procedure. Here, the selector circuit 66 is temporarily called a first selector circuit, and the selector circuit 67 is temporarily called a second selector circuit. 68 is a residue order counter that stores the order of the remainder polynomial and determines the end of the Euclidean algorithm operation; 69 is a order difference counter for counting the difference between the orders of the divisor polynomial and the dividend polynomial; It determines whether or not the value of the means 62- (d-1) is 0, and generates signals for controlling the selectors 66 and 67 and the operations of the counters 68 and 69. Reference numeral 71 surrounded by a dotted line is a Euclidean algorithm calculation unit that performs a calculation operation in the Euclidean algorithm.

FIG. 8 is a block diagram showing a first multiply-accumulate operation cell which constitutes the Euclidean algorithm 71 shown in FIG. 7. In the figure, input / output signals A _i , B _i , A are shown.
_{i + 1} and B _{i + 1} are connected to another product-sum operation cell,
The value calculated by the dividing means 64 is input from the input signal line R. That is, the Euclidean algorithm operation unit 7
Reference numeral 1 is composed of a cascaded product-sum calculation means in which the first product-sum calculation cells are cascaded and a division means 4.

Next, the operation will be described. In the following, the read distance for designating the 8-symbol error when the design distance is d = 17
The Solomon code will be described. At that time, the storage means 61-1 to 61- (d-1), 62-1 to 62-1 shown in FIG.
Each of (d-1) has 16 stages. First, initial setting is performed. Storage means 61-1 to 61- (d-
For 2), 0 is input and the storage means 61- (d-1)
Enter 1 for. On the other hand, the syndrome S _i (i = 0, 1, ..., 15) generated by the received word is converted into S ₀ ,
Storage means 62-1, 62-2, ... In the order of S ₁ , ...
Input to 62- (d-1). At the time of this input, the output of the selector circuit 66 shown in FIG. 8 is blocked, and the contents of the storage means 62-i are the selector circuit 67 and the addition means 65.
It is controlled so as to be output to Bi + 1 which is the input of the next stage through the above, and B ₁ to S ₁₅ , S ₁₄ , ... S ₁ , S ₀ are input in this order. Further, d-2 = 15 is set in the remainder order counter 68 shown in FIG. 7, and 1 is set in the order difference counter 69.
Set.

Next, in the dividing means 64, the storage means 6
From the contents stored in 1- (d-1), the storage means 62-
The contents stored in (d-1) are divided in the Galois field, and the value is held temporarily. Further, the determining means 70 determines whether or not the content of the storage means 62- (d-1) is 0.

When the content of the storage means 62- (d-1) is 0, the determining means 70 outputs an instruction signal for decrementing the content of the remainder order counter 68 by 1 and incrementing the content of the order difference counter 69 by 1. To be done. Further, the determination means 70 outputs the selection signal of the selector 67, and the selector 67 selects the contents of the storage means 62-1 to 62- (d-2). Then, in the multiplication means 63, the value 0 calculated and held in the division means 64 and the storage means 62-1 to 62-
The contents of (d-2) are multiplied, and the addition means 65 performs an exclusive OR operation for adding the result of the multiplication means 63 and the output of the selector 67. Then, the outputs of the addition means 65 are stored in the storage means 62-2 to 62- (d-1), respectively. That is, the storage means 62-1 to 62- (d-
This means that the shift operation was performed for the contents of 1). The contents of the order difference counter 9 are amplified by 1 for each shift. Note that 0 is stored in the storage unit 62-1. Further, with respect to the storage means 61-1 to 61- (d-1), the input is blocked by the selector circuit 66 and the stored value is held as it is.

When the content of the storage means 62- (d-1) is not 0, it is 0 when the value of the order difference counter 69 is not 0.
The operation differs depending on the case, and the following operation is performed for each case. That is, the order difference counter 6
When the content of 9 is not 0, the determining means 70 outputs an instruction signal for decreasing the content of the order difference counter 69 by 1. Further, the determination means 70 and the order difference counter 69
Selection signals of the selector 66 and the selector 67 are output from the selector 67, and the selector 67 stores the storage means 61-1 to 61- (d.
The content of -2) is selected. Then, the multiplication means 63 multiplies the value calculated and held by the division means 64 and the contents of the storage means 62-1 to 62- (d-2), and the addition means 65 multiplies the result of the multiplication means 63 and the selector 67. Perform an exclusive OR operation that adds the output together. And
The output of the addition means 65 is selected by the selector 66 and stored in the storage means 61-2 to 61- (d-1). It should be noted that 0 is stored in the storage means 61-1. Further, the stored values of the storage units 62-1 to 62- (d-1) are retained as they are. Then, the order difference counter 6
The above operation is repeated until the content of 9 becomes 0.

When the content of the order difference counter 69 is 0, the judging means 70 outputs an instruction signal for setting the content of the order difference counter 69 to 1. Further, the order difference counter 69 outputs an instruction signal for decreasing the content of the remainder order counter 68 by 1. Further, selection signals of the selector 66 and the selector 67 are output from the determination means 70, and the selector 67 stores the storage means 61-1 to 61- (d-
The contents of 2) are selected. Then, the multiplication means 63 multiplies the value calculated and held by the division means 64 by the contents of the storage means 62-1 to 62- (d-1), and the addition means 65 calculates the result of the multiplication means 63 and the selector 67. Perform an exclusive OR operation that adds the output together. Then, the output of the addition means 65 is stored in the storage means 62-2 to 62- (d-
Store in 1). Note that 0 is stored in the storage unit 62-1. Further, in the selector 66, the storage means 62
The contents of -1 to 62- (d-1) are selected and stored in the storage means 61-1 to 61- (d-1).

That is, the content of the order difference counter 69 is 0.
The operation of the previous section repeated until the following becomes, and this operation when the content of the order difference counter 69 is 0, the storage means 61
The divided polynomials stored in -1 to 61- (d-1) are divided by the divided polynomials stored in the storage units 62-1 to 62 (d-1), and the remainder is calculated in the next division. The storage means 62-1 to 62- (d-1) store the division polynomial, and the storage polynomial stored in the storage means 62-1 to 62- (d-1) is stored as the dividend polynomial in the next division. This is stored in the means 61-1 to 61- (d-1).

The above operation is repeated until the value of the remainder degree counter 8 becomes smaller than [(d-1) / 2] = 8. At this time, the values stored in the storage means, 62-1 to 62- (d-1), are the coefficients of the error number polynomial.

Example 7. In the above embodiment, the storage means is one.
The Reed-Solomon code having a 6-stage configuration and capable of error correction up to 8 symbols has been described, but the design distance d is 1
Even when the correction symbol number k is smaller than 7 and the correction symbol number k is smaller than 8 symbols, the operation of the Euclidean algorithm can be performed by the configuration of the storage means of 16 stages as in the sixth embodiment. That is, when setting the initial value, the syndrome S _i (i = 0, 1, ..., 2k−1) is set to S ₀ , S
Storage means 62-1 and 62 _-in the order of ₁ , ..., S _2k-1.
2, ..., 62-2k, and the storage means 62- (2
0 is input to k + 1), ..., 62- (d-1). Also, the value of the remainder degree counter 68 is set to 15,
By setting the value of the order difference counter 69 to d-16 and performing the operation of the Euclidean algorithm until the value of the remainder order counter becomes smaller than k, the coefficient of the error number polynomial is calculated. Is storage means 6
2-1 to 62- (d-1).

Example 8. FIG. 9 is a block diagram showing a Euclidean algorithm operation unit and an error position calculation unit configured by using the product sum operation cells shown in FIG. In FIG. 9, a portion 71 surrounded by a dotted line is the Euclidean algorithm operation unit 71 described in FIG. 7, and a portion 72 surrounded by a dotted line is an error locator polynomial calculation unit 75-1 to 75-.
(D-2) and 76-1 to 76-d are the product-sum operation cells shown in FIG. Regarding other numbers, the same numbers indicate the same configurations and the same functions.

The Reed-Solomon code having the design distance d will be described below. At this time, in FIG. 9, the Euclidean algorithm operation unit 71 determines that the product-sum operation cell 75-
1-75- (d-2) (d-2) -stage superposed memory means for storing the highest-order coefficient of the divisor polynomial and the dividend polynomial.
(D-1), 62- (d-1) and storage means 61- (d
It is composed of a selector 66 for selecting an input to -1) and a Galois field division means 64. The error locator polynomial calculator 72 has a structure in which d-stages of product-sum operation cells 76-1 to 76-d are stacked.

Next, the operation will be described. The Euclidean algorithm operation unit 71 has been described in the sixth embodiment, and thus its description is omitted. The operation of the error locator polynomial calculator 72 will be described. First, as an initial setting, the storage means 61-1 to 6-6 in the operation cells 76-1 to 76-d are set.
0 is set for 1-d, and operation cells 76-1 to 7-7
The storage means 62-2 to 62-d in 6-d are set to 0, and the storage means 62-1 is set to 1.

According to the contents of the storage means 62- (d-1) and the value of the order difference counter 69 in the Euclidean algorithm operation part 71, the selector 66 and the selector 67 in the operation cells 76-1 to 76-d are respectively subjected to the Euclidean algorithm operation. Switching operations similar to those of the selectors 66 and 67 of the respective arithmetic cells in the unit 71 are performed. Then, the result of division by the division means 64 is input. This operation is repeated until the value of the remainder order counter becomes smaller than a predetermined value. As a result, the storage units 62-1 to 62 in the error locator polynomial calculation unit 72.
The value stored in -d becomes the coefficient of the error locator polynomial.

Example 9. FIG. 10 is a block diagram of a second product-sum operation cell that constitutes the Euclidean algorithm operation unit and the error locator polynomial operation unit that can correct both errors and erasures. In the figure, reference numeral 77 is a selector circuit corresponding to the selector circuit 67, and the input / output signal lines A _i , B
_i , C _i , A _{i + 1} , B _{i + 1} , and C _{i + 1} are connected to another product-sum operation cell, and the dividing means 64 is connected to the input signal line R.
The value calculated in or the element on the Galois field stored in the vanishing position storage means is input. In addition, FIG.
FIG. 2 is a block configuration diagram of a disappearance position storage device, in which 80 is a storage unit for storing the disappearance position,
Reference numeral 81 is an address generation means for generating an address of the storage means 80, and 82 is a lost position information generation means for generating data to be written in the storage means 80.

FIG. 12 is a block diagram showing the Euclidean algorithm operation unit and the error position calculation unit configured by using the second product-sum operation cell shown in FIG. 12
At 85-1 to 85- (d-2) and 86-1
˜86-d are the product-sum operation cells shown in FIG.
Reference numeral 7 denotes a selector circuit for selecting one of the output of the division means 64 and the output of the erasure position storage means 80 and inputting it to the Euclidean algorithm operation part 83 and the error locator polynomial calculation part 84. Further, regarding other numbers, the same numbers indicate the same configurations and the same functions.

Next, the operation will be described. In the following, n1
For decoding a product code of × n2, first, an error correction operation is performed n2 times for a C1 code having a code length n1, and if the error cannot be corrected, the received word symbol is considered to be lost, and a C2 code having a code length n2 is n1. The case of performing the erasure error correction will be described. First, before the decoding of the product code is performed, the element α ⁿ² on the Galois field is stored in the storage unit of the erasure position information generating means 82 as an initial value. This value is multiplied by α ^-1 every time the decoding operation of the received word of the C1 code is completed.

First, since the erasure error correction operation is not performed for the decoding operation of the C1 code, the selector 87 always selects the input from the dividing means 64. Further, in order to perform the operations described in the sixth and eighth embodiments, the product-sum operation cells 85-1 to 85- (d-2), depending on the values of the determination means 70 and the order difference counter 69,
86-1 to 86-d selector 66 and selector 87
By manipulating, the coefficients of the error locator polynomial and the error number polynomial are calculated. Further, when the error correction is impossible at the time of C1 decoding, the value of the erasure position information generating means 82 shown in FIG. 11 is stored in the place indicated by the address generating means 81 in the erasure position storing means 80. Then, the value of the address generation means is incremented by 1.

Next, at the time of C2 decoding, first, for initialization, the values described in the sixth and eighth embodiments are set. Next, the values of the disappearance position storage means 80 are sequentially output. At this time, the selector 87 shown in FIG. 12 outputs the value of the disappearance position storage means 80, and the product-sum operation cell 85-
1-85- (d-2) and 86-1 to 86-d, the selector 77 has Ci (i = 1, 1) in FIG.
2, ..., D) signal lines are selected, and storage means 62-1 to 62- in the Euclidean algorithm operation unit 83 are selected.
The value of (d-1) and the values of the storage units 62-1 to 62-d in the error locator polynomial calculation unit 84 are rewritten. When all the disappearance position information is input, the storage means 62-1 to 6-6 in the Euclidean algorithm operation unit 83.
The correction syndrome is stored in 2- (d-1), and the storage unit 62- in the error locator polynomial calculation unit 84 is stored.
The coefficients of the erasure position polynomial are stored in 1 to 62-d.

Next, the division operation described in the sixth and eighth embodiments is performed. At this time, in order to perform the operations described in the sixth and eighth embodiments, the sum-of-products operation cell 85-1 is set according to the values of the determination means 70 and the order difference counter 69.
~ 85- (d-2), 86-1 to 86-d selector 6
6 and the selector 77 are operated to operate. However, the termination condition is to terminate the operation when the value of the remainder degree counter 68 becomes smaller than [(d-1 + e) / 2], where e is the number of disappearances.

[0063]

Since the present invention is constructed as described above, it has the following effects.

Since the circuit scale of the 2-input 1-output exclusive OR circuit, which is a constituent element of the multiplication means on the Galois field in the error numerical calculation circuit, is configured to be small, the number of stages of the exclusive OR circuit is reduced. This has the effect of reducing the size and enabling high-speed operation.

Further, according to the present invention, the multiplication operation in the arithmetic means can be omitted by appropriately selecting the relationship between the constant set in the first multiplication means and the constant set in the second multiplication means. It is possible to reduce the circuit scale.

Further, storage means for performing a chain search operation,
The multiplication means can be shared with the storage means for performing the error numerical value calculation operation and the multiplication means, and the circuit scale can be reduced.

Further, by changing the input to the storage means according to the value of the degree difference counter of the divisor polynomial and the dividend polynomial, the storage means for the error position polynomial and the error value polynomial is always kept constant, and the next Chien search operation is performed. At this time, since the error locator polynomial and the error numerical polynomial can be read out as they are without using a selector for the calculation, the circuit scale can be reduced and the control can be easily performed.

Further, since the contents of the erasure position storage means for storing the erasure position are inputted to the Euclidean algorithm operation means and the error locator polynomial operation means, the correction syndrome and the coefficient of the erasure position polynomial can be calculated, so that the erasure error is generated. There is an effect that correction can be performed and error correction capability is improved.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a first embodiment and a second embodiment of the present invention.

FIG. 2 is a block diagram for explaining a third embodiment and a fourth embodiment of the present invention.

FIG. 3 is a block diagram for explaining a fifth embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional error numerical value calculation circuit.

FIG. 5 is a block diagram showing a configuration of a conventional error correction decoding device.

FIG. 6 is a block diagram showing an example of a hardware configuration of a Euclid algorithm operation unit.

FIG. 7 is a block diagram for explaining a sixth embodiment and a seventh embodiment of the present invention.

FIG. 8 is a first part of the first cascaded product-sum calculation means of FIG.
3 is a block diagram showing a product-sum calculation cell of FIG.

FIG. 9 is a block diagram for explaining an eighth embodiment of the present invention.

FIG. 10 is a block diagram showing a second product-sum operation cell which constitutes a third cascaded product-sum operation means in embodiment 9 of the present invention.

FIG. 11 is a block diagram showing an erasure position storage means in embodiment 9 of the present invention.

FIG. 12 is a block diagram for explaining a ninth embodiment of the present invention.

[Explanation of symbols]

 1 1st input terminal 2 2nd input terminal 3 3rd input terminal 4 1st memory means 5 2nd memory means 6 3rd memory means 7 1st multiplication means 8 2nd multiplication means 9th 3 multiplication means 12 operation means 14 second multiplication means 15 division means 16 fourth input terminal 17 fourth storage means 18 fourth multiplication means 53 syndrome calculation circuit 55 chain search circuit 56 error numerical value calculation circuit 61 first Storage means 62 second storage means 63 multiplication means on Galois field 64 division means on Galois field 65 addition means on Galois field 66 first selector circuit 67, 77 second selector circuit 68 order difference counter 69 remainder Order counter 70 Judgment means 71 Euclidean algorithm operation part 72 Error locator polynomial operation part 75, 76 First product-sum operation cell 80 Erasure position storage means 81 Second product sum operation cell 87 dress generator 82 erasure position information generating means 85, 86 the third selector circuit

Claims (8)

[Claims] 1. An error correction decoding device for a Reed-Solomon code on GF (2 ⁿ ), wherein: first storage means for storing a coefficient of an error number polynomial as an initial value; The contents of the above error numerical polynomial are in descending order of constant α ^j on the Galois field,
The first multiplication means for multiplying α ^j-1 , α ^j-2 , α ^j-3 , ..., The number of exclusive OR circuits of 2 inputs and 1 output which constitute the first multiplication means is minimum. An error correction decoding apparatus comprising: a unit for predetermining the value of j so as to satisfy the above condition; and a unit for storing the multiplication result of the first multiplication unit in the first storage unit. 2. An error correction decoding apparatus for Reed-Solomon code on GF (2 ⁿ ) in which a second storage means for storing an odd-order coefficient of an error locator polynomial as an initial value, the second storage means The second is obtained by multiplying the stored contents by the constants α ⁱ , α ^i-2 , α ^i-4 , α ^i-6 , ... on the Galois field in ascending order of odd order of the error locator polynomial. Means for predetermining the value of i such that the number of 2-input 1-output exclusive OR circuits constituting the second multiplication means is minimized, and the multiplication result of the second multiplication means is An error correction decoding device, comprising: a means for storing in the second storage means. 3. An error correction decoding apparatus for Reed-Solomon code on GF (2 ⁿ ) wherein the generator polynomial is: In the first storage means for storing the coefficient of the error number polynomial as the initial value, the second storage means for storing the odd-order coefficient of the error locator polynomial as the initial value, The constant α ^j on the Galois field in descending order of the error numerical polynomial with respect to the stored contents,
First multiplication means for multiplying α ^j-1 , α ^j-2 , α ^j-3 , ..., Means for storing the multiplication result of the first multiplication means in the first storage means, k = means for calculating k by j + m-1, and constants α ^k , α ^k-2 , α on the Galois field in order of increasing odd order of the error locator polynomial with respect to the contents stored in the second storage means. second multiplication means for multiplying ^k-4 , α ^k-6 , ..., Means for storing the multiplication result of the second multiplication means in the second storage means, Error correction decoding device. 4. In the error correction decoding device for Reed-Solomon code on GF (2 ⁿ ), the generator polynomial is: In the second storage means, the first storage means stores the coefficient of the error number polynomial as an initial value, the second storage means stores the odd-order coefficient of the error locator polynomial as the initial value, The second is obtained by multiplying the stored contents by the constants α ⁱ , α ^i-2 , α ^i-4 , α ^i-6 , ... on the Galois field in ascending order of odd order of the error locator polynomial. Means for storing the multiplication result of the second multiplication means in the first storage means, means for calculating k by k = i + m−1, and contents stored in the first storage means. On the other hand, in order of increasing order of the error numerical polynomial, the constant α ^k on the Galois field,
first multiplication means for multiplying α ^k-1 , α ^k-2 , α ^k-3 , ..., Means for storing the multiplication result of the first multiplication means in the first storage means An error correction decoding device characterized by the above. 5. The error correction decoding device according to claim 3, wherein the second storage means and the second multiplication means are shared by the storage means and the multiplication means of the Chien search circuit. Decoding device. 6. A first cascaded product-sum operation means configured by cascading a predetermined number of first product-sum operation cells, each first product-sum operation cell storing a coefficient of a dividend polynomial. First storage means 61 for
-I and second storage means 62 for storing the coefficient of the divisor polynomial-
i, the content of the first storage means and the content of the first storage means, and outputs any one of the two inputs as one input of the addition means 65 on the Galois field. 67, a multiplication unit 63 in the Galois field that multiplies the contents of the second storage unit and an input from the outside, and outputs the multiplication result as one input of the addition unit; Outputs two input signals to the next stage A _{i + 1} , B
_The means for outputting _{i + 1} , the input signal A _i from the preceding stage, and the contents of the second storage means are inputted and either output of either input is blocked, or either input is set to the first input. First cascaded product sum computing means having a first selector circuit 66 for outputting as an input of the storing means and a connecting line for inputting an input signal B _i from the preceding stage to the second storing means; The contents of the second storage means 62- (d-1) (d is the design distance) at the final stage of the cascaded product sum calculation means are divided by the contents of the first storage means 61- (d-1), and the division is performed. The division means 64 on the Galois field that temporarily holds the result and outputs it as the input from the outside, the remainder degree counter 68 in which the degree of the remainder polynomial is set, the difference between the degree of the dividend polynomial and the degree of the divisor polynomial Order difference counter 69 to be set, the storage means 62- (d-1) Determination means 70 for controlling the first cascaded product-sum calculation means in accordance with the contents of the order difference counter and the contents of the order difference counter, the storage means 61- (d-1) is set to logic "1", and the storage means 62- The logic "0" is set in (d-2), the numerical value of (d-2) is set in the remainder order counter, and the numerical value 1 is set in the order difference counter, and the syndrome S _i generated from the received word is set. Storage means 62− in the order of S ₀ , S ₁ ...
Initial value setting means input to 1, 62-2, ... When the content of the storage means 62- (d-1) is logical "0", the content of the remainder order counter is decremented by 1 to obtain the order difference. A shift control means for incrementing the content of the counter by 1 and inputting the content of the second storage means to the second storage means of the next stage via the second selector circuit and the addition means, storage means 62- (d-1) ) Is not 0, and the content of the order difference counter is not 0, the content of the order difference counter is decremented by 1, and the content of the first storage means and the multiplication means 63 are added.
If the contents of the remainder computing means for adding the output of the above-mentioned by the adding means 65 and inputting to the first storing means of the next stage, the storing means 62- (d-1) is not 0, the content of the order difference counter is 0. For example, the content of the order difference counter is set to 1, the content of the remainder order counter is decremented by 1, and the output of the adding means 65 is input to the second storage means.
The contents of the second storage means are passed through the first selector circuit to the first
And a Euclidean algorithm operation means for repeating the shift control means, the remainder operation means, and the divisor exchange means until the content of the remainder degree counter becomes a predetermined value or less. Characteristic error correction decoding device. 7. The Euclidean algorithm operation means according to claim 6, wherein the first product-sum operation cell is cascaded one stage at the final stage of the operation means similar to the first cascaded product-sum operation means. Done second
The cascaded product-sum calculation means of, the output of the division means of the Euclidean algorithm calculation means is connected as an input from the outside of the second cascaded product-sum calculation means,
Control means for controlling the arithmetic operation in the second cascade product sum arithmetic means in parallel with the arithmetic operation in the Euclidean algorithm arithmetic means according to the contents of the judging means, the remainder degree counter, and the order difference counter, and the second cascaded product sum arithmetic means. Second storage means 6 of the first stage
2-1 is provided with a logic "1" and all other second storage means and first storage means are provided with an initial value setting means for setting a logic "0", and the content of the remainder order counter is predetermined. An error correction decoding apparatus characterized in that the Euclidean algorithm operation is repeated until the value becomes less than or equal to the value of ## EQU1 ## and the value stored in the second storage means is used as a coefficient of the error locator polynomial. 8. A third cascaded product-sum operation means configured by cascading a predetermined number of second product-sum operation cells, each second product-sum operation cell being the first product-sum operation. Second in the cell
A third input is added to the selector circuit of the third cascaded product sum calculation means to which the contents of the second storage means 62- (i + 1) of the next stage is input as the third input, Contents of the second storage means 92- (d-1) at the final stage of the cascaded product-sum calculation means of the first storage means 91- (d-
The division means 64 on the Galois field that divides by the contents of 1) and temporarily holds the division result, and the third selector circuit 8 that switches and outputs this division means and the disappearance information read from the disappearance position storage means 80.
7. Fourth cascaded product-sum calculation means in which one stage of the second product-sum calculation means is cascaded at the final stage of the calculation means similar to the third cascaded product-sum calculation means, and the third cascade connection Means for connecting the output of the third selector circuit as an external input to each of the second product-sum calculation means of the product-sum calculation means and the fourth cascaded product-sum calculation means, and disappearance from the disappearance position storage device. When the information is read, the third selector circuit outputs the lost information,
The second selector circuit of each of the second product-sum operation means includes means for outputting the contents of the second storage means of the next stage, and an error characterized in that both an error and an erasure can be corrected. Correction decoding device.