JPH047847B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error control code decoding device.

[Conventional technology]

Figure 6 shows, for example, literature (Kimura, Imai, Doi;
“Reed based on Systrick algorithm
“Solomon code decoder construction method”, IEICE Technical Report
Vol84, No.321, AL84-76, PP.55-62, March 1985)
This figure shows the configuration of a t-fold error correction decoder based on the systolic algorithm.

In the figure, 1 is a syndrome cell circuit, 2
3 is a receive data input terminal rin, 3 is a command input terminal COMin, 4 is a data input terminal yin, 5 is a syndrome output signal line yout, and 6 is a command output signal line COMout. 7 is GCD (Greatest
Common Divisor) cell circuit, 8 is the order data input signal line degin, 9 is the command input signal line
startin, 10 is the variable data input signal line Verin, 1
1 is an order data output signal line degout, 12 is a command output signal line Startout, and 13 is a signal line verout for outputting the error locator polynomial σ(x) and the error value polynomial n(x). 14 is the Galois field element αi (i=
1, 2, ..., n; n is the code length) was memorized.
ROM 15 is an address data input signal line ADin. 16 is an evaluation cell circuit, 1
7 is a ROM data input signal line Xin, 18 is a command input signal line COMin, and 19 is an input signal for error locator polynomial σ(x), error value polynomial n(x), and differential σ'(x) of error locator polynomial. line fin, 20 is n
(αi), σ′ (αi) output signal line, 21 is σ(αi)
This is the output signal line. 22 is a circuit for obtaining an error value at position i estimated to be an error, and a gate circuit for outputting it; 23 is an error value output signal line; 24 is a buffer memory; 25 is a buffer output signal line; 26 is a Galois field. 27 is a decoded data output terminal Dout. Also, 28 is the syndrome-GCD interface circuit, and 29 is the syndrome-GCD interface circuit.
This is a GCD-Evaluation interface circuit.

Reference numeral 30 in FIG. 7 is a model of a subcell constituting the syndrome cell circuit 1, 31 is an input signal line for the received data in the previous stage, 32 is a command input signal line, 3
3 is a syndrome input signal line in the previous stage, 34 is a register that stores the term αi of the generator polynomial for syndrome Si, 35 is a register that stores intermediate calculation results for syndrome Si, and 36 is a syndrome
A register for storing Si, 37 is an output signal line for the received data to the next stage, 38 is a command output signal line,
39 is a syndrome output signal line to the next stage.

Reference numeral 40 in FIG. 8 is a model of a subcell constituting the GCD cell circuit 7, and 41 to 44 are input signal lines (ain, bin, lin,
min), 45 is the command input signal line startin, 46
~49 is the input signal line (degAin,
degBin, degLni, degMin), 50 is a register state that stores the processing mode of the subcell, 51, 52
are registers that store constants used in processing, 53~
63 are input data delay registers (a,
b, l, m, start, degA, degB, degL,
degM) 64 to 67 are the output signal lines (aout, bout, lout, mout) of the coefficients of each polynomial, 68 is the command output signal line startout, and 69 to 72 are the output signal lines of the order after processing in the subcell (degAout,
degBout, degLout, degMout).

In FIG. 9, 73 is a model of a subcell constituting the Evaluation cell circuit, 74 is a signal line Xin that inputs the Galois field element αi corresponding to position i, 75 is a command input signal line COMin, and 76 is a data input terminal fin. , 77 is a register fi for storing the error locator polynomial σ(x), its differential σ'(x), and the i-th coefficient of the error value polynomial n(x), 78 is an αi output signal line Xout, 7
9 is a command output signal line COMout, and 80 is a processed data output signal line fout.

FIG. 10 shows the calculation algorithm of the GCD cell circuit 7 and the interfaces 28 and 29 before and after it. Here step 81 is syndrome-
GCD interface circuit operation, step 82
~85 is the operation of the GCD cell circuit, steps 86~88 are
3 illustrates the operation of the GCD-Evaluation interface circuit.

Next, the operation will be explained. In Fig. 6, the command input terminal 3 is connected to the beginning of the received data.
Enter the 'start' command. The received data is input to the syndrome cell circuit 1 through the received data input terminal 2, and is also stored in the buffer memory 24. Also, zero is always input to the data input terminal 4.

At this time, in Fig. 7, numbers #0 to #2t-
The syndrome cell circuit 1 composed of 1 (t=d-1/2) subcells 30 calculates syndromes of S ₀ to _{S 2t-1} , respectively. The subcell 30 that receives the 'start' command along with the first data stores the data in the register S35. From the next received data, a 'calc' command is input from the command input terminal 3. At this time, the subcell 30 performs a product-sum operation of S=S.X+rin on the input data input from the reception data input terminal rin2.
Here, X is data in register X34, which stores the root of the generator polynomial. During this time, syndrome input signal line yin33, syndrome output signal line yout
39 and register y36 are zero. code length n
When the nth data is input as , 'end' is input to the command input signal line 32. At this time, the product-sum operation result for S is the register y3
Syndrome output signal line stored in 6 and sequentially sent to syndrome-GCD interface circuit 28
Output from yout5.

Syndrome-GCD interface circuit 2
8 performs the operation 81 of the algorithm in FIG. Here, the syndrome polynomial S(x) for the syndrome is S(x)=S _2t-1 X ^2t-1 +...+
S ₁ X + S ₀ . Also A, B, L, M
Also check the maximum degree of the polynomial. Syndrome
After receiving the 'end' signal on the command output signal line 6, the GCD interface circuit 28 inputs 'start=1' on the command input signal line 9, and also inputs A, B, L on the variable data input signal line 10. , M, and the maximum degree data of each polynomial are output to the degree data input signal line 8.

Here, it is composed of the subcell 40 shown in FIG.
The GCD cell circuit 7 performs each step 82-85 of the algorithm shown in FIG. The above command'
When start=1', the maximum degree coefficient of the polynomial B input from the input signal line bin42 is input to the α register 51,
The maximum degree coefficient of the polynomial A input from the input signal line ain41 is stored in the β register 52. Also input signal line degAin46, input signal line
Comparing the data of degBin47, one of them is t
If smaller than (t(d-1)/2, d: minimum distance), no operation is performed, 'nop', degAdegB>
If t, then the calculation at step 83 in FIG. 10 is performed. Also, if 'reduceA', degB>degA>t, then the first
The calculation at step 84 in Figure 0 is performed. Also'
Store reduceB' in state register 50. These data are held until the next command 'start=1' is received, and calculations are performed according to the state register 50. For input data 1 to 2t-1, command input signal lines 9 and 45 input 'start=0', and order data input signal line 8 and input signal lines 46 to 49 input zero. In one subcell 40, the order of either A or B decreases by one, and the order of L or M increases by one, so the maximum order data is sent to the next stage at the same time as A, B, L, and M. The signals are output to output signal lines 64-72 using delay registers 53-63 so that the signals can be output.

When 'start=1' is output from the command output signal line 12 of the GCD cell circuit 7, the GCD-Evaluation
The interface circuit 29 is the GCD cell circuit 7
is input on the order data output signal line 11 of
Steps 86, 87, and 88 in FIG. 10 are performed using degA, degB, degL, degM and A, B, L, and M input from the variable data output signal line 13. Further, the error locator polynomial σ(x) is differentiated to obtain the differential σ'(x) of the error locator polynomial. The output is command'
When start=1' is received, the command 'load' is sent to the command input signal line 18 of the Evolution cell circuit 16.
#i' (i=t, . . . , 1, 0) is output, and then 'calc' is output n times. When sending this 'calc', position i (i=n,...,
Address data is sent to the address data input signal line 15 so that the element αi for 2, 1) is output to the input signal line 17.

The Evalution cell circuit 16 has numbers #0 to
It is composed of #t subcells 73. The register fi77 with number #i stores the coefficient data of the error locator polynomial σ(x), the differential σ'(x) of the error locator polynomial, and the error value polynomial n(x) at the time of the 'load#i' command. to command input signal line 18'
At the same time that celc' is input, data in the ROM 14 is input to the input signal line Xin 17. At this time, 1 is input to the input signal line fin19. Subcell 73 where 'calc' is input is fout80=fin76・Xin74
Perform the calculation +fi77, COMout79=COMin75,
It is output to the output signal lines 78 to 80 as Xout78=Xin74. When this is carried out to the subcell with number #t, the error locator polynomial σ(αi) is on the output line 21 of fout, and the error value polynomial n(αi) and the error locator polynomial are on the output line 20 of fout #t-1. The differential σ′(αi) of is obtained. Here, αi is the element of the Galois field corresponding to the position i output from the ROM 14.
(i = 1, 2, ..., n) Gate circuit 2 that calculates the error value at position i
2, when the obtained error position polynomial σ(αi) is zero, it is determined that an error has occurred at position i, the error value is calculated by n(αi)/σ′(αi), and the gate circuit 22 is opened and the error value is output to the output signal line 23, and the data at position i is output from the buffer memory 24 to the signal line 25 and the Galois field adder 26.
The decoded data is corrected by the decoded data output terminal 27 and outputted from the decoded data output terminal 27.

[Problem that the invention seeks to solve]

Since the conventional decoding device based on the systolic algorithm is configured as described above, it has the problem that it can only correct errors and does not have a correction function for erasures.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a decoding device based on a systolic algorithm that can perform error correction as well as erasure correction.

[Means for solving problems]

a syndrome cell circuit that inputs received data and calculates a syndrome; a flag signal output circuit that outputs a flag signal corresponding to the received data and the erasure position; and an erasure position generation circuit that generates erasure position symbol data corresponding to the flag signal. , a modified syndrome cell circuit that outputs a modified syndrome by removing erasure position information from the syndrome data series output from the syndrome cell circuit, and an error location polynomial σe(x) and an error erasure value polynomial from the modified syndrome data series. n
A GCD cell circuit that obtains a data sequence of coefficients of (x), and coefficient data of the error erasure position polynomial σ(x) from the data sequence of the error position polynomial σe(x) and the erasure position data sequence of the erasure position symbol data. a multiplier cell circuit that outputs the error erasure position and a numerical value from the coefficient data of the error erasure position polynomial σ(x) and the error erasure value polynomial n(x); The present invention is characterized by comprising a gate circuit for correcting the received data based on the error erasure position and numerical value.

[Effect]

The syndrome cell circuit according to the present invention receives received data and outputs a syndrome.

Further, the flag signal output circuit outputs the received data and a flag signal corresponding to the erasure position of the received data.

Here, the vanishing position generation circuit generates vanishing position symbol data corresponding to the flag signal, and the modified syndrome cell circuit outputs a modified syndrome that removes vanishing position information from the syndrome data series output from the syndrome cell circuit. . The GCD cell circuit obtains data sequences of the coefficients of the error locator polynomial σe(x) and the error erasure value polynomial n(x) from the data sequence of the modified syndrome, and outputs them to the multiplication cell circuit. The multiplication cell circuit obtains coefficient data of the error locator polynomial σ(x) from the data series of the error locator polynomial σe(x) and the erasure locator data series of the erasure locator symbol data.
Output to Evaluation cell circuit.

Evaluation cell circuit is error erasure position polynomial σ
(x) and the coefficient data of the error erasure numerical polynomial n(x), the error erasure position and numerical value are determined and output to the gate circuit. The gate circuit corrects the received data based on the error erasure position and numerical value determined by the evaluation cell circuit.

〔Example〕

An embodiment of the present invention will be described below based on the drawings.

First, the solution algorithm of the present invention will be explained.

The error correction solution algorithm of the conventional apparatus described above is generally called the Euclidean decoding method. (Reference: Y: Sugiyama, M. Kasahara, S.
Hirasawa and T.Namekawa, “A Method
for Solving Key Equation for Decoding
Goppa Codes”, Inform.Conter., Vol27, pp.87
−99, Jan. 1975) This algorithm also applies error-erasure correction with the number of errors ne, the number of erasures nε,
If the minimum distance between codes is d=2t+1, then 2ne+nε<
If d, the modified syndrome Sε(x), Sε(x)
= σε(x)・S(x) modg(x), g( ^x ) =
Y.Sugiyama, M.Kasahara, S.Hirasawa and
N. Namekawa, “An Erasures−Errors
Decoding Algorithm for Goppa Codes”，
IEEE Trans, Inform.Theory (Corresp.) to
appear, Mar. 1976). Here, σε(x) is the vanishing position polynomial, and S(x) is the syndrome polynomial.

Based on this, one embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a t-fold error erasure correction circuit based on the systolic algorithm according to the present invention.

1 to 27 are the same in structure as in FIG. 8
9 is a vanishing position generation circuit that generates a Galois field element αij for vanishing position ij (j=1, 2, ..., d-1); 90 is a flag signal output circuit that outputs a flag signal of the vanishing position; 91 is a flag signal output circuit that outputs a flag signal of the vanishing position; Vanishing position coefficient output signal line LDout, 92 a syndrome-correction syndrome interface circuit, 93 a vanishing position coefficient latch circuit, 94 a correction syndrome cell circuit, 9
5 is a vanishing position coefficient input signal line LDin, 96 is a command input signal line COMin, 97 is a vanishing position output signal line LSout, 98 is a syndrome input signal line Yin,
99 is the modified syndrome output signal line Yout, 10
0 is the command output signal line COMout, 101 is the erasure location coefficient output signal line LDout, 102 is the modified syndrome-GCD interface circuit, 103 is the erasure location coefficient latch, 104 is the erasure location input signal line LDin, 105 is the erasure location output signal line LDout,
106 is a GCD-multiplication interface circuit, 1
07 is a multiplication cell circuit, 108 is an error-vanishing numerical polynomial latch, and 109 is an error-vanishing numerical polynomial n.
(x) input signal line EEin, 110 is command input signal line COMin, 111 is error locator polynomial σe(x)
112 is the erasure position coefficient input signal line LDin, 113 is the output signal line EEout of the error-erasure numerical polynomial n(x), 114 is the error-
Output signal line ELout of vanishing position polynomial σ(x), 1
15 is a command output signal line COMout, and 116 is a multiplication-evaluation interface.

FIG. 2 shows an example of the configuration of the vanishing position generating circuit 89, in which 3, 90, and 91 are the same as in FIG. 1, and 11
7 is a control circuit, 118 is a latch control circuit related to the latch, and 119 is αi that generates the Galois field element αi.
generation circuit, 120 is a group of latches #0 to #2t-1;
121 is a control signal line related to the αi generation circuit; 122
123 is a latch control signal line outputted from the control circuit 56; 124 is a latch control signal line;
is the αi data signal line.

FIG. 3 is an example of a configuration diagram of the vanishing position coefficient latch 93, where 125 is a latch, 126 is a control circuit, and 12
7 is a selector circuit, 128 is a latch trigger signal line, 129 is a selector control signal line, 95, 9
6, 97, 101 are the same as those in FIG.

Reference numeral 130 in FIG. 4 is an example of the configuration of subcells of the correction syndrome circuit and the multiplication cell circuit, 131 is a command input signal line COMin, 132 is an erasure position coefficient input signal line Xin, 133 is a data transfer input signal line Yin, 134- 136 is a latch for input data, 137 is a control circuit, 138 is latch A, 13
9 is a latch B, 140 is a Galois field adder circuit, 1
41 is a Galois field multiplication circuit, 142 is a selector circuit, 143 is a latch trigger signal line, 144 is a selector control signal line, 145 to 147 are output data latches, 148 is a command output terminal COMout,
149 is the erasure position coefficient output signal line Xout, 150
is the data transfer output signal line Yout.

150 in FIG. 5 is a subcell model of the GCD cell circuit 7 in FIG.
The model is the same as that of the GCD subcell 40 in FIG. 8, except for the t delay latch 52 and the tout output signal line 153.

Next, the operation will be explained. Here, when the number of error symbols is ne and the number of lost symbols is nε,
It is assumed that 2ne+nε<d (d is the minimum distance between codes).

The erasure flag signal output from the flag signal output circuit 90 is synchronized with the received data input from the input terminal 2. The operation of the syndrome cell 1 is the same as the conventional device. On the other hand, when the erased position generating circuit 89 added in the present invention receives a 'start' command from the command input terminal 3, the control circuit 117 sends the αi generating circuit 119 through the control signal line 121.
turns on, and the position i is synchronized with the received data.
The Galois field element αi corresponding to αi data signal line 12
Output to 4. When the position ij disappears, that is, when the flag signal output from the flag signal output circuit 90 is asserted, a latch signal is output to the latch control signal line 123 through the latch control circuit 118,
αij indicating the position is stored in the register 59. After 'end' is input from command input terminal 3,
The control circuit 56 outputs a signal to the control signal line 122, the latch control circuit 57 outputs a shift signal to the latch control signal line 123 2t times, and outputs the erasure position coefficient αij to the erasure position coefficient output signal line 91.

In the syndrome-modified syndrome interface circuit 92, from syndrome cell 1 to 'end'
After receiving the command, it outputs the 'load#i' (i=2t-1 to 0) command to the command input signal line 96, and also outputs the syndrome Si (i=2t-1 to 0) input from the syndrome output signal line 5. ) is output to the input signal line 98 of the modified syndrome cell circuit 94. At the same time, the output signal line 91 of the vanishing position coefficient
The data input from the vanishing position coefficient latch circuit 9
3 input signal line 95 and stored in latch group 125.

The modified syndrome cell circuit 94 according to the present invention is composed of subcells 130 with numbers #0 to #2t-1, and the subcell with number #i is a control circuit when 'load#i' is input to the command input signal line 132. 137 outputs a latch signal to the latch signal line 143, and the Si data latched in the Yin latch 136 is stored in the latch A138. At this time, the selector circuit 142 indicates that zero is Yout latch 1.
47. Also So(j≠i)
In this case, the control circuit 137 controls the selector control signal line so that So is input to the Yout latch 147. After the command 'load #0' has been input to the command input signal line 96, the 'calc' command is input. At this time, the control circuit 126 of the erasure position coefficient latch circuit 93 selects one of the erasure position coefficient data with the selector circuit 127 through the selector control signal line 129 and outputs it to the output signal line 97. This output data is input to the Xin latch 135 of the subcell 130#0 of the modified syndrome cell circuit 94. At the same time, the signal 'calc' is input to the COMin latch 134, and the Yin latch 1
Zero is input to 36. If the Xin latch 135 is not zero, the control circuit 137 will
outputs a latch signal to latch A138 and transfers the data of Yin latch 136 to latch B139.
Latch the output data of 40. The selector circuit 142 also selects the Yout latch 147 to latch this output data. At this time, the data of the Xin latch 135 is latched to the Xout latch 149, and the command of the COMin latch 134 is
Latch to COMout latch 145. Latch B1
The data stored in 39 is processed by multiplier 141.
The data of the Xin latch 135 is multiplied by the Galois field, the output is input to the adder 140, and the latch A1
38 data and Galois field are added. This is similarly performed for subcells #1 to #2t-1. however,
Each input signal line of COMin131, Xin132, and Yin133 is connected to the previous stage COMout148, respectively.
It is connected to each output signal line of Xout 149 and Yout 150. By performing the process up to the subcell number #2t−1 for a certain erasure position coefficient αij,
This means that the calculation (X-αi)·S(x)modX ^2t (t=d-1/2) has been performed. After inputting the 'calc' command 2t times and outputting all the data of the latch group 125 from the output signal line 97, the command input signal line 9
5, the 'end' command is input. At this time, the control circuit 126 of the vanishing position coefficient latch circuit 93:
output a shift signal to the latch control signal line 128;
The data of the latch group 64 is output one after another to the output signal line 101. At this time, zero is input to the input signal line LDin95. On the other hand, modified syndrome cell 94
In the subcell 130#0, when the 'end' command is input to the COMin latch 134 from the command input line 131, the control circuit 137 outputs the latch signal line 1.
Outputs the latch signal to 43 and outputs the latch signal to latch A138.
The data from latch 136 is input, and the output data from adder 140 is latched into Yout latch 147. At this time, Xin latch 135, Yin latch 1
Zero is input to 36. Number #1~#2t-
1 subcell 1330 is also COMin134, Xin1
32, COMout1 of the previous stage to each latch of Yin133
45, Xout146, and Yout, the same operation is performed only by inputting the data of each latch. This 'end'
By outputting the command 2t times, the modified syndrome Sε(x) is output from the output signal line 99.

The modified syndrome-GCD interface circuit 102 has the functions of the syndrome-GCD interface circuit 126 of the conventional device, and
Output signal line 101 of vanishing position coefficient latch circuit 93
The input dij is sent to the erasure position coefficient latch circuit 103 at the next stage. Also, check the number of disappearances nε and te=
t + "nε/2 (" is a Gaussian symbol and indicates rounding up to a positive integer, t is the number of symbols that can be corrected when the number of erasures nε is 0, and te is the maximum degree that the error erasure position polynomial σ(x) can replace) )
It is output to the order input signal line 8 together with the order data to the GCD cell circuit 7 . The GCD cell circuit 7 has the same function as the conventional device, but the structure of the subcell 150 is different in the present invention, and the input signal line tin 151,
It has a t delay latch 152 and an output signal line tout 153, and inputs te along with a 'start=1' command from an input signal line tin151. This te is t of the conventional device.
The data changes.

The vanishing position coefficient latch circuit 103 has a configuration in which the selector circuit of the vanishing position coefficient latch circuit 93 in the previous stage is removed, and the control circuit latches 2t times after the 'start=1' command is input to the command input signal line 9. Output the signal and latch αi, and the 'start=1' command is sent to the GCD-multiplying interface circuit 10.
6 from the command output signal line 12, the erasure position coefficient αi is also output from the output signal line 105 at the same time.

The GCD-multiplying interface circuit 106 is
At the same time as the 'start=1' command is input from the command output signal line 12 of the GCD cell circuit 7, the 10th Perform calculations 86, 87, and 88 in the figure. However, t in calculations 85 and 86 is replaced by te. In this way, after identifying the error-erasure numerical polynomial n(x) and the error locator polynomial σe(x), the command input signal line 11
Input 'load#1' (i=2t~0) in 0, error -
The vanishing numerical polynomial n(x) is input from the input signal line 109,
The error-erasure numerical polynomial coefficient latch 108 latches the error locator polynomial σe(x) into the multiplication cell circuit 1.
It is input from the input signal line 111 of 07.

Subcells #0 to #2t of the multiplication cell circuit 107 for calculating the error-erasure position polynomial σ(x) added in the present invention are the subcells 13 of the modified syndrome.
It has the same structure as 0 and its operation is the same as the modified syndrome cell circuit 94.

Multiplication-Evaluation Interface Circuit 11
6 calculates the differential σ'(x) of the error locator polynomial from the error locator polynomial σ(x) inputted from the output signal line 114, and calculates the error-vanishing numerical polynomial n(x).
Both are input to the evaluation cell circuit 16.
The subsequent data processing is similar to that of the conventional device. However, the evaluation cell circuit 16 is numbered #0~
Consisting of #2t subcell 73, σ(αi) is the #2t subcell output, n(αi), σ′(αi) are #2t−
1
This is the subcell output.

In the above embodiment, the GFROM 14 is used, but the αi generation circuit 119 shown in FIG. 2 may be used instead.

〔Effect of the invention〕

As described above, the present invention includes a syndrome cell circuit that inputs received data and calculates a syndrome, a flag signal output circuit that outputs a flag signal corresponding to the received data and the vanishing position, and a vanishing position symbol that corresponds to the flag signal. an erasure position generation circuit that generates data; a modified syndrome cell circuit that outputs a corrected syndrome that removes the information on the erased position from the syndrome data series output from the syndrome cell circuit; and an error position polynomial from the corrected syndrome data series. σe
(x) and a GCD cell circuit that calculates a data sequence of the coefficients of the error-erasing numerical polynomial n(x), and the error is erased from the data sequence of the error locator polynomial σe(x) and the erasure position data sequence of the erasure position symbol data. A multiplication cell circuit that outputs coefficient data of a position polynomial σ(x), and an evaluation cell circuit that calculates an error erasure position and numerical value from the coefficient data of an error erasure position polynomial σ(x) and an error erasure numerical polynomial n(x). , and a gate circuit for correcting the received data based on the error erasure position and numerical value determined by the evaluation cell circuit, so error-erasure correction can be processed in a pipelined manner with simple control. This has the effect of making it easier to convert to VLSI.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a decoding device based on a systolic algorithm according to an embodiment of the present invention, FIG. 2 is a block diagram of an erasure position coefficient generation circuit in this invention, and FIG. 3 is a block diagram showing an erasure position coefficient generation circuit in this invention. 4 is a block diagram showing the subcell circuit of the modified syndrome cell circuit and multiplication cell circuit in this invention. FIG. 5 is a model diagram of the subcell circuit of the GCD cell circuit in this invention. is a block diagram of a decoding device based on a conventional systolic algorithm, FIG. 7 is a subcell model diagram of a syndrome cell circuit, FIG. 8 is a subcell model diagram of a GCD cell circuit of a conventional device, and FIG. 9 is an evaluation cell model. Model diagram of circuit subcells,
FIG. 10 is a flowchart of an algorithm for solving the GCD problem using a conventional device. DESCRIPTION OF SYMBOLS 1...Syndrome cell circuit, 90...Flag signal generation circuit, 89...Elimination position generation circuit, 94...Modified syndrome cell circuit, 7...GCD cell circuit, 1
07...Multiplication cell circuit, 16...Evaluation cell circuit,
22...Gate circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A syndrome cell circuit that inputs received data and calculates a syndrome, a flag signal output circuit that outputs a flag signal corresponding to the received data and the erasure position, and an erasure position symbol data corresponding to the flag signal. an erasure position generation circuit that generates an erased position; a modified syndrome cell circuit that outputs a modified syndrome that removes erasure position information from the syndrome data series output from the syndrome cell circuit; x) and error-vanishing numerical polynomial n
A GCD cell circuit that obtains a data sequence of coefficients of (x), and coefficient data of the error erasure position polynomial σ(x) from the data sequence of the error position polynomial σe(x) and the erasure position data sequence of the erasure position symbol data. a multiplier cell circuit that outputs the error erasure position and a numerical value from the coefficient data of the error erasure position polynomial σ(x) and the error erasure value polynomial n(x); and a gate circuit for correcting the received data based on the error erasure position and numerical value. 2 The modified syndrome cell circuit includes a register that stores the syndrome data series, a shift circuit that shifts the data in the register when the erasure position symbol data is input, and multiplies the data in the register and the erasure position symbol data. 2. The decoding device according to claim 1, further comprising a multiplication circuit and an adder that adds the output of the multiplication circuit and the output of the shift circuit. 3 In the above GCD cell circuit, nε is the number of erasures, t is the number of symbols that can be corrected when the number of erasures is 0, and te
When is the maximum degree that the error erasure position polynomial σ(x) can change, it must be equipped with an arithmetic circuit that calculates te = t + ``nε/2 (where `` is a Gauss symbol indicating rounding up to a positive integer). A decoding device according to claim 1 or 2, characterized in that: