JPH0637455A - Manufacture of multilayer printed wiring board - Google Patents
Manufacture of multilayer printed wiring boardInfo
- Publication number
- JPH0637455A JPH0637455A JP4187254A JP18725492A JPH0637455A JP H0637455 A JPH0637455 A JP H0637455A JP 4187254 A JP4187254 A JP 4187254A JP 18725492 A JP18725492 A JP 18725492A JP H0637455 A JPH0637455 A JP H0637455A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- inner layer
- layer circuit
- wiring board
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、スルーホールを設けて
形成される多層プリント配線板の製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board formed by providing through holes.
【０００２】[0002]
【従来の技術】多層プリント配線板は、銅箔等のエッチ
ング加工で内層回路１を設けて形成した内層用回路板を
所要枚数プリプレグを介して重ねると共にさらにその外
側にプリプレグを介して銅箔８を重ね、これを加熱加圧
して積層成形することによって図４（ａ）のような多層
板２を作成し、この多層板２に内層回路１を貫通して図
４（ｂ）のようにスルーホール３をドリル加工した後
に、図４（ｄ）のようにスルーホール３の内周にスルー
ホールメッキ４を施すことによって製造される。スルー
ホールメッキ４によって内層回路１同士や内層回路１と
外層回路を形成する外層の銅箔８とを導通接続するもの
である。2. Description of the Related Art In a multilayer printed wiring board, a required number of circuit boards for inner layers, which are formed by providing inner layer circuits 1 by etching a copper foil or the like, are stacked with a prepreg and the copper foil 8 is further provided on the outside with a prepreg. 4A, and by heating and pressurizing the layers to form a multilayer board 2 as shown in FIG. 4A, the inner layer circuit 1 is penetrated through the multilayer board 2 and a through is performed as shown in FIG. 4B. After the hole 3 is drilled, it is manufactured by applying through-hole plating 4 to the inner circumference of the through-hole 3 as shown in FIG. Through-hole plating 4 electrically connects the inner layer circuits 1 to each other and the inner layer circuit 1 to the outer layer copper foil 8 forming the outer layer circuit.
【０００３】上記のように多層板２にスルーホール３を
ドリル加工して設ける際に、積層板やプリプレグから構
成される樹脂基材層９の樹脂がドリル加工の際の熱で部
分的に溶融し、スルーホール３の内周に露出する内層回
路１の端面がこの樹脂で被覆される、いわゆるスミアが
発生する。このようにスミアが発生すると、スルーホー
ル３の内周に施すスルーホールメッキ４と内層回路１と
の間の導通がスミアで阻害されて導通信頼性が低下する
ことになる。When the through holes 3 are drilled in the multilayer board 2 as described above, the resin of the resin base material layer 9 composed of the laminated board and the prepreg is partially melted by the heat during the drilling. However, a so-called smear occurs in which the end surface of the inner layer circuit 1 exposed on the inner circumference of the through hole 3 is covered with this resin. When smear occurs in this manner, the conduction between the through hole plating 4 applied to the inner periphery of the through hole 3 and the inner layer circuit 1 is hindered by the smear, and the conduction reliability is lowered.
【０００４】そこで従来から、過マンガン酸カリウム
や、クロム酸カリウム等の強い酸化剤を用いてスルーホ
ール３を処理することによって、図４（ｃ）のようにス
ルーホール３の内周の樹脂を溶解させ、スルーホール３
の内周のスミアを除去するデスミア処理をおこなうよう
にしている。Therefore, conventionally, by treating the through hole 3 with a strong oxidizing agent such as potassium permanganate or potassium chromate, the resin on the inner circumference of the through hole 3 is removed as shown in FIG. 4 (c). Melt and through hole 3
Desmear processing is performed to remove the smear on the inner circumference of the.
【０００５】[0005]
【発明が解決しようとする課題】上記のように過マンガ
ン酸カリウムや、クロム酸カリウム等の強い酸化剤を用
いてスルーホール３の内周の樹脂を溶解させると、図４
（ｃ）のように樹脂基材層９のスルーホール３に面する
部分が後退するように溶解侵食され、樹脂基材層９が劣
化されるおそれがある。そしてこのように樹脂基材層９
が劣化されると微細クラック等が樹脂基材層９に生じ
て、図５に示すようにこのクラックの部分にスルーホー
ルメッキ４のメッキ液がしみ込み（イで示す）、スルー
ホール３間の絶縁抵抗が低下して、電子部品の高密度実
装に対応したスルーホールピッチの縮小化が難しくな
り、信頼性試験においても十分な性能を発揮することが
できなくなるという問題があった。As described above, when the resin on the inner periphery of the through hole 3 is dissolved by using a strong oxidizing agent such as potassium permanganate or potassium chromate, as shown in FIG.
As shown in (c), the portion of the resin base material layer 9 facing the through hole 3 may be dissolved and eroded so as to recede, and the resin base material layer 9 may be deteriorated. Then, in this way, the resin base material layer 9
Is deteriorated, fine cracks and the like are generated in the resin base material layer 9, and the plating solution of the through hole plating 4 permeates into the cracked portion as shown in FIG. There is a problem in that the insulation resistance decreases, making it difficult to reduce the through-hole pitch corresponding to high-density mounting of electronic components, and it becomes impossible to exhibit sufficient performance even in a reliability test.
【０００６】本発明は上記の点に鑑みてなされたもので
あり、スルーホール間の絶縁抵抗を低下させることなく
内層回路とスルーホールメッキとの導通信頼性を高める
ことができるプリント配線板の製造方法を提供すること
を目的とするものである。The present invention has been made in view of the above points, and manufactures a printed wiring board which can improve the reliability of conduction between the inner layer circuit and the through hole plating without lowering the insulation resistance between the through holes. It is intended to provide a method.
【０００７】[0007]
【課題を解決するための手段】本発明に係るプリント配
線板の製造方法は、内層回路１を設けて形成した多層板
２に内層回路１を貫通してスルーホール３を設けると共
にスルーホール３の内周にスルーホールメッキ４を施す
ことによって多層プリント配線板を製造するにあたっ
て、酸と過酸化水素とを含む混合溶液でスルーホール３
を処理することによって内層回路１のスルーホール３の
内周縁部をエッチング処理し、しかる後にスルーホール
３の内周にスルーホールメッキ４を施すことを特徴とす
るものである。In the method for manufacturing a printed wiring board according to the present invention, a through-hole 3 is formed while penetrating the inner layer circuit 1 in a multilayer board 2 formed by forming the inner layer circuit 1. When manufacturing a multilayer printed wiring board by applying through-hole plating 4 on the inner circumference, the through-hole 3 is formed by a mixed solution containing acid and hydrogen peroxide.
The inner peripheral portion of the through hole 3 of the inner layer circuit 1 is subjected to an etching treatment, and then the through hole plating 4 is applied to the inner periphery of the through hole 3.
【０００８】[0008]
【作用】酸と過酸化水素とを含む混合溶液でスルーホー
ル３を処理して内層回路１のスルーホール３の内周縁部
をエッチング処理することによって、内層回路１をエッ
チングする際にこの内層回路１の内周面に付着するスミ
ア樹脂も同時に除去することができ、内層回路１をスル
ーホール３の内周面に露出させるデスミア処理をおこな
うことができる。また酸と過酸化水素とを含む混合溶液
は回路金属を溶解する作用はあるが樹脂を侵食する作用
は小さいので、樹脂基材層９を劣化させることはない。When the through hole 3 is treated with a mixed solution containing an acid and hydrogen peroxide to etch the inner peripheral edge of the through hole 3 of the inner layer circuit 1, the inner layer circuit 1 is etched when the inner layer circuit 1 is etched. The smear resin adhering to the inner peripheral surface of No. 1 can also be removed at the same time, and the desmear process of exposing the inner layer circuit 1 to the inner peripheral surface of the through hole 3 can be performed. Further, the mixed solution containing the acid and hydrogen peroxide has a function of dissolving the circuit metal but a small function of attacking the resin, and therefore does not deteriorate the resin base material layer 9.
【０００９】[0009]
【実施例】以下本発明を実施例によって詳述する。多層
板２は、銅張りエポキシ樹脂積層板や銅張りポリイミド
樹脂積層板など、金属張り積層板をエッチング加工等す
ることによって銅の内層回路１を設けて形成した内層用
回路板を所要枚数プリプレグを介して重ねると共にさら
にその外側にプリプレグを介して銅箔８（あるいは外層
回路板）を重ね、これを加熱加圧して積層成形すること
によって図１（ａ）のように作成したものを用いること
ができる。そして先ず、内層回路１を通るようにドリル
加工をおこなうことによって、図１（ｂ）のように多層
板２を貫通してスルーホール３を設ける。EXAMPLES The present invention will be described in detail below with reference to examples. The multilayer board 2 is a copper-clad epoxy resin laminated board, a copper-clad polyimide resin laminated board, or the like. It is preferable to use the one prepared as shown in FIG. 1A by stacking the copper foil 8 and the copper foil 8 (or the outer layer circuit board) on the outer side of the copper foil 8 via the prepreg and heating and pressurizing the copper foil 8 to form a laminate. it can. Then, first, by drilling so as to pass through the inner layer circuit 1, a through hole 3 is provided so as to penetrate the multilayer plate 2 as shown in FIG.
【００１０】次に、酸と過酸化水素を含む混合溶液でス
ルーホール３の内周を処理する。酸としては硫酸や塩酸
などの酸化性の強くない無機酸を用いることができるも
のであり、酸と過酸化水素の他に、銅イオンを配合した
り、有機溶剤を配合したりすることができる。銅イオン
は硫酸銅等として配合することができるものであり、ま
た有機溶剤としてはブチルセロソルブ等を用いることが
できる。混合溶液において酸や過酸化水素等の配合量は
特に限定されるものではないが、混合溶液の配合量の一
例を示すと、３５％Ｈ2 Ｏ2 を７５．５ｇ／リットル、
Ｈ2 ＳＯ4 を１７１．１ｇ／リットル、銅イオン（Ｃｕ
ＳＯ4 ）を１８．３ｇ／リットル、残を水とするものを
挙げることができる。有機溶剤をさらに配合する場合に
は有機溶剤は５０ｇ／リットル〜２５０ｇ／リットル程
度で配合するのが好ましい。Next, the inner periphery of the through hole 3 is treated with a mixed solution containing acid and hydrogen peroxide. As the acid, an inorganic acid that is not highly oxidative such as sulfuric acid or hydrochloric acid can be used, and in addition to the acid and hydrogen peroxide, copper ions or an organic solvent can be mixed. . The copper ion can be added as copper sulfate or the like, and butyl cellosolve or the like can be used as the organic solvent. The amount of the acid, hydrogen peroxide, etc. in the mixed solution is not particularly limited, but an example of the amount of the mixed solution is 35% H 2 O 2 at 75.5 g / liter,
171.1 g / liter of H 2 SO 4 , copper ions (Cu
SO 4 ), which has 18.3 g / l and the balance water. When an organic solvent is further added, it is preferable to add the organic solvent in an amount of about 50 g / liter to 250 g / liter.
【００１１】酸と過酸化水素を含む混合溶液で多層板２
のスルーホール３を処理するにあたっては、この混合溶
液に多層板２を浸漬したり、スルーホール３にこの混合
溶液をスプレーしたりしておこなうことができる。この
とき外層の銅箔８はレジスト等で保護するようにしても
よい。処理時間は５秒〜１分程度が好ましい。混合溶液
の過酸化水素の割合を多くすると処理時間は短くなる。
そしてこのように酸と過酸化水素を含む混合溶液で多層
板２のスルーホール３を処理すると、スルーホール３の
内周において内層回路１が混合溶液でエッチング作用を
受け、図１（ｃ）に示すように内層回路１のスルーホー
ル３の内周縁部が後退するように溶解される。内層回路
１のスルーホール３の内周縁部がこのように溶解される
と、これに伴って内層回路１のスルーホール３の内周面
に付着しているスミア樹脂も同時にスルーホール３内か
ら除かれることになり、内層回路１をスルーホール３内
に全周に亘って露出させることができる。Multilayer board 2 with a mixed solution containing acid and hydrogen peroxide
The through hole 3 can be treated by immersing the multilayer plate 2 in the mixed solution or spraying the mixed solution on the through hole 3. At this time, the outer layer copper foil 8 may be protected by a resist or the like. The processing time is preferably about 5 seconds to 1 minute. If the proportion of hydrogen peroxide in the mixed solution is increased, the processing time becomes shorter.
When the through hole 3 of the multilayer board 2 is treated with the mixed solution containing the acid and hydrogen peroxide in this way, the inner layer circuit 1 is subjected to the etching action of the mixed solution at the inner periphery of the through hole 3, and as shown in FIG. As shown, the inner peripheral edge of the through hole 3 of the inner layer circuit 1 is melted so as to recede. When the inner peripheral edge portion of the through hole 3 of the inner layer circuit 1 is thus melted, the smear resin attached to the inner peripheral surface of the through hole 3 of the inner layer circuit 1 is also removed from the through hole 3 at the same time. As a result, the inner layer circuit 1 can be exposed in the through hole 3 over the entire circumference.
【００１２】このように本発明では内層回路１をエッチ
ングすることによって付着しているスミア樹脂を除去す
るようにしたものであり、従って多層板２の樹脂基材層
９を侵食させる必要がないものであり、特に酸と過酸化
水素を主成分とする混合溶液はエポキシ樹脂やポリイミ
ド等を腐食する作用が小さく、樹脂基材層９を劣化させ
るようなことがないものである。またスミアの発生がひ
どくてスミア樹脂で内層回路１が完全に覆われている場
合にはエッチングをすることができないので、本発明は
スミアの発生があまりひどくない場合に適用されるもの
である。As described above, according to the present invention, the smear resin adhering to the inner layer circuit 1 is removed by etching the inner layer circuit 1. Therefore, it is not necessary to erode the resin base material layer 9 of the multilayer board 2. In particular, the mixed solution containing acid and hydrogen peroxide as the main components has a small effect of corroding the epoxy resin, polyimide, etc. and does not deteriorate the resin base material layer 9. Further, when the smear is so severe that the inner layer circuit 1 is completely covered with the smear resin, etching cannot be performed. Therefore, the present invention is applied when the smear is not so severe.
【００１３】上記のように酸と過酸化水素を含む混合溶
液で多層板２のスルーホール３を処理してスミアを除去
するデスミア処理をおこなった後に、必要に応じて過硫
安にてソフトエッチングをおこない、そして化学銅メッ
キ等をおこなってスルーホール銅メッキ処理をおこなう
ことにより、図１（ｄ）のようにスルーホール３の内周
面にスルーホールメッキ４を施すものである。このと
き、内層回路１のスルーホール３に面する端面はエッチ
ング処理によってスミアで覆われていず露出しているた
めに、図２に示すようにスルーホールメッキ４と内層回
路１を接続不良のおそれなく導通させることができるも
のである。また多層板２の樹脂基材層９は上記のように
劣化を受けていないので、スルーホールメッキ４を施す
際のしみ込み（イ）も小さくなり、電子部品の高密度実
装に対応したスルーホールピッチの縮小化が容易にな
り、信頼性試験においても十分な性能を発揮させること
ができるものである。ちなみに、図１の本発明の方法で
製造した多層プリント配線板と、図４の従来の方法で製
造した多層プリント配線板について、ＰＣＴ試験（１２
１℃、５００時間の条件）及びＴＨＢ試験（バイアス電
圧５Ｖ、８５℃、８５％ＲＨ、１０００時間の条件）を
して回路間絶縁抵抗を測定したところ、従来の図４の方
法で製造した多層プリント配線板ではともに１×１０10
Ω以上であったが、本発明の図１の方法で製造した多層
プリント配線板ではともに１×１０11Ω以上であった。After the through-hole 3 of the multilayer board 2 is treated with the mixed solution containing the acid and hydrogen peroxide to perform the desmear treatment for removing the smear as described above, the soft etching is performed with ammonium persulfate as required. Then, through-hole copper plating is performed by performing chemical copper plating or the like to perform through-hole plating 4 on the inner peripheral surface of the through-hole 3 as shown in FIG. 1D. At this time, since the end face of the inner layer circuit 1 facing the through hole 3 is not covered with smear by the etching process and is exposed, there is a risk of connection failure between the through hole plating 4 and the inner layer circuit 1 as shown in FIG. It can be conducted without the need for conduction. Further, since the resin base material layer 9 of the multilayer board 2 is not deteriorated as described above, the penetration (a) at the time of applying the through hole plating 4 is reduced, and the through hole corresponding to the high density mounting of electronic parts is provided. The pitch can be easily reduced, and sufficient performance can be exhibited even in the reliability test. By the way, a PCT test (12) was performed on the multilayer printed wiring board manufactured by the method of the present invention in FIG. 1 and the multilayer printed wiring board manufactured by the conventional method in FIG.
When the inter-circuit insulation resistance was measured by conducting a THB test (bias voltage 5V, 85 ° C., 85% RH, 1000 hours) under the condition of 1 ° C. and 500 hours), a multilayer produced by the conventional method of FIG. 1 × 10 10 for both printed wiring boards
Ω or more, but both were 1 × 10 11 Ω or more in the multilayer printed wiring board manufactured by the method of FIG. 1 of the present invention.
【００１４】上記のように多層板２にスルーホールメッ
キ４を施した後に、外層の銅箔８をエッチング加工して
外層回路を設けることによって、多層プリント配線板Ａ
として仕上げることができる。この多層プリント配線板
Ａは例えば、半導体装置のチップキャリアとして用いる
ことができる。図３（ａ）はＰＧＡ型半導体装置を形成
するようにした例を示すものであり、スルーホール３に
外部接続用端子ピン１０を挿着すると共に、多層プリン
ト配線板Ａにキャビティ凹所１１を設けてＩＣチップ等
の半導体チップ１２を実装するようにしたものである。
１３はワイヤーボンディング、１８は半導体チップ１２
を保護するキャップである。図３（ｂ）はＱＦＰ型半導
体装置を形成するようにした例を示すものであり、リー
ドフレーム１４のリード１５をプリント配線板Ａに接続
すると共にキャビティ凹所１１に半導体チップ１２を実
装し、プリント配線板Ａの全体を樹脂成形品１６中に封
止するようにしたものである。図３（ｃ）はＬＣＣ型半
導体装置を形成するようにした例を示すものであり、プ
リント配線板Ａの端縁部にリード１７を設けるようにし
たものである。After the through-hole plating 4 is applied to the multilayer board 2 as described above, the outer layer copper foil 8 is etched to provide an outer layer circuit, whereby the multilayer printed wiring board A is formed.
Can be finished as This multilayer printed wiring board A can be used, for example, as a chip carrier of a semiconductor device. FIG. 3A shows an example in which a PGA type semiconductor device is formed. The external connection terminal pin 10 is inserted into the through hole 3 and the cavity recess 11 is formed in the multilayer printed wiring board A. The semiconductor chip 12 such as an IC chip is provided and mounted.
13 is wire bonding, 18 is a semiconductor chip 12
It is a cap that protects. FIG. 3B shows an example in which a QFP type semiconductor device is formed. The lead 15 of the lead frame 14 is connected to the printed wiring board A, and the semiconductor chip 12 is mounted in the cavity recess 11. The entire printed wiring board A is sealed in a resin molded product 16. FIG. 3C shows an example in which an LCC type semiconductor device is formed, in which leads 17 are provided at the edge portion of the printed wiring board A.
【００１５】[0015]
【発明の効果】上記のように本発明は、酸と過酸化水素
とを含む混合溶液でスルーホールを処理することによっ
て内層回路のスルーホールの内周縁部をエッチング処理
し、しかる後にスルーホールの内周にスルーホールメッ
キを施すようにしたので、内層回路をエッチングする際
にこの内層回路の内周面に付着するスミア樹脂も同時に
除去することができ、内層回路をスルーホールの内周面
に露出させるデスミア処理をおこなうことができるもの
であり、内層回路とスルーホールメッキとの導通信頼性
を高めることができるものである。また酸と過酸化水素
とを含む混合溶液は回路金属を溶解する作用はあるが樹
脂を侵食する作用は小さいので、樹脂基材層を劣化させ
ることはなく、スルーホール間の絶縁抵抗を低下させる
ことがないものである。As described above, according to the present invention, the inner peripheral portion of the through hole of the inner layer circuit is etched by treating the through hole with a mixed solution containing an acid and hydrogen peroxide, and then the through hole is removed. Since through hole plating is applied to the inner circumference, smear resin that adheres to the inner peripheral surface of this inner layer circuit can be removed at the same time when the inner layer circuit is etched, and the inner layer circuit can be applied to the inner peripheral surface of the through hole. The exposed desmear treatment can be performed, and the reliability of conduction between the inner layer circuit and the through hole plating can be improved. Further, the mixed solution containing acid and hydrogen peroxide has a function of dissolving the circuit metal but has a small effect of eroding the resin, so that it does not deteriorate the resin base material layer and lowers the insulation resistance between the through holes. There is no such thing.
【図１】本発明の一実施例を示すものであり、（ａ）乃
至（ｄ）はそれぞれ断面図である。FIG. 1 shows an embodiment of the present invention, in which (a) to (d) are sectional views, respectively.
【図２】同上の一部の拡大した断面図である。FIG. 2 is an enlarged sectional view of a part of the above.
【図３】半導体装置を示すものであり、（ａ）乃至
（ｃ）はそれぞれ断面図である。FIG. 3 illustrates a semiconductor device, in which (a) to (c) are cross-sectional views, respectively.
【図４】従来例の一実施例を示すものであり、（ａ）乃
至（ｄ）はそれぞれ断面図である。FIG. 4 shows an example of a conventional example, and (a) to (d) are cross-sectional views, respectively.
【図５】同上の一部の拡大した断面図である。FIG. 5 is an enlarged sectional view of a part of the above.
１ 内層回路 ２ 多層板 ３ スルーホール ４ スルーホールメッキ 1 Inner layer circuit 2 Multilayer board 3 Through hole 4 Through hole plating
Claims (1)
回路を貫通してスルーホールを設けると共にスルーホー
ルの内周にスルーホールメッキを施すことによって多層
プリント配線板を製造するにあたって、酸と過酸化水素
とを含む混合溶液でスルーホールを処理することによっ
て内層回路のスルーホールの内周縁部をエッチング処理
し、しかる後にスルーホールの内周にスルーホールメッ
キを施すことを特徴とする多層プリント配線板の製造方
法。1. When manufacturing a multilayer printed wiring board by manufacturing a multilayer printed wiring board by forming a through hole through an inner layer circuit in a multilayer board formed by providing an inner layer circuit and performing through hole plating on the inner circumference of the through hole, Multilayer printing characterized by etching the inner peripheral edge of the through hole of the inner layer circuit by treating the through hole with a mixed solution containing hydrogen peroxide, and then performing through hole plating on the inner periphery of the through hole. Wiring board manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4187254A JPH0637455A (en) | 1992-07-15 | 1992-07-15 | Manufacture of multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4187254A JPH0637455A (en) | 1992-07-15 | 1992-07-15 | Manufacture of multilayer printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0637455A true JPH0637455A (en) | 1994-02-10 |
Family
ID=16202756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4187254A Pending JPH0637455A (en) | 1992-07-15 | 1992-07-15 | Manufacture of multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0637455A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103200791A (en) * | 2013-04-25 | 2013-07-10 | 无锡江南计算技术研究所 | High-frequency board-holed plating method of glass cloth reinforced PTFE (Poly Tetra Fluoro Ethylene) material |
| CN109275285A (en) * | 2018-11-16 | 2019-01-25 | 江门崇达电路技术有限公司 | A kind of the via hole method improving Reliability of PCB |
| JP2020057767A (en) * | 2018-09-26 | 2020-04-09 | 京セラ株式会社 | Printed wiring board |
-
1992
- 1992-07-15 JP JP4187254A patent/JPH0637455A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103200791A (en) * | 2013-04-25 | 2013-07-10 | 无锡江南计算技术研究所 | High-frequency board-holed plating method of glass cloth reinforced PTFE (Poly Tetra Fluoro Ethylene) material |
| JP2020057767A (en) * | 2018-09-26 | 2020-04-09 | 京セラ株式会社 | Printed wiring board |
| CN109275285A (en) * | 2018-11-16 | 2019-01-25 | 江门崇达电路技术有限公司 | A kind of the via hole method improving Reliability of PCB |
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| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20001003 |