JPH0637450A - Multilayered thin-film printed-circuit board - Google Patents

Multilayered thin-film printed-circuit board

Info

Publication number
JPH0637450A
JPH0637450A JP19079392A JP19079392A JPH0637450A JP H0637450 A JPH0637450 A JP H0637450A JP 19079392 A JP19079392 A JP 19079392A JP 19079392 A JP19079392 A JP 19079392A JP H0637450 A JPH0637450 A JP H0637450A
Authority
JP
Japan
Prior art keywords
layer
wiring
insulating layer
layers
multilayer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19079392A
Other languages
Japanese (ja)
Other versions
JP3565872B2 (en
Inventor
Osamu Shimada
修 島田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19079392A priority Critical patent/JP3565872B2/en
Publication of JPH0637450A publication Critical patent/JPH0637450A/en
Application granted granted Critical
Publication of JP3565872B2 publication Critical patent/JP3565872B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To provide a multilayered thin-film printed-circuit board capable of reliable connection by forming I/O terminals, each having a non-buffering composite structure of different metal layers and being isolated electrically from the substrate surface. CONSTITUTION:A first interconnection layer 2a, and underlays 3a for I/O terminals 3 are provided on the surface of an insulating substrate 1. The layers 2a and 3a each include a refractory metal layer and an aluminum layer. The entire surface of the substrate, except part of the surface of the individual underlays, is covered with an insulating layer 2d. A protective layer is formed around the inner insulating layer 2d and the underlays 3a, and interconnection layers 2b and 2c and another inner insulating layer 2d are formed to provide a multilayered thin-film interconnection 2. The interconnection layers 2b and 2c are extended to connect the underlay 3a, and a contact layer 3c for an I/O terminal 3 is provided. The uppermost interconnection layer 2c is then covered with a protective insulating layer 2d'. In this manner a reliable, multilayered thin-film printed circuit board is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は薄膜多層配線基板に係
り、さらに詳しくは、マルチチップモジュールやハイブ
リッドICの構成に適する薄膜多層配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film multi-layer wiring board, and more particularly to a thin film multi-layer wiring board suitable for the construction of multichip modules and hybrid ICs.

【0002】[0002]

【従来の技術】近年、電子部品もしくは電子回路の小形
化,高密度化(大容量化)などが図られており、たとえ
ばパッケージ化した半導体装置を、いわゆるプリント基
板に搭載・実装することが広く知られている。しかし、
前記従来の実装手段では、その高密度化(大容量化)な
どに限界あるため、薄膜技術によって製造し得る薄膜多
層配線基板を、実装用の配線基板としたマルチチップモ
ジュールなどの開発が進められている。そして、こうし
た動向に対応して、薄膜多層配線基板の開発も活発に推
進されているのが現状である。
2. Description of the Related Art In recent years, electronic parts or electronic circuits have been miniaturized and increased in density (increased capacity). For example, packaged semiconductor devices are widely mounted and mounted on so-called printed circuit boards. Are known. But,
Since the conventional mounting means is limited in high density (large capacity), development of a multi-chip module etc. using a thin film multilayer wiring board which can be manufactured by thin film technology as a wiring board for mounting has been promoted. ing. In response to these trends, the current situation is that the development of thin film multilayer wiring boards is being actively promoted.

【0003】図3および図4はこのような薄膜多層配線
基板のそれぞれ異なる構成例の要部を断面的に示したも
ので、図3の場合は、表面に絶縁層が設けられている支
持基板1の所定領域面上に、多層配線部2を形成・配置
し、その多層配線部2の最上層の配線層2cを I/O端子形
成領域面間で延ばし I/O端子部3としている。一方、図
4の場合は、同じく表面に絶縁層が設けられている支持
基板1の所定領域面上に、多層配線部2の第1の配線層
(下地層ないし最下層)2aおよび複数個の I/O端子部3
の下地層3aを同じプロセスで形成・配置し、その後の多
層配線部2の形成段階で、つまり第2層以降の配線層2
b,2c…、たとえば配線層2cを前記第1の配線層2aと異
なる金属材料で形成するとき、前記 I/O端子部3の下地
層3a面にビアホールによって電気的に接続させており、
下地層3aが即 I/O端子部3の役割を成す構成を採ってい
る。なお、図3,図4において、3dは配線層2a,2b,2c
…間の層間絶縁層を、2d′は表面保護層をそれぞれ示
す。
FIG. 3 and FIG. 4 are cross-sectional views showing the essential parts of different structural examples of such a thin-film multilayer wiring board. In the case of FIG. 3, a supporting board having an insulating layer on its surface is shown. The multilayer wiring portion 2 is formed and arranged on the surface of the predetermined area 1 and the uppermost wiring layer 2c of the multilayer wiring portion 2 is extended between the I / O terminal forming area surfaces to form the I / O terminal portion 3. On the other hand, in the case of FIG. 4, the first wiring layer (underlayer or bottom layer) 2a of the multilayer wiring part 2 and a plurality of layers are formed on the surface of the predetermined area of the supporting substrate 1 on which the insulating layer is provided. I / O terminal part 3
Underlying layer 3a is formed and arranged in the same process, and at the subsequent stage of forming the multilayer wiring part 2, that is, the wiring layer 2 of the second and subsequent layers.
b, 2c, for example, when the wiring layer 2c is formed of a metal material different from that of the first wiring layer 2a, it is electrically connected to the base layer 3a surface of the I / O terminal portion 3 by a via hole,
The underlying layer 3a immediately plays the role of the I / O terminal section 3. In FIGS. 3 and 4, 3d is the wiring layers 2a, 2b, 2c.
The interlayer insulating layer between 2 and 2d 'is a surface protective layer.

【0004】[0004]

【発明が解決しようとする課題】しかし、前記図3およ
び図4に要部を図示した構成の薄膜多層配線基板の場合
は、次のような不都合な問題が認められる。先ず、図3
に図示した構成では、支持基板1面上の第1の配線層2a
を成す下地層および I/O端子部3、特に I/O端子部3の
形成予定領域は何等保護されないまま、多層配線部2が
形成されることになる。つまり、所要の配線層2a,2b,
2c…などを順次形成するプロセスにおいて、金属層
(膜)や層間絶縁層2dの選択的なエッチングによるパタ
ーンニング時に、前記 I/O端子部3を形成予定領域面の
絶縁層が除去ないし損傷され、絶縁機能が損なわれると
いう問題がある。特に、表面酸化層を有するシリコン板
を支持基板1とした場合、前記表面酸化層の損傷などに
より、各 I/O端子部3間で電気的な短絡を起こし易いと
いう不都合がある。
However, in the case of the thin film multi-layer wiring board having the construction whose essential parts are shown in FIGS. 3 and 4, the following inconvenient problems are recognized. First, FIG.
In the configuration shown in FIG. 1, the first wiring layer 2a on the surface of the supporting substrate 1
The underlying wiring layer and the I / O terminal portion 3, which constitutes the above, and particularly the region where the I / O terminal portion 3 is to be formed is not protected at all, and the multilayer wiring portion 2 is formed. That is, the required wiring layers 2a, 2b,
In the process of sequentially forming 2c, etc., the insulating layer on the surface where the I / O terminal portion 3 is to be formed is removed or damaged during patterning by selective etching of the metal layer (film) or the interlayer insulating layer 2d. However, there is a problem that the insulation function is impaired. In particular, when a silicon plate having a surface oxide layer is used as the supporting substrate 1, there is a disadvantage that an electrical short circuit easily occurs between the I / O terminal portions 3 due to damage of the surface oxide layer.

【0005】また、図4に図示した構成でも、前記図3
の構成の場合と同様の問題がある。たとえば多層配線部
2の形成段階で、 I/O端子部3を成す下地層3aの表面が
損傷され、外部との電気的な接続を行うため、ワイヤボ
ンデングなど行ったときに、十分な接続強度を採り得な
いという問題がある。
Further, even in the configuration shown in FIG.
There is a problem similar to the case of the configuration. For example, the surface of the underlying layer 3a forming the I / O terminal portion 3 is damaged during the formation of the multi-layer wiring portion 2 to make an electrical connection with the outside. There is a problem that the strength cannot be obtained.

【0006】一方、図5に要部の構成を図示したごと
く、多層配線部2の層間絶縁層2dの一部を延設し、この
延設された絶縁層面上に I/O端子部3ないしコンタクト
部を形成・配置することも知られている。しかし、この
構成の場合は、下地層を成す絶縁層が、一般に緩衝剤と
して作用し、 I/O端子部3の機械的な固定性が劣るた
め、外部との信頼性のある電気的な接続を達成し得ない
という問題がある。特に、下地層を成す絶縁層が、ポリ
イミド樹脂など有機物系の場合は、機械的な接続に要す
る力が分散し易いので接続の確実性が損なわれる。
On the other hand, as shown in FIG. 5 which shows the structure of the main part, a part of the interlayer insulating layer 2d of the multilayer wiring part 2 is extended, and the I / O terminal part 3 or It is also known to form and arrange contact portions. However, in the case of this configuration, the insulating layer forming the underlayer generally acts as a buffering agent, and the mechanical fixing property of the I / O terminal portion 3 is poor, so that a reliable electrical connection to the outside is provided. There is a problem that can not be achieved. In particular, when the insulating layer forming the underlayer is made of an organic material such as polyimide resin, the force required for mechanical connection tends to be dispersed, so that the reliability of the connection is impaired.

【0007】本発明は上記した点に鑑みなされたもの
で、信頼性の高い外部との電気的な接続が可能で、たと
えばマルチチップモジュールなどの構成に適する薄膜多
層配線基板の提供を目的とする。
The present invention has been made in view of the above points, and an object of the present invention is to provide a thin film multilayer wiring board which is highly reliable and can be electrically connected to the outside, and which is suitable for a structure such as a multichip module. .

【0008】[0008]

【課題を解決するための手段】本発明に係る薄膜多層配
線基板は、支持基板の主面上に多層配線部および外部と
の電気的接続をなす I/O端子部が形成されて成る薄膜多
層配線基板において、前記 I/O端子部が多層配線部の支
持基板面に隣接する第1の配線層を構成する金属と同種
の金属から成る複数に分離されている下地層、前記各下
地層の周縁部並びに外周辺部の配線パターンが存在しな
い領域面を被覆する第1の配線層と第2の配線層との層
間絶縁層と同種の絶縁体から成る端子部保護層、および
前記多層配線部の第2の配線層以降のいずれかの配線層
を構成する金属と同種の金属から成りその配線層に接続
し、他端が対応する下地層の露出面に接続するコンタク
ト層を具備した構成を成していることを特徴とする。
A thin film multilayer wiring board according to the present invention is a thin film multilayer wiring board in which a multilayer wiring section and an I / O terminal section for electrically connecting to the outside are formed on a main surface of a supporting substrate. In the wiring board, the I / O terminal portion is separated into a plurality of base layers made of the same metal as the metal forming the first wiring layer adjacent to the supporting substrate surface of the multilayer wiring portion, A terminal portion protective layer made of the same kind of insulator as the interlayer insulating layer between the first wiring layer and the second wiring layer, which covers the peripheral surface and the area surface where the wiring pattern does not exist, and the multilayer wiring portion. Of the second wiring layer and subsequent wiring layers, which is made of the same kind of metal as the wiring layer and is connected to the wiring layer, and the other end of which is connected to the exposed surface of the underlying layer. It is characterized by being made.

【0009】[0009]

【作用】本発明によれば、先ず、 I/O端子部が第1の配
線層と同種の金属から成る下地層は、第1の配線層と同
プロセスで同時に形成し得るので、支持基板面に対し確
実に絶縁性を保持するばかりでなく、その下地層周縁部
並びに外周辺部の配線パターンが存在しない領域面が絶
縁層で被覆されている。そして、前記のような構造ない
し形態をなす下地層の露出面に第2の配線層以降のいず
れかの配線層から延ばされてコンタクト層を構成してい
る。つまり、各 I/O端子部は支持基板面に対して所要の
電気的な絶縁性を確保しながら、異種の金属で複層にか
つ緩衝作用受けない形に構成されるとともに、良好な表
面状態を呈しているため、外部電源などに対し信頼性の
高い接続機能を保持・発揮する。
According to the present invention, first, the base layer whose I / O terminal portion is made of the same metal as that of the first wiring layer can be formed simultaneously with the first wiring layer in the same process. On the other hand, not only the insulating property is surely maintained, but also the peripheral surface of the base layer and the area surface where the wiring pattern does not exist are covered with the insulating layer. Then, a contact layer is formed on the exposed surface of the underlayer having the above-described structure or form by extending from any of the wiring layers after the second wiring layer. In other words, each I / O terminal is configured in multiple layers with different kinds of metals and without buffering effect while ensuring the required electrical insulation from the surface of the support substrate, and has a good surface condition. As a result, it retains and demonstrates a highly reliable connection function for external power sources.

【0010】[0010]

【実施例】以下、図1および図2を参照して本発明の一
実施例を説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.

【0011】図1は本発明に係る薄膜多層配線基板の要
部構成例を断面的に示したもので、1は支持基板、たと
えば酸化膜付き(図示せず)のシリコン基板、2は前記
酸化膜付きのシリコン基板1面上に酸化膜(絶縁層)を
介して一体的に形成・配置された多層配線部、3は同じ
く前記酸化膜付きのシリコン基板1の他の領域面上に酸
化膜(絶縁層)を介して一体的に形成・配置された外部
との電気的接続をなすI/O端子部である。そして、前記
I/O端子部3は、多層配線部2の支持基板1面に隣接す
る第1の配線層2aを構成する金属、たとえばTiやCrと同
種の金属から成る複数に分離されている下地層3a、前記
各下地層3aの少なくとも周縁部の一部並びに外周辺部の
配線パターンが存在しない領域の支持基板1面を被覆す
る第1の配線層2aと第2の配線層2bとの層間絶縁層2dと
同種の絶縁体から成る端子部保護層3b、および前記多層
配線部2の第2の配線層2b以降のいずれかの配線層2b,
2c…を構成する金属、たとえばTi-Cu-Ti複合系もしくは
Cr-Cu-Cr複合系と同種の金属から成りその配線層2b,2c
…に接続し、他端が対応する下地層3aの露出面に接続す
るコンタクト層3cで構成されている。
FIG. 1 is a cross-sectional view showing an example of the essential structure of a thin-film multilayer wiring board according to the present invention. The multilayer wiring part 3 formed and arranged integrally on the surface of the silicon substrate 1 with the film via the oxide film (insulating layer) is an oxide film on the surface of the other region of the silicon substrate 1 with the oxide film. It is an I / O terminal portion that is integrally formed and arranged via an (insulating layer) to electrically connect to the outside. And said
The I / O terminal portion 3 is divided into a plurality of base layers 3a made of a metal that constitutes the first wiring layer 2a adjacent to the surface of the supporting substrate 1 of the multilayer wiring portion 2, for example, a metal similar to Ti or Cr. An interlayer insulating layer between the first wiring layer 2a and the second wiring layer 2b, which covers at least a part of the peripheral portion of each of the base layers 3a and the area of the outer peripheral portion where the wiring pattern does not exist A terminal part protection layer 3b made of the same kind of insulator as 2d, and any wiring layer 2b after the second wiring layer 2b of the multilayer wiring part 2;
Metals that compose 2c ..., such as Ti-Cu-Ti composite system or
Wiring layers 2b and 2c made of the same metal as the Cr-Cu-Cr composite system
, And the other end is connected to the exposed surface of the corresponding underlying layer 3a.

【0012】本発明に係る薄膜多層配線基板は、次のよ
うな手段で容易に製造し得る。図2(a) (e)は製造実施
態様例を模式的に示す断面図であり、先ず絶縁性支持基
板(ベース基板)1として、たとえば酸化膜付きのシリ
コン基板を用意する。次いで前記絶縁性支持基板1の主
面上に、第1の金属層(下地層)として、たとえば蒸着
もしくはスパッタリングにより、Ti層やCr層などおよび
Al層を順次被着・形成した後、たとえば酸素ガスおよび
CF4 によるドライエッチングなどでパターンニングし
て、第1の配線層2aおよび所要数の I/O端子部3の下地
層3aを形成する(図2(a))。つまり、第1の配線層2aお
よび I/O端子部3の下地層3aは、高融点の金属層とAl層
(表面層)との複合層で構成されている。その後、前記
第1の配線層2aおよび I/O端子部3の下地層3aを形成し
た面に、層間絶縁層2dとして、たとえばポリイミド樹脂
層を被着・形成する(図2(b))。この層間絶縁層2dの形
成において、各下地層3aの主面の一部を露出させるよう
に周縁部、並びに外周辺部の配線パターンが存在しない
領域も合わせて保護のため被覆する。 前記層間絶縁層
2dおよび下地層3a周辺の保護層を形成してから、第2の
配線層2b,2c…、およびそれら配線層2b,2c…層間の層
間絶縁層2dをいわゆる薄膜技術により順次形成して、所
要の薄膜多層配線部2を形成する(図2(c) 〜(e))。こ
こで、配線層2b,2c…は、たとえばCu層をTi層で挾んだ
構成の複合体、もしくはCu層をCr層で挾んだ構成の複合
体であり、前記の下地層3aまで、いずれかの配線層形成
段階で延設され、下地層3aの露出面に電気的に接続して
コンタクト層3cを設け I/O端子部3を形成する一方、最
上層の配線層(図では2c)の保護用絶縁層2d′を被着・
形成することにより、前記図1に示す構成の薄膜多層配
線基板が得られる。そして、この構成においては、前記
保護用絶縁層2d′面を、電子部品の搭載・実装に利用す
ることも可能である。
The thin film multilayer wiring board according to the present invention can be easily manufactured by the following means. 2 (a) and 2 (e) are cross-sectional views schematically showing an example of a manufacturing embodiment. First, as the insulating support substrate (base substrate) 1, for example, a silicon substrate with an oxide film is prepared. Then, on the main surface of the insulating support substrate 1, as a first metal layer (underlayer), for example, by vapor deposition or sputtering, a Ti layer, a Cr layer, etc.
After sequentially depositing and forming the Al layer, for example, oxygen gas and
Patterning is performed by dry etching with CF 4 or the like to form the first wiring layer 2a and the required number of base layers 3a of the I / O terminal portions 3 (FIG. 2 (a)). That is, the first wiring layer 2a and the underlying layer 3a of the I / O terminal portion 3 are composed of a composite layer of a high melting point metal layer and an Al layer (surface layer). Then, for example, a polyimide resin layer is deposited / formed as an interlayer insulating layer 2d on the surface of the first wiring layer 2a and the underlying layer 3a of the I / O terminal portion 3 (FIG. 2 (b)). In the formation of the interlayer insulating layer 2d, the peripheral portion and the region where the wiring pattern does not exist in the outer peripheral portion are also covered for protection so as to expose a part of the main surface of each base layer 3a. The interlayer insulating layer
After forming the protective layer around 2d and the underlying layer 3a, the second wiring layers 2b, 2c ... And the interlayer insulating layer 2d between these wiring layers 2b, 2c ... The thin film multilayer wiring part 2 is formed (FIGS. 2 (c) to 2 (e)). Here, the wiring layers 2b, 2c ... Are, for example, a composite having a structure in which a Cu layer is sandwiched by a Ti layer, or a composite having a structure in which a Cu layer is sandwiched by a Cr layer. The I / O terminal portion 3 is formed by being extended at any of the wiring layer forming steps and electrically connected to the exposed surface of the underlying layer 3a to form the I / O terminal portion 3, while the uppermost wiring layer (2c in the figure is formed). ) Protective insulating layer 2d '
By forming it, the thin film multilayer wiring board having the structure shown in FIG. 1 is obtained. In this structure, the surface of the protective insulating layer 2d 'can also be used for mounting and mounting electronic components.

【0013】本発明は上記例示に限定されるものでな
く、発明の主旨、換言すると I/O端子部を第1の配線層
の構成と同種の金属の下地層を設け、この下地層の周縁
部並びに外周辺部の配線パターンが存在しない領域面を
層間絶縁層と同種の絶縁体で被覆して端子部保護層を設
けること、および第2の配線層以降のいずれかの配線層
を構成する金属配線層に延長し対応する下地層の露出面
に接続してコンタクト層とすることを具備する範囲で、
たとえば I/O端子部も周辺部および中心部に散在させて
設置してもよい。
The present invention is not limited to the above-mentioned examples, but the gist of the invention, in other words, the I / O terminal portion is provided with an underlayer of the same metal as that of the first wiring layer, and the peripheral edge of this underlayer is provided. Area and outside peripheral area where no wiring pattern is present is covered with an insulating material of the same kind as the interlayer insulating layer to provide a terminal portion protective layer, and any wiring layer after the second wiring layer is formed. To the extent that it extends to the metal wiring layer and connects to the exposed surface of the corresponding underlying layer to form a contact layer,
For example, I / O terminal parts may be scattered and installed in the peripheral part and the central part.

【0014】[0014]

【発明の効果】以上説明したように、本発明に係る薄膜
多層配線基板においては、先ず、 I/O端子部の一部を成
す第1の配線層と同種の金属から成る下地層が、第1の
配線層と同じプロセスで同時に形成されるので、支持基
板面に対し確実に絶縁性を保持するばかりでなく、その
下地層周縁部並びに外周辺部の配線パターンが存在しな
い領域面が絶縁層で被覆されている。そして、前記のよ
うな構造ないし形態を採っている形で、前記下地層の露
出面に第2の配線層以降のいずれかの配線層が延ばされ
てコンタクト層を構成している。つまり、各 I/O端子部
は支持基板面に対して所要の電気的な絶縁性を確保しな
がら、異種の金属で複層にかつ緩衝作用受けない形に構
成されるとともに、良好な表面状態を呈しているため、
外部電源などに対し信頼性の高い接続機能を保持・発揮
する。
As described above, in the thin film multilayer wiring board according to the present invention, first, the underlayer made of the same metal as the first wiring layer forming a part of the I / O terminal portion is Since it is formed simultaneously with the first wiring layer in the same process, not only does it surely maintain the insulating property with respect to the surface of the supporting substrate, but also the peripheral surface of the underlying layer and the area surface where the wiring pattern does not exist are the insulating layer. It is covered with. Then, in the form having the above-described structure or form, one of the wiring layers after the second wiring layer is extended to the exposed surface of the underlayer to form a contact layer. In other words, each I / O terminal is configured in multiple layers with different kinds of metals and without buffering effect while ensuring the required electrical insulation from the surface of the support substrate, and has a good surface condition. Because,
Maintains and demonstrates a highly reliable connection function for external power supplies.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る薄膜多層配線基板の要部構成例を
示す断面図。
FIG. 1 is a sectional view showing a configuration example of a main part of a thin-film multilayer wiring board according to the present invention.

【図2】本発明に係る薄膜多層配線基板を製造する工程
例を模式的に示したもので、(a) は第1層目の配線層お
よび I/O端子部の下地層を形成した状態を示す断面図、
18b) は第1層目の層間絶縁層を形成した状態を示す断
面図、(c) は第2層目の配線層を形成した状態を示す断
面図、(d) は第2層目の層間絶縁層を形成した状態を示
す断面図、(e) はコンタクト層を兼ねる最上層配線層を
形成し、さらに表面保護層を設けた状態を示す断面図。
FIG. 2 schematically shows an example of a process of manufacturing a thin-film multilayer wiring board according to the present invention, in which (a) shows a state in which a first wiring layer and an I / O terminal portion base layer are formed. Cross section showing
18b) is a cross-sectional view showing a state in which a first interlayer insulating layer is formed, (c) is a cross-sectional view showing a state in which a second wiring layer is formed, and (d) is a second layer interlayer. FIG. 6E is a cross-sectional view showing a state in which an insulating layer is formed, and FIG. 6E is a cross-sectional view showing a state in which the uppermost wiring layer also serving as a contact layer is formed and a surface protective layer is further provided.

【図3】従来の薄膜多層配線基板の要部構成例を示す断
面図。
FIG. 3 is a cross-sectional view showing a configuration example of a main part of a conventional thin-film multilayer wiring board.

【図4】従来の薄膜多層配線基板の他の要部構成例を示
す断面図。
FIG. 4 is a cross-sectional view showing another configuration example of the main part of a conventional thin-film multilayer wiring board.

【図5】従来の薄膜多層配線基板のさらに他の要部構成
例を示す断面図。
FIG. 5 is a cross-sectional view showing still another example of the main part configuration of a conventional thin-film multilayer wiring board.

【符号の説明】[Explanation of symbols]

1…絶縁性支持基板 2…多層配線部 2a…最下層
配線層 2b…第2層目の配線層 2c…最上層配線層
2d…層間絶縁層 2d′…表面保護層 3… I/O端子部 3a…下地層 3b…端子保護層
3c…コンタクト層
1 ... Insulating support substrate 2 ... Multilayer wiring part 2a ... Bottom wiring layer 2b ... Second wiring layer 2c ... Top wiring layer
2d ... interlayer insulation layer 2d '... surface protection layer 3 ... I / O terminal part 3a ... base layer 3b ... terminal protection layer
3c ... Contact layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 9355−4M H01L 23/12 Q ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location 9355-4M H01L 23/12 Q

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 支持基板の主面上に多層配線部および外
部との電気的接続をなす I/O端子部が形成されて成る薄
膜多層配線基板において、 前記 I/O端子部が多層配線部の支持基板面に隣接する第
1の配線層を構成する金属と同種の金属から成る複数に
分離されている下地層、 前記各下地層の周縁部並びに外周辺部の配線パターンが
存在しない領域面を被覆する第1の配線層と第2の配線
層との層間絶縁層と同種の絶縁体から成る端子部保護
層、および前記多層配線部の第2の配線層以降のいずれ
かの配線層を構成する金属と同種の金属から成りその配
線層に接続し、他端が対応する下地層の露出面に接続す
るコンタクト層を具備した構成を成していることを特徴
とする薄膜多層配線基板。
1. A thin-film multilayer wiring board comprising a supporting board, a main surface of which a multilayer wiring section and an I / O terminal section for electrical connection with the outside are formed, wherein the I / O terminal section is a multilayer wiring section. A plurality of underlayers made of the same kind of metal as the first wiring layer adjacent to the supporting substrate surface, and a region surface where no wiring pattern exists in the peripheral portion and the outer peripheral portion of each of the underlying layers. A terminal portion protection layer made of an insulating material of the same kind as the interlayer insulating layer between the first wiring layer and the second wiring layer, and any wiring layer after the second wiring layer of the multilayer wiring portion. A thin-film multilayer wiring board comprising a contact layer made of the same kind of metal as the constituent metal and connected to the wiring layer, and the other end being connected to the exposed surface of the corresponding underlying layer.
JP19079392A 1992-07-17 1992-07-17 Thin film multilayer wiring board Expired - Fee Related JP3565872B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19079392A JP3565872B2 (en) 1992-07-17 1992-07-17 Thin film multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19079392A JP3565872B2 (en) 1992-07-17 1992-07-17 Thin film multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH0637450A true JPH0637450A (en) 1994-02-10
JP3565872B2 JP3565872B2 (en) 2004-09-15

Family

ID=16263837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19079392A Expired - Fee Related JP3565872B2 (en) 1992-07-17 1992-07-17 Thin film multilayer wiring board

Country Status (1)

Country Link
JP (1) JP3565872B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100254873B1 (en) * 1997-07-09 2000-05-01 구본준 A liquid crystal display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100254873B1 (en) * 1997-07-09 2000-05-01 구본준 A liquid crystal display

Also Published As

Publication number Publication date
JP3565872B2 (en) 2004-09-15

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