JPH0636454A - Information signal processing device - Google Patents

Abstract

PURPOSE:To reduce a processing amount per unit time and to perform signal processing at low speed by applying sampling to an FM signal by a 2MHz signal, applying frequency modulation to the signal and again applying sampling to the signal by a 4MHz signal. CONSTITUTION:A clock signal with the frequency of 4MHz from a clock generator 104 is divided in frequency by an half into 2MHz by means of a frequency divider 109, an audio input signal is subjected to sampling by the 2 MHz clock signal and then, subjected to modulation processing in a modulation processing block 102. A high frequency component in the re-sampled pulse signal formed by the re-sampling according to the 4MHz clock signal before the frequency division is extracted by means of the signal subjected to modulation processing and sampling and outputted through a filter 112. Thus, a processing amount per unit time is reduced and frequency modulation processing by a low speed arithmetic processing circuit is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information signal processing apparatus, for example, an information signal processing apparatus for performing FM modulation processing on an information signal and then recording the information signal on a recording medium.

[0002]

2. Description of the Related Art Conventionally, as a device for performing FM modulation processing on an information signal and then recording it on a recording medium, after FM modulation processing is performed on an audio signal such as a video tape recorder. , There is an apparatus for recording on a magnetic tape in a state where the FM modulation processing is performed.

FIG. 5 is a diagram showing an example of a schematic configuration of an FM modulator which performs an FM modulation process on an audio signal as a conventional information signal processor.

In FIG. 5, the input audio signal is supplied to an analog / digital (A / D) converter 501, and the A / D converter 501 generates the input audio signal from a clock generator 504. A sampling pulse signal is formed and output by sampling in accordance with a clock signal having a predetermined frequency.

The clock signal generated from the clock generator 504 is also supplied to each section in the modulation processing block 502 indicated by the dotted frame in the figure, and the FM modulation processing to be described later in the modulation processing block 502 is performed. And is converted into an analog signal in the digital / analog (D / A) converter 503 to which the clock signal generated from the clock generator 504 is supplied.
Is output.

The frequency of the clock signal supplied from the clock generator 504 to each circuit block is set so that the frequency band of the FM-modulated audio signal formed by the FM modulator is below the Nyquist frequency. Has been done.

For example, if the carrier frequency of the FM-modulated audio signal is 1.5 MHz and the maximum frequency deviation is ± 100 KHz, as shown in FIG.
It is necessary to set the frequency of the clock signal generated from No. 4 to more than twice the maximum value of the frequency component of the FM-modulated audio signal, so (1.5 MHz + 100 KH
z) × 2 = 3.2 MHz or more, which is 4 MHz with some margin.

The FM modulation processing operation in the modulation processing block 502 of the FM modulator shown in FIG. 5 will be described below.

In FIG. 5, the sample pulse signal "f (t)" output from the A / D converter 501 is multiplied by the coefficient "c1" in the coefficient multiplier 505, so that the sample pulse signal "c1" is obtained. .F (t) ", and the coefficient adder 506 adds the coefficient" c2 "to the sample pulse signal" c2 + c1.f "
(T) ”is output.

The sample pulse signal output from the coefficient adder 506 is integrated by the integrator 507, whereby the sample pulse signal “∫ (c2 + c1)
・ F (t)) dt = c2 ・ t + c1∫f (t) dt "
And is modulated in the sin function circuit 508,
A sample pulse signal “sin (c2 · t + c1 · ∫f (t) dt)” corresponding to the FM-modulated audio signal is obtained and supplied to the D / A converter 503 in the subsequent stage.

[0011]

However, in the configuration of the conventional FM modulator as described above, the clock signal controlling the operation of each unit in the modulation processing block 502 indicated by the dotted frame in FIG. The frequency of is set to more than twice the maximum value of the frequency component of the FM-modulated audio signal, the amount of arithmetic processing per unit time is large, and high-speed arithmetic processing is required. Since it is necessary to configure the device with a circuit, the cost is high, and when the modulation processing block is configured with a digital signal processor or the like, realization of the modulation processing by software becomes very difficult.

Further, as a conventional FM modulator, for example, as shown in FIG. 7, a preprocessing circuit 702 and the like are provided in the preceding stage of a modulation processing block 502, and an A / D converter 701 to which an audio signal is supplied and the above-mentioned. The pre-processing circuit 702 and the frequency output from the clock generator 504 are 4
When the clock signal of MHz is divided by the frequency divider 704 to operate according to the clock signal of which frequency is 40 KHz, the sampling frequency of the sample pulse signal output from the preprocessing circuit 702 is increased. An interpolation filter 703 is provided between the preprocessing circuit 702 and the modulation processing block 704.
However, the frequency of the operation clock signal of the A / D converter 701 and the preprocessing circuit 702 (that is, 40
KHz) and the frequency of the operation clock signal of the modulation processing block 502 (that is, 4 MHz) increase (that is, 1: 100), the circuit scale of the interpolation filter 703 increases and the cost increases. There was also the problem of becoming.

The present invention solves the above-mentioned conventional problems, reduces the amount of arithmetic processing per unit time, and can process information signals with a low-speed arithmetic processing circuit, which simplifies the apparatus and reduces It is an object of the present invention to provide an information signal processing device that can reduce costs.

[0014]

An information signal processing device according to the present invention inputs an information signal and forms sampled data by sampling the input information signal in accordance with a clock signal having a first frequency, The first sampling means for outputting, the signal processing means for subjecting the sample data outputted by the first sampling means to signal processing and outputting the sample data, and the sample data outputted by the signal processing means for the first sampling means. N times the frequency (n is a positive integer)
A second sample for outputting resampled data by resampling according to a clock signal having a second frequency of
It has a sampling means and a filter means for extracting and outputting a high frequency component in the resampled data outputted from the second sampling means.

[0015]

According to the above configuration, the information processing amount per unit time can be reduced, the information signal can be processed by the low-speed arithmetic processing circuit, and the apparatus can be simplified and the cost can be reduced. An object is to provide a signal processing device.

[0016]

EXAMPLES The present invention will be described below with reference to examples of the present invention.

FIG. 1 is a diagram showing a schematic structure of an FM modulator to which the present invention is applied, as an embodiment of the present invention.
In the structure shown in FIG. 1, the same components as those in the structure shown in FIG. 5 are designated by the same reference numerals.

In FIG. 1, a clock signal having a frequency of 4 MHz is generated from a clock generator 104 as in the conventional FM modulator shown in FIG. 5, the generated clock signal is divided into two, and one is D / It is supplied to the D / A converter 103, the switch 110 and the filter circuit 112 as an operation control clock signal of the A converter 103, the switch 110 and the filter circuit 112, and the other frequency is divided by a frequency divider 109 into half. By the frequency of 2
After being set to a clock signal of MHz, it is supplied to the A / D converter 101 as a sampling clock signal of an input audio signal, and in the modulation processing block shown by a dotted frame 102 in the drawing as a modulation processing control clock signal. Is supplied to each part of.

Incidentally, FIG. 2A shows the clock generator 1.
2 is a diagram showing an output waveform of a clock signal having a frequency of 4 MHz, and FIG. 2B is a diagram showing an output waveform of a clock signal having a frequency of 2 MHz output from the frequency divider 109.

In FIG. 1, the frequency output from the frequency divider 109 in the A / D converter 101 is 2 MH.
The sample pulse signal formed by sampling in accordance with the clock signal of z is subjected to FM modulation processing in the modulation processing block 102 at the next stage, and the modulation processing block 102 of this embodiment uses the frequency divider 109 from the frequency divider 109. The sample pulse signal input according to the clock signal whose output frequency is 2 MHz has a carrier frequency of 500 K.
FM modulation processing is performed so that the frequency becomes Hz.

The operation of each part in the modulation processing block 102 is the same as that of the modulation processing block 502 of the conventional FM modulator shown in FIG. 5, and therefore detailed description thereof will be omitted here.

A sample pulse signal that has been subjected to FM modulation processing in the modulation processing block 102 is supplied to one input terminal of the switch 110, and a zero level signal generator 111 generates the other input terminal. A pulse signal indicating a zero level is supplied, the switching operation is controlled in accordance with a clock signal having a frequency of 4 MHz output from the clock generator 104, and the pulse signals supplied to both input terminals are alternated to the next stage. Is output to the filter circuit 112.

FIG. 3 is a diagram showing waveforms of input / output signals in the switch 110. FIG. 3 (a) shows a sampling pulse signal output from the modulation processing block 102 and subjected to FM modulation processing. A waveform is shown in FIG. 3B, where the frequency output from the frequency divider 109 is 2M.
3C shows the waveform of the H clock signal, FIG. 3C shows the waveform of the sample pulse signal output from the switch 110, and FIG. 3D shows the frequency output from the clock generator 104 of 4 MHz. The waveform of the clock signal of is shown.

Therefore, the sample pulse signal output from the switch 110 is the sample pulse signal subjected to FM modulation processing output from the modulation processing block 102 which operates according to the clock signal having a frequency of 2 MHz in the preceding stage. At 110, the frequency is resampled according to the 4 MHz clock signal.

The sample pulse signal output from the switch 110 is supplied to the filter circuit 112 in the subsequent stage, and the filter circuit 112 filters the sample pulse signal according to the clock signal whose frequency output from the clock generator 104 is 4 MHz. .

FIG. 4A is a diagram showing a frequency spectrum below the Nyquist frequency (that is, 2 MHz) in the sample pulse signal supplied from the switch 110 to the filter circuit 112 which operates according to the clock signal having a frequency of 4 MHz. 4A, 401 is an FM-modulated audio signal component having a carrier frequency of 500 KHz, and 402 is a signal component obtained by symmetrically folding the FM-modulated audio signal component 401 at 1 MHz.

Further, FIG. 4B shows the filter circuit 112.
The filter circuit 112 shows a high-pass filter characteristic as shown in the figure, and the filter circuit 112 outputs the FM modulated audio signal component 401 at 1 MHz as shown in FIG. A sample pulse signal of the signal component 402 folded back symmetrically is output.

By the way, paying attention to the frequency spectrum shown in FIG. 4C, this frequency spectrum is the frequency spectrum of the FM-modulated audio signal having the carrier frequency of 1.5 MHz (that is, the FM-modulated audio signal shown in FIG. 6). The sample pulse signal having the frequency spectrum as shown in FIG. 4C output from the filter circuit 112 in this way has a frequency of 4 MHz output from the clock generator 104. The FM is converted into an analog signal by the D / A converter 103 that operates according to the clock signal.
It is output as a modulated audio signal.

Therefore, in this embodiment, an FM equivalent to the FM modulated audio signal obtained by the conventional FM modulator is used.
The modulated audio signal can be obtained by a low-cost modulation processing circuit block which operates with a clock signal having a frequency lower than that of the conventional FM modulator (that is, 2 MHz in the case of this embodiment).

As described above, the FM shown in this embodiment is
In the modulator, an audio signal is input, the input audio signal is sampled in accordance with a clock signal having a frequency of 2 MHz, and a sample pulse signal is formed.
A high frequency component in a resampled pulse signal formed by performing M modulation processing and re-sampling the sample pulse signal subjected to the FM modulation processing according to a clock signal having a frequency of 4 MHz, and outputting the extracted high frequency component. With this configuration, the amount of arithmetic processing per unit time in the FM modulation processing can be reduced, and the audio signal can be subjected to FM modulation processing by the low-speed arithmetic processing circuit, so that the apparatus can be simplified and the cost can be reduced. Will be able to.

[0031]

As described above, according to the present invention, the amount of arithmetic processing per unit time can be reduced and the information signal can be processed by the low-speed arithmetic processing circuit, which simplifies the device and reduces the cost. Therefore, it is possible to provide an information signal processing device that can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention in which F is applied.
It is a figure showing the schematic structure of the M modulator.

FIG. 2 is a diagram showing a waveform of a clock signal in the FM modulator shown in FIG.

FIG. 3 is a diagram showing waveforms of sample pulse signals of respective parts in the FM modulator shown in FIG.

4 is a diagram showing a frequency spectrum of a signal of each unit in the FM modulator shown in FIG.

FIG. 5 is a diagram showing an example of a schematic configuration of an FM modulator that FM-modulates an audio signal as a conventional information signal processing device.

6 is a diagram showing a frequency spectrum of a signal of each part in the conventional FM modulator shown in FIG.

FIG. 7 is a diagram showing a schematic configuration of another FM modulation apparatus that FM-modulates an audio signal as a conventional information signal processing apparatus.

[Explanation of symbols]

 104 clock generator 109 frequency divider 110 switch 111 zero level signal generator 112 filter circuit

Claims (2)

[Claims] 1. A first sampling means for forming and outputting sample data by inputting an information signal and sampling the input information signal according to a clock signal having a first frequency, and the first sampling means. Signal processing means for performing signal processing on the output sample data and outputting the sample data, the sample data output from the signal processing means being n times (n is a positive integer) the first frequency. Second sampling means for outputting resampled data by resampling in accordance with a clock signal having a frequency of 2, and a filter for extracting and outputting a high frequency component in the resampled data output from the second sampling means. An information signal processing device comprising: 2. The information signal is an audio signal,
2. The information signal processing device according to claim 1, wherein the signal processing means performs FM modulation processing on the sample data output from the first sampling means and outputs the result.