JP2517709B2 - Digital signal processor - Google Patents

Description

The present invention relates to a digital signal processing apparatus suitable for use in, for example, pre-emphasis processing, equalization processing, etc. in a VTR.

[Outline of Invention]

The present invention, in a digital signal processing device that performs signal processing to obtain a desired frequency characteristic within a transmission band, influences the aliasing noise in a band up to a frequency close to 1/2 fs of the sampling frequency fs of the transmission signal. In order to ensure that the sampling frequency is fs, sampling is performed (oversampling) at a frequency n times the sampling frequency fs and quantized, and the transmission band is sharply limited by the digital low-pass filter with a cutoff frequency of 1 / 2fs to the sampling frequency fs. After frequency conversion, processing is performed so that the frequency characteristic becomes the desired one, enabling an increase in the number of calculations without increasing the frequency of the clock that requires calculation processing, and enabling more advanced signal processing. is there.

[Conventional technology]

Conventionally, in a system or the like where an analog signal is converted into a digital signal and signal processing is performed for recording or transmission, the theoretical limit that is not affected by aliasing noise, that is, up to near 1/2 of the sampling frequency fs of the transmission signal When it is desired to secure a band, an oversampling method in which sampling is performed using a clock that is n times the sampling frequency fs is usually used.

For example, a case of a digital signal processing device that digitally performs signal processing as oversampling and finally obtains an output signal of a sampling frequency fs will be described with reference to FIG.

For example, an analog video signal is supplied from the input terminal 11 to the pre-filter 12 as an input signal. Pre-filter
In 12, the unnecessary components above the frequency of 1/2 fs in the input signal are removed in an analog manner, and the output of the pre-filter 12 becomes A /
It is supplied to the D converter 13.

Each of the A / D converter 13, the digital signal processing circuit 14, and the digital low-pass filter 15 is supplied with a clock pulse of, for example, twice the frequency of the original sampling clock from the terminal 18, and based on this clock pulse, A / D Each of the D converter 13, the digital signal processing circuit 14, and the digital low-pass filter 15 operates.

Further, each of the digital signal processing circuit 14 and the digital low-pass filter 15 is, for example, a program stored system, and each of the digital signal processing circuit 14 and the digital low-pass filter 15 has a frequency 2f from the terminal 19.
A clock pulse having a frequency higher than s is supplied, and the arithmetic processing is executed in a time-division manner within the oversampling period to perform a predetermined process.

In the A / D converter 13, the analog video signal is
It is sampled at the timing of the clock pulse from 8 and then quantized into a digital video signal. A /
The output of the D converter 13 is supplied to the digital signal processing circuit 14.

In the digital signal processing circuit 14, the video signal is digitally equalized to have a desired frequency characteristic, and the output of the digital signal processing circuit 14 is supplied to the digital low pass filter 15.

The digital low-pass filter 15 has a cutoff frequency of 1/2 fs.
At, the band of the digital video signal is sharply limited, and the output of the digital low-pass filter 15 is supplied to the frequency conversion circuit 16.

A clock pulse of frequency fs is supplied to the frequency conversion circuit 16 from the terminal 20, and frequency conversion is performed at the timing of this clock pulse. That is, when oversampling is performed at twice the frequency, the sampling frequency is set to fs by performing thinning-out processing once every two times in the frequency conversion circuit 16, and the sampling frequency is approximately 1/2 fs. A frequency band is secured and a digital video signal having a desired frequency characteristic is taken out from the output terminal 17.

[Problems to be solved by the invention]

In the above-described conventional digital signal processing device using oversampling, the frequency band up to 1/2 fs is ensured without being affected by aliasing noise. However, at the time of signal processing for obtaining a desired frequency characteristic, sampling is performed by a clock pulse having a frequency that is, for example, twice the original sampling frequency fs.
There was a drawback that the calculation time for signal processing was cut in half. For this reason, if the predetermined arithmetic processing cannot be executed within the arithmetic time, it is necessary to increase the frequency of the clock for the arithmetic processing and use a high-speed arithmetic element.
There arises a problem of high cost.

Therefore, an object of the present invention is to increase the number of possible calculations within the calculation time without increasing the frequency of the clock for the calculation processing even when oversampling is used, thereby enabling more complicated signal processing. Another object is to provide a digital signal processing device.

[Means for solving problems]

According to the present invention, an input signal is supplied through an analog filter, and an oversampling frequency (fos) that is at least twice the sampling frequency (fs) of the transmission signal is used.
A / D converter that performs A / D conversion, a digital low-pass filter that limits the output band of the A / D converter and removes aliasing noise, and a band-limited output of the digital low-pass filter that outputs the sampling frequency of the transmission signal (fs ) And the output of the frequency conversion circuit, the clock pulse of the sampling frequency and the clock pulse of a frequency higher than the oversampling frequency (fos) are supplied, and within the sampling period (1 / fs) And a digital signal processing circuit for performing a digital equalizing process such as ensuction.

[Action]

In the A / D converter 3, the transmission signal is sampled (oversampled) at a frequency of n times the sampling frequency fs to be finally obtained and quantized. The frequency band of the sampled transmission signal is sharply limited, and a band up to a frequency close to 1/2 of the sampling frequency fs is secured without being affected by aliasing noise. This transmission signal is supplied to the frequency conversion circuit 5 and frequency-converted to have the sampling frequency fs, and then supplied to the digital signal processing circuit 6, where the digital signal processing circuit 6 performs arithmetic processing at the sampling cycle 1 / fs. Then, the transmission signal is digitally equalized to obtain a digital signal having a desired frequency characteristic.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention.
As shown in the figure, the pre-filter 2, the A / D converter 3, the digital low-pass filter 4, the frequency conversion circuit 5 and the digital signal processing circuit 6 constitute a digital signal processing device. To obtain a digital output signal having a desired frequency characteristic of.

An input terminal is shown by 1 in FIG. 1, and an analog video signal, for example, is supplied from the input terminal 1 to the pre-filter 2 as an input signal. The pre-filter 2 is
For example, it is an analog low-pass filter for band limitation to prevent the generation of aliasing noise at the time of A / D conversion, and the cutoff frequency is 1/2 of the sampling frequency fs. In the pre-filter 2, as shown in FIG. 2A, the unnecessary component of the frequency of the sampling frequency fs or more in the input signal is removed, and the output that is moderately limited in the frequency band near 1/2 fs produces an output. It is supplied to the A / D converter 3.

Each of the A / D converter 3 and the digital low-pass filter 4 has an oversampling frequency fos (= 2f) which is, for example, twice the original sampling clock from the terminal 8.
The clock pulse of s) is supplied, and each of the A / D converter 3 and the digital low-pass filter 4 operates based on the clock pulse of the frequency fos.

In the A / D converter 3, the analog video signal from the pre-filter 2 is sampled at the timing of the clock pulse from the terminal 8 and then quantized into a digital video signal. As shown in FIG. 2B, the A / D converter 3 supplies an output including a component generated at the time of sampling to the digital low-pass filter 4.

Each of the digital low-pass filter 4 and the digital signal processing circuit 6 is, for example, a program stored system, and each of the digital low-pass filter 4 and the digital signal processing circuit 6 has a clock of a frequency higher than the oversampling frequency fos from the terminal 9. The pulse is supplied, the arithmetic operation is executed in a time division within a predetermined time, and a plurality of processes are performed.

The cut-off frequency of the digital low-pass filter 4 is approximately 1/2 of the sampling frequency fs, and the digital low-pass filter 4 performs arithmetic processing within the oversampling period 1 / fos, as shown in FIG. 2C. The frequency band of the digital video signal is sharply limited to the frequency conversion circuit 5
Is supplied to.

A clock pulse of frequency fs is supplied from a terminal 10 to each of the frequency conversion circuit 5 and the digital signal processing circuit 6. In the frequency conversion circuit 5, frequency conversion is performed at the timing of the clock pulse of the frequency fs from the terminal 10. That is, when the oversampling is performed at the frequency fos which is twice the sampling frequency fs, the frequency conversion circuit 5 performs the thinning-out process once every two times to obtain the sampling frequency fs as shown in FIG. 2D. Converted to a signal. The digital video signal having the sampling frequency fs is supplied to the digital signal processing circuit 6.

The digital signal processing circuit 6 is supplied with a clock pulse of a higher frequency from the terminal 9 by the oversampling frequency fos and a clock pulse of the frequency fs from the terminal 10. In the digital signal processing circuit 6, arithmetic processing is performed within the sampling period 1 / fs, and the video signal is digitally equalized,
For example, in the case of the emphasis processing, the high frequency component of the frequency is emphasized to obtain a desired frequency characteristic. The sampling frequency is set to fs, a frequency band up to about 1/2 fs is secured without being affected by aliasing noise, and a digital video signal having a desired frequency characteristic is taken out from the output terminal 7.

In the embodiment of the present invention, the case where the oversampling frequency fos is twice the sampling frequency fs has been described, but the oversampling frequency fos may be twice or more the sampling frequency fs.

〔The invention's effect〕

In the present invention, the transmission signal is sampled (oversampled) and quantized at a frequency n times the sampling frequency fs that is finally desired in the A / D converter, and is quantized by a digital low-pass filter with a cutoff frequency of 1 / 2fs. The frequency band of the oversampled transmission signal is sharply limited, and a band up to a frequency close to 1/2 of the sampling frequency fs is secured without being affected by aliasing noise. This transmission signal is supplied to the frequency conversion circuit and frequency-converted to have the sampling frequency fs, and then supplied to the digital signal processing circuit, where the digital signal processing circuit performs arithmetic processing within the sampling cycle 1 / fs. The transmission signal is digitally equalized to be a digital signal having a desired frequency characteristic.

Therefore, according to the present invention, the signal processing which is conventionally performed by the arithmetic processing within the oversampling period 1 / n fs can be performed by the arithmetic processing within the sampling period 1 / fs. Therefore, the calculation time is increased, and more complicated signal processing becomes possible. Further, according to the present invention, it is not necessary to increase the frequency of the clock for arithmetic processing and it is not necessary to use a high-speed arithmetic element, so that the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a schematic diagram used for explaining the operation of the embodiment of the present invention, and FIG. 3 is a block diagram used for explaining a conventional digital signal processing device. is there. Description of main symbols in the drawing 1: Input terminal, 2: Pre-filter, 3: A / D converter, 4: Digital low-pass filter, 5: Frequency conversion circuit, 6: Digital signal processing circuit, 7: Output terminal.

Claims (1)

(57) [Claims] 1. An input signal is supplied through an analog filter and a sampling frequency (fs) of the transmission signal is 2
A / D with oversampling frequency (fos) more than double
A / D converter for conversion, a digital low-pass filter for limiting the output band of the A / D converter to remove aliasing noise, and a band-limited output of the digital low-pass filter for sampling frequency of the transmission signal ( fs) and the output of the frequency conversion circuit, and the clock pulse of the sampling frequency and the clock pulse of a frequency higher than the oversampling frequency (fos) are supplied, and the sampling period (1 / fs), and a digital signal processing circuit for performing a digital equalization process such as enthusias.