JPH06350635A - Atm transmission line changeover device - Google Patents

Abstract

PURPOSE:To reduce an abort rate of valid cells in the ATM transmission line changeover device. CONSTITUTION:In the ATM transmission line changeover device selectively switching a 0 system transmission line or a 1 system transmission line, cell header code error control sections 21, 22 detect whether or not there is any code error in a cell header of a 0 system cell and a 1 system cell, provide an output of a 1st code error signal when the code error is in existence in the 0 system cell and an output of a 2nd code error signal when the code error is in existence in the 1 system cell while the code error cannot be corrected. A selector 24 selects any of the 0 system cell, the 1 system cell and an idle cell. A selector section 23 controls the selector 24 based on the 1st and 2nd code error signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an asynchronous transfer mode (AT
M) The present invention relates to a transmission line switching device, and more particularly to a transmission line switching system in an ATM transmission device that transmits an information string in cell units.

[0002]

2. Description of the Related Art Generally, an ATM transmission line switching system of this kind is known, for example, the system described in the 1991-4 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers, 1B-483. JP-A-2-246646,
JP-A-3-71749, JP-A-3-104451
The switching method described in Japanese Patent Application Laid-Open No. 3-128547 is known.

Here, a conventional ATM transmission line switching system will be outlined with reference to FIG.

The 0-system transmission line and the 1-system transmission line are input to the illustrated ATM transmission line switching device, and the 0-system transmission line and the 1-system transmission line are input.
A cell is given from each transmission line (here,
A cell received from the 0-system transmission line is called a 0-system cell, and a cell received from the 1-system transmission line is called a 1-system cell). Synchronization unit 11
CCs 0 and 1 receive cells 0 and 1 respectively.
ITT Recommendation I. After the cells are synchronized according to 432, the 0-system cell and the 1-system cell are transferred to the cell header code error control unit 13
And 14 are given.

In the cell header code error control units 13 and 14, CCITT Recommendation I.S. In accordance with H.432, code error control of the cell header in the 0-system cell and the 1-system cell is performed.

Here, the code error control of the cell header will be described with reference to FIG.

When there is no code error in either the error correction mode or the error correction mode, the cell header code error control unit 13 sets the 0-system cell to the FIFO type memory 1
5 and the cell phase comparison unit 16. Similarly, the cell header code error control unit 14 sets the 1-system cell to the FIFO memory 1
7 and the cell phase comparison unit 16.

When a code error is detected in the error correction mode, the mode shifts to the error detection mode. At this time, when the code error is 1 bit, after correcting the code error of the cell header, the 0-system cell is given to the FIFO type memory 15 and the cell phase comparison unit 16, and the 1-system cell is given to the FIFO type memory 1.
7 and the cell phase comparison unit 16. On the other hand, when the code error is 2 bits or more, the cell is discarded,
The empty cell is given to the FIFO memory 15 and the 17-cell phase comparison unit 16.

When a code error of 1 bit or more is detected in the error detection mode, the cell is discarded and an empty cell is output to the FIFO type memory 15 and the 17-cell phase comparison section 16. If there is no code error, the mode shifts to the error correction mode.

By the above-mentioned code error control, a cell having a code error in the cell header will not be output.

Referring again to FIG. 4, the cell phase comparison unit 16
Then, the phase of the 0-system cell is compared with that of the 1-system cell and the phase difference notification signal is notified to the read control unit 18. In the read control unit 18, the FIFO type memories 15 and 1 are read based on the phase difference notification signal.
A read control signal is applied to 7 to read the cells from the FIFO memories 15 and 17 in the same phase. That is, in the read control unit 18, the FIFO memories 15 and 17 are
The read control of the FIFO memories 15 and 17 is performed so that the cells output from the same are given to the selector 19 in the same phase.

A switching control command or the like is given to the selector control unit 20 from an external control device as required, and thereby the selector control unit 20 gives a selector control signal to the selector 19. The selector 19 switches the system in response to the selector control signal, selects one of the 0-system cell and the 1-system cell, and outputs the selected cell.
As described above, the 0-series cell and the 1-series cell input to the selector 19
Since the system cells have the same phase, this switching control is performed without interruption.

[0013]

By the way, the conventional AT
In the M transmission line switching method, the transmission line is switched according to a switching instruction from the outside regardless of the error detection state of the cell header, and the cell header control unit detects two or more bits in the error correction mode. When a cell header error of 1 bit or more is detected in the mode, the cell is discarded and made an empty cell. Therefore, for example, even if a 2-bit error occurs only in the cell header of the selected transmission line and there is no code error in the cell of the other transmission line, the selector output becomes an empty cell, and as a result, a valid cell is not generated. There is a problem of being discarded.

An object of the present invention is to provide an ATM transmission line switching device in which valid cells are not discarded.

[0015]

According to the present invention, an ATM transmission used in an ATM transmission apparatus having an active transmission path and a standby transmission path to selectively switch the active transmission path and the standby transmission path. Whether or not there is a code error in the cell headers of the active cell and the standby cell, in the path switching device, the cells transmitted through the active transmission path and the standby transmission path are received as the active cell and the standby cell, respectively. If it is not possible to correct the code error by detecting the above, a first code error signal is transmitted when the working cell has a code error, and a second code error occurs when the protection cell has a code error. A first means for transmitting a signal, a second means for generating an empty cell, and a third means for selecting one of the working cell, the spare cell and the empty cell as a selected cell.
And the fourth means for controlling the third means on the basis of the first and second code error signals.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

Referring to FIG. 1, in this embodiment, the same components as those of the ATM transmission line switching apparatus shown in FIG. 4 are designated by the same reference numerals.

As described above, the 0-system cell and the 1-system cell are cell-synchronized by the cell synchronization units 11 and 12, respectively, and are given to the cell header code error control units 21 and 22. Then, the cell header code error control units 21 and 22 perform code error control according to the state transition shown in FIG.

Referring also to FIG. 2, if there is no code error in both the error correction mode and the error detection mode, the cell header code error control unit 21 instructs the FIFO type memory 15 and the cell phase control unit 16. The 0-system cell is sent as it is. Similarly, the cell header code error control unit 2
2 sends the 1-system cell as it is to the FIFO type memory 17 and the cell phase control unit 16.

In the error correction mode, when a code error is detected, the mode shifts to the error detection mode. At this time, if the code error is 1 bit, the code error of the cell header of both the 0-system cell and the 1-system cell is corrected and output to the FIFO memories 15 and 17, respectively, and also output to the cell phase comparison unit 16. On the other hand, if the code error is 2 bits or more, the 0-system cell and the 1-system cell are output to the FIFO type memories 15 and 17 as they are and to the cell phase comparison unit 16.

Similarly, in the error detection mode, 1
Even when a code error of more than one bit is detected, the 0-system cell and the 1-system cell are output to the FIFO memories 15 and 17 as they are and the cell phase comparison unit 1
6 is output. In the error detection mode, when no code error is detected, the error detection mode is changed to the error correction mode.

Further, when a code error of 2 bits or more is detected in the error correction mode and a code error of 1 bit or more is detected in the error detection mode, the cell header code error control units 21 and 22 are respectively the first and the second. The second code error notification signal is given to the selector control unit 23.

The cell phase comparison unit 16 compares the phases of the 0-system cell and the 1-system cell and outputs the phase difference notification signal to the read control unit 18.
Give to. The read control unit 18 controls the reading of the FIFO memories 15 and 17 according to the phase difference notification signal.
As a result, the cells read from the FIFO type memories 15 and 17 are given to the selector 24 as a read 0 system cell and a read 1 system cell in the same phase. An empty cell generation unit 25 is connected to the selector 24, and the empty cell is given from the empty cell generation unit 25 to the selector 24.

As described with reference to FIG. 4, the selector control unit 2
A command such as a switching instruction is given to 3 by an external control device (not shown), and in response to this command, the selector control unit 23 controls the selector 24 to switch 0 system and 1 system. That is, the selector 24 selects 0 system or 1 system.

The selector control unit 23 is supplied with the first and second code error notification signals and the read 0-system cells and 1-system cells.

Here, referring to FIG. 1 and FIG. 3, cells 0, 1 and 2 are sequentially arranged as cells A, B, C, D, E, and 0 system cells.
It is assumed that F, ... Are sent from the 0-system transmission line and the 1-system transmission line (in this example, the 0-system transmission line is the active system transmission line, and the 1-system transmission line is the standby system transmission line). And the selector 24
Suppose that the read 0-system cell is selected. That is, 0
It is assumed that the system transmission path is selected. Since there is no error in the cells A and B in the 0 system cell (FIG. 3A), the selector 24 selects the 0 system cell under the control of the selector control unit 23. In the 0-system cell, assuming that cell C has an error in the cell header, this is represented by cell C ′ (FIG. 3A). At this time, if there is no error in the 1-system cell corresponding to the 0-system cell (FIG. 3B), the selector control unit 23 is provided with the first code error notification signal, and therefore the selector control unit 23.
Controls switching of the selector 24 at the timing of receiving the read 0-system cell and the read 1-system cell assuming that the 0-system cell has an error by the first code error notification signal. That is, the selector 24 is switched and controlled at the timing when the 0-system cell and the read 1-system cell are input to the selector 24. As a result, the selector 24 selects the 1-system cell and outputs it as the selected cell (FIGS. 3C and 3D).

In the example shown in FIG. 3, since the cell D is normal in the 0-system cell, that is, the first first code error notification signal is not transmitted, the selector control section 23 controls the switching of the selector 24. Then, the selector 24 selects the read 0-system cell.

When there is an error in the cell E in the 0-system cell and the 1-system cell (this cell is represented by E '. FIGS. 3A and 3B), the first and second code error notification signals are selected by the selector. It is given to the control unit 23. As a result, the selector control unit 23 determines that there is an error in the 0-system cell and the 1-system cell, and controls the selector 24 to switch so that the selector 24 selects the empty cell generation unit 25 (FIG. 3C). As a result, the selector 24 outputs an empty cell as the selected cell (see FIG. 3).
(D)). Thus, when there is a code error in both the 0-system cell and the 1-system cell, both cells are effectively discarded and an empty cell is output, so that the cell having the code error in the cell header is selected as the selected cell. It is never output.

Since the cell F is normal in the 0-system cell and the 1-system cell (FIGS. 3A and 3B), that is, the selector control unit 23 does not receive the first and second code error notification signals. Therefore, the selector 24 selects the read 0-system cell and outputs it as the selected cell under the control of the selector control unit 23 (FIGS. 3C and 3D).

[0030]

As described above, according to the present invention, the active system transmission line and the standby system transmission line are selectively switched based on the cell header code error detection result in the active system cell and the standby system cell, and the empty cell is removed. Since I tried to output it,
There is an effect that the cell discard rate can be reduced without outputting a cell having an error in the cell header. That is, valid cells are never discarded.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an ATM transmission line switching device according to the present invention.

2 is a diagram showing a state transition of a cell header code error control unit used in the ATM transmission line switching apparatus shown in FIG.

FIG. 3 is a time chart for explaining a switching operation of the ATM transmission line switching device shown in FIG.

FIG. 4 is a block diagram showing an example of a conventional ATM transmission line switching device.

5 is a diagram showing a state transition of a cell header code error control unit used in the ATM transmission line switching device shown in FIG.

[Explanation of symbols]

 11, 12 Cell synchronization unit 13, 14, 21, 22 Cell header code error control unit 15, 17 FIFO type memory 16 Cell phase comparison unit 18 Read control unit 19, 24 Selector 20, 23 Selector control unit 25 Empty cell generation unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04L 1/22 4101-5K

Claims (2)

[Claims] 1. An ATM transmission line switching device used in an ATM transmission device having an active transmission line and a standby transmission line to selectively switch the active transmission line and the standby transmission line, wherein the active transmission line is And receiving the cells transmitted on the protection transmission path as working cells and protection cells, respectively, and detecting whether or not there is a code error in the cell headers of the working cell and the protection cell and correcting the code error. If it is not possible, first means for sending a first code error signal when there is a code error in the working cell and for sending a second code error signal when there is a code error in the spare cell, Second means for generating an empty cell; third means for selecting one of the working cell, the spare cell, and the empty cell as a selected cell; and the first and second codes. Based on error signal An ATM transmission path switching device comprising: a fourth means for controlling the third means based on the above. 2. The ATM transmission line switching device according to claim 1, wherein the fourth means is the first and the second.
If no code error signal is received, the third means is controlled to send the active cell as the selected cell,
Receiving the code error signal, the spare cell is selected and sent as the selected cell, and the empty cell is sent as the selected cell when the first and second code error signals are received. An ATM transmission line switching device characterized in that