JPH06350065A - Solid-state image pickup device and its manufacture - Google Patents

Solid-state image pickup device and its manufacture

Info

Publication number
JPH06350065A
JPH06350065A JP5133761A JP13376193A JPH06350065A JP H06350065 A JPH06350065 A JP H06350065A JP 5133761 A JP5133761 A JP 5133761A JP 13376193 A JP13376193 A JP 13376193A JP H06350065 A JPH06350065 A JP H06350065A
Authority
JP
Japan
Prior art keywords
transfer
film
electrode wiring
solid
transfer electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5133761A
Other languages
Japanese (ja)
Other versions
JP2531435B2 (en
Inventor
Satoshi Uchiya
聡 打矢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5133761A priority Critical patent/JP2531435B2/en
Publication of JPH06350065A publication Critical patent/JPH06350065A/en
Application granted granted Critical
Publication of JP2531435B2 publication Critical patent/JP2531435B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To improve a converging factor by a lens array and to raise sensitivity by thinning a polycrystalline silicon film at a part having an influence on the shape of a shading film, concerning to a solid-state image sensing device with a lens array. CONSTITUTION:Only at a wiring part (transfer electrode wires 10A and 15A) where the value of resistance becomes an imprortant factor, a polycrystalline silicon film part is thickened by doubling polycrystalline silicon films, and a part having an influence on the shape of a shading film on a charge transfer part (transfer gate electrodes 8-1A and 8-2A) is thinned by leaving only the second one out of the two layers of the polycrystalline silicon films.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、固体撮像装置及びその
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and a method for manufacturing the same.

【0002】[0002]

【従来の技術】固体撮像装置は光電変換部において光電
変換され、蓄積された電荷を一定期間ごとに電荷転送レ
ジスタ部に読みだし、それを順次出力部に転送し、出力
部で電気信号に変換して外部に出力する装置である。
2. Description of the Related Art In a solid-state image pickup device, photoelectric conversion is performed in a photoelectric conversion unit, and accumulated charges are read out to a charge transfer register unit at regular intervals, which are sequentially transferred to an output unit and converted into an electric signal at the output unit. It is a device for outputting to the outside.

【0003】図6は従来の2次元CCD型の固体撮像装
置の平面図、図7(a)は図6のA−A線断面図、図7
(b)は図6のB−B線断面図である。
FIG. 6 is a plan view of a conventional two-dimensional CCD type solid-state image pickup device, and FIG. 7A is a sectional view taken along line AA of FIG.
(B) is a BB line sectional view of FIG.

【0004】この従来例について、その製造工程に沿っ
て説明する。
This conventional example will be described along with its manufacturing process.

【0005】まず、N型シリコン基板1の表面部に選択
的にP型ウェル層2を形成する。続いて光電変換部のN
型拡散層3、電荷転送部のN型埋込チャネル4、電荷読
出部のP型拡散層5及び素子分離部のチャネルストッパ
6をそれぞれリソグラフィ技術及びイオン注入技術を用
いて形成する。
First, the P-type well layer 2 is selectively formed on the surface of the N-type silicon substrate 1. Next, N of the photoelectric conversion unit
The type diffusion layer 3, the N-type buried channel 4 of the charge transfer portion, the P-type diffusion layer 5 of the charge reading portion, and the channel stopper 6 of the element isolation portion are formed by using the lithography technique and the ion implantation technique, respectively.

【0006】次に、基板表面を熱酸化し、第1のゲート
絶縁膜7を形成し、その上部に減圧CVD法により、多
結晶シリコン膜を400nm堆積し、これをフォトリソ
グラフィ技術及びドライエッチング法を適用して、転送
ゲート電極8−1および転送電極配線15を形成する。
Next, the surface of the substrate is thermally oxidized to form a first gate insulating film 7, and a 400 nm thick polycrystalline silicon film is deposited on the first gate insulating film 7 by a low pressure CVD method, which is then subjected to a photolithography technique and a dry etching method. Is applied to form the transfer gate electrode 8-1 and the transfer electrode wiring 15.

【0007】次に、転送ゲート電極8−1及び転送ゲー
ト電極配線15をマスクとして第1のゲート絶縁膜7を
エッチング除去し、新たに熱酸化を行って第2のゲート
絶縁膜9を形成した後、再び多結晶シリコン膜を400
nm堆積し、パターニングして転送ゲート電極8−2お
よび転送電極配線10を形成する。
Next, the first gate insulating film 7 is removed by etching using the transfer gate electrode 8-1 and the transfer gate electrode wiring 15 as a mask, and new thermal oxidation is performed to form a second gate insulating film 9. After that, the polycrystalline silicon film is again 400
Then, the transfer gate electrode 8-2 and the transfer electrode wiring 10 are formed.

【0008】さらに、層間絶縁膜11を形成した後、転
送電極配線10,15の端部上にコンタクトホール(図
示せず)を開口し、アルミニウム膜をスパッタ法を用い
て蒸着し、N型拡散層3上部に開口17を有する遮光膜
12および転送電極配線10,15にそれぞれ転送パル
スを供給する金属膜配線(図示せず)を形成する。
Further, after the interlayer insulating film 11 is formed, contact holes (not shown) are opened on the ends of the transfer electrode wirings 10 and 15, and an aluminum film is vapor-deposited by the sputtering method, and N-type diffusion is performed. Metal film wirings (not shown) for supplying transfer pulses are formed on the light shielding film 12 having the opening 17 and the transfer electrode wirings 10 and 15 on the layer 3 respectively.

【0009】最後に、透明高分子樹脂をスピンコート法
により塗布し、熱硬化させることにより平坦化層13を
形成した後、感光性高分子樹脂を同じくスピンコート法
により塗布し、フォトリソグラフィ技術を用いてパター
ニングし、熱処理することで軟化させ、マイクロレンズ
14を形成する。
Finally, a transparent polymer resin is applied by a spin coating method and is thermally cured to form a planarizing layer 13, and then a photosensitive polymer resin is also applied by a spin coating method. The microlenses 14 are formed by patterning using the same, and softening by heat treatment.

【0010】[0010]

【発明が解決しようとする課題】上述した従来の固体撮
像装置では電荷転送部に光が漏れ込む現象であるスミア
を低減するために遮光膜12が転送ゲート電極及び電送
電極配線を完全に覆うように形成されている。各画素列
の対応する転送ゲート電極は行方向に転送電極配線によ
り接続されているので、これらの転送電極配線へ転送パ
ルスを供給する金属膜配線から離れているチップ中央付
近で転送パルスになまりが生じ、電気的特性劣化が生じ
るのを防ぐため、多結晶シリコン膜の厚さはあまり薄く
できない。例えば、受光サイズ1/2インチ、画素数4
0万個程度の固体撮像装置においては、転送パルスがな
まらないための転送電極配線の層抵抗として40Ω/□
程度が限界であり、これを実現するには400nm程度
の多結晶シリコン膜が必要となる。
In the conventional solid-state image pickup device described above, the light-shielding film 12 completely covers the transfer gate electrode and the transfer electrode wiring in order to reduce smear, which is a phenomenon in which light leaks into the charge transfer portion. Is formed in. Since the corresponding transfer gate electrodes of each pixel column are connected in the row direction by the transfer electrode wiring, the transfer pulse is rounded near the center of the chip away from the metal film wiring supplying the transfer pulse to these transfer electrode wirings. The thickness of the polycrystalline silicon film cannot be made very thin in order to prevent the occurrence of electrical characteristics deterioration. For example, light receiving size 1/2 inch, number of pixels 4
In the solid state image pickup device of about 0,000, the layer resistance of the transfer electrode wiring is 40 Ω / □ to prevent the transfer pulse from becoming blunt.
However, a polycrystalline silicon film having a thickness of about 400 nm is required to realize this.

【0011】しかしながら、転送ゲート電極8−2がN
型拡散層3の上方へ張り出しているので、400nm程
度の厚さであってもその段差部で被覆形状が悪くなり、
図8に示す従来の固体撮像装置における集光状態を示す
断面図のようにマイクロレンズアレイを用いても完全に
遮光開口部に光が集光できなく、マイクロレンズで屈折
した光の一部が遮光膜12で反射もしくは吸収してしま
うため、感度が低くなっているという問題があった。
However, the transfer gate electrode 8-2 is N
Since it projects above the mold diffusion layer 3, even if the thickness is about 400 nm, the covering shape becomes poor at the step portion,
Even if a microlens array is used as shown in the cross-sectional view of the conventional solid-state imaging device shown in FIG. 8, the light cannot be completely focused on the light-shielding opening, and a part of the light refracted by the microlens is partially reflected. Since it is reflected or absorbed by the light shielding film 12, there is a problem that the sensitivity is low.

【0012】[0012]

【課題を解決するための手段】本発明の固体撮像装置
は、複数の光電変換素子からなる光電変換素子列および
前記光電変換素子毎に複数の転送ゲート電極を設けてな
る垂直転送レジスタからなる画素列を複数並列して集積
した半導体チップを層間絶縁膜を介して被覆し、前記光
電変換素子の上部にそれぞれ開口を有する遮光膜を有す
る固体撮像装置において、前記各画素列の対応する転送
ゲート電極を行方向に接続する転送電極配線が前記転送
ゲート電極と同一材質でより厚く形成されているという
ものである。
A solid-state image pickup device according to the present invention is a pixel including a photoelectric conversion element array including a plurality of photoelectric conversion elements and a vertical transfer register including a plurality of transfer gate electrodes for each photoelectric conversion element. In a solid-state imaging device having a plurality of columns integrated in parallel and covering a semiconductor chip via an interlayer insulating film and having a light-shielding film having an opening above each photoelectric conversion element, a transfer gate electrode corresponding to each pixel column is provided. The transfer electrode wiring for connecting in the row direction is made of the same material as the transfer gate electrode and is thicker.

【0013】また、本発明の固体撮像装置の製造方法
は、半導体基板表面の所定領域にゲート絶縁膜を形成
し、前記ゲート絶縁膜を第1の導電性膜で被覆しパター
ニングして第1の転送電極配線層を形成する工程と、前
記第1の導電性膜と同一材質の第2の導電性膜を全面に
堆積しパターニングすることにより、前記第1の転送電
極配線層に積層されてともに転送電極配線を構成する第
2の転送電極配線層および前記第2の転送電極配線層か
ら列方向に張り出した転送ゲート電極を形成する工程
と、しかる後に層間絶縁膜を堆積し、所定領域に開口を
有する遮光膜を形成する工程とを有するというものであ
る。
According to the method of manufacturing a solid-state image pickup device of the present invention, a gate insulating film is formed in a predetermined region on the surface of a semiconductor substrate, and the gate insulating film is covered with a first conductive film and patterned to form a first conductive film. The step of forming the transfer electrode wiring layer and the step of depositing the second conductive film of the same material as the first conductive film on the entire surface and patterning the second conductive film are laminated on the first transfer electrode wiring layer. A step of forming a second transfer electrode wiring layer that constitutes the transfer electrode wiring and a transfer gate electrode protruding in the column direction from the second transfer electrode wiring layer, and then depositing an interlayer insulating film and opening in a predetermined region And a step of forming a light-shielding film having

【0014】[0014]

【実施例】図1は本発明の一実施例のCCD型の固体撮
像装置を示す平面図、図2(a)は図1のA−A線断面
図、図2(b)は図1のB−B線断面図である。
1 is a plan view showing a CCD type solid-state image pickup device according to an embodiment of the present invention, FIG. 2A is a sectional view taken along the line A--A of FIG. 1, and FIG. It is a BB line sectional view.

【0015】N型シリコン基板1の表面部にP型ウェル
層2が選択的に形成されている。P型ウェル層2の表面
部に選択的にN型埋込チャネル4が形成されている。N
型埋込チャネル層4と平行してフォトダイオードのN型
拡散層3が列状に配置されている。N型拡散層3とN型
埋込みチャネル4との間には電荷読出部のP型拡散層5
が形成されている。6はN型拡散層3,N型埋込チャネ
ル4等を絶縁分離するP+ 型のチャネルストッパであ
る。
A P-type well layer 2 is selectively formed on the surface of the N-type silicon substrate 1. An N-type buried channel 4 is selectively formed on the surface of the P-type well layer 2. N
N-type diffusion layers 3 of the photodiode are arranged in a row in parallel with the buried channel layer 4. Between the N-type diffusion layer 3 and the N-type buried channel 4, a P-type diffusion layer 5 of the charge reading section is provided.
Are formed. Reference numeral 6 is a P + type channel stopper for insulatingly separating the N type diffusion layer 3, the N type buried channel 4 and the like.

【0016】N型埋込チャネル4上には第1のゲート酸
化膜7を介して転送ゲート電極8−1Aが各N型拡散層
3に対応して一つ宛設けられ、各画素列の転送ゲート電
極8−1Aは行方向に転送電極配線15Aにより相互に
連結されている。転送電極配線15Aは約400nmの
厚さの多結晶シリコンで構成され、転送ゲート電極8−
1Aは約150nmの厚さの多結晶シリコン膜で構成さ
れている。同様に、N型埋込チャネル4上にはまた第2
のゲート酸化膜9を介して転送ゲート電極8−2A(厚
さ約150nmの多結晶シリコン膜)が各N型拡散層3
に対応して一つ宛形成され、各画素列の転送ゲート電極
8−2Aは行方向に転送電極配線10A(厚さ約400
nmの多結晶シリコン膜)により相互に連結されてい
る。図6に示した従来例との相違点は転送電極配線の厚
さが転送ゲート電極より厚くなっていることである。
One transfer gate electrode 8-1A is provided on the N-type buried channel 4 via the first gate oxide film 7 so as to correspond to each N-type diffusion layer 3, and transfer of each pixel column is performed. The gate electrodes 8-1A are interconnected in the row direction by transfer electrode wirings 15A. The transfer electrode wiring 15A is made of polycrystalline silicon having a thickness of about 400 nm, and the transfer gate electrode 8-
1A is composed of a polycrystalline silicon film having a thickness of about 150 nm. Similarly, on the N-type buried channel 4, there is also a second
The transfer gate electrode 8-2A (a polycrystalline silicon film having a thickness of about 150 nm) is formed on each N-type diffusion layer 3 through the gate oxide film 9 of
One transfer gate electrode 8-2A of each pixel column is formed corresponding to the transfer electrode wiring 10A (thickness of about 400) in the row direction.
nm polycrystalline silicon film). The difference from the conventional example shown in FIG. 6 is that the transfer electrode wiring is thicker than the transfer gate electrode.

【0017】次に、この実施例の製造方法について説明
する。
Next, the manufacturing method of this embodiment will be described.

【0018】まず、図3(a)に示すように、N型シリ
コン基板1の表面部に選択的にP型ウェル層2を形成す
る。続いて図3(b)に示すように、光電変換部のN型
拡散層(図2(b)の3)、電荷転送部のN型埋込チャ
ネル4、電荷読出部のP型拡散層(図2(b)の5)及
び素子分離用のチャネルストッパ(図2(b)の6)を
それぞれ形成する。
First, as shown in FIG. 3A, the P-type well layer 2 is selectively formed on the surface of the N-type silicon substrate 1. Subsequently, as shown in FIG. 3B, the N-type diffusion layer of the photoelectric conversion unit (3 in FIG. 2B), the N-type buried channel 4 of the charge transfer unit, and the P-type diffusion layer of the charge reading unit ( 2) of FIG. 2B and a channel stopper (6 of FIG. 2B) for element isolation are formed.

【0019】次に、基板表面を熱酸化し、図3(c)に
示すように、第1のゲート酸化膜7を形成し、その上部
に減圧CVD法により、多結晶シリコン膜を250nm
堆積し、これをフォトリソグラフィ技術及びウェットエ
ッチング法を適用して、転送ゲート電極8−1Aを行方
向に接続する転送電極配線を形成するため第1の転送電
極配線層15aを形成する。
Next, the surface of the substrate is thermally oxidized to form a first gate oxide film 7 as shown in FIG. 3C, and a polycrystalline silicon film of 250 nm is formed on the first gate oxide film 7 by a low pressure CVD method.
The first transfer electrode wiring layer 15a is formed by depositing and applying the photolithography technique and the wet etching method to form the transfer electrode wiring that connects the transfer gate electrodes 8-1A in the row direction.

【0020】続いて、減圧CVD法により、図3(d)
に示すように、再度多結晶シリコン膜16を150nm
堆積する。これをフォトリソグラフィ技術及びドライエ
ッチング法を適用して、図4(a)に示すように、第1
の転送電極配線層15aを被覆する第2の転送電極配線
層15bと列方向に長方形状に張り出した転送ゲート電
極8−1Aとを形成する。次に、図4(b)に示すよう
に、2層膜構成の転送電極配線15Aおよび転送ゲート
電極8−1Aをマスクとして第1のゲート酸化膜7をエ
ッチング除去し、新たに熱酸化を行って第2のゲート酸
化膜9を形成した後、第1の多結晶シリコン電極(15
A,8−1A)を形成したのと同様の2段階で形成する
手法を用いて、光電変換部(3)から電荷転送部(4)
への信号電荷の読出及び電荷転送を行うための第2の多
結晶シリコン電極(転送ゲート電極8−2Aおよび転送
電極配線10A)を形成する。
Subsequently, by the low pressure CVD method, as shown in FIG.
As shown in FIG.
accumulate. By applying a photolithography technique and a dry etching method to this, as shown in FIG.
The second transfer electrode wiring layer 15b covering the transfer electrode wiring layer 15a and the transfer gate electrode 8-1A protruding in a rectangular shape in the column direction are formed. Next, as shown in FIG. 4B, the first gate oxide film 7 is removed by etching using the transfer electrode wiring 15A having a two-layer film structure and the transfer gate electrode 8-1A as a mask, and new thermal oxidation is performed. After the second gate oxide film 9 is formed by the above, the first polycrystalline silicon electrode (15
A, 8-1A) is formed in the same two steps as in the photoelectric conversion section (3) to the charge transfer section (4).
A second polycrystalline silicon electrode (transfer gate electrode 8-2A and transfer electrode wiring 10A) for reading and transferring signal charges to and from is formed.

【0021】さらに、図2に示すように、層間絶縁膜1
1を形成した後、転送電極配線10A,15Aの端部上
にコンタクトホール(図示せず)を開口し、たとえばア
ルミニウム膜等をスパッタ法を用いて350nm蒸着
し、フォトリソグラフィ技術及びドライエッチング法を
適用して遮光膜12と転送電極配線10A,15Aにそ
れぞれ転送パルスを供給する金属膜配線(図示せず)を
形成する。
Further, as shown in FIG. 2, the interlayer insulating film 1
1 is formed, a contact hole (not shown) is opened on the end portions of the transfer electrode wirings 10A and 15A, and an aluminum film or the like is deposited to a thickness of 350 nm by a sputtering method, followed by photolithography and dry etching. By applying it, metal film wirings (not shown) for supplying transfer pulses are formed to the light shielding film 12 and the transfer electrode wirings 10A and 15A, respectively.

【0022】最後に、透明高分子樹脂をスピンコート法
により塗布し、熱硬化させることにより平坦化層13を
形成し、感光性高分子樹脂を同じくスピンコート法によ
り塗布し、フォトリソグラフィ技術を用いてパターニン
グし、熱処理することで軟化させ、マイクロレンズ14
を形成することにより、本発明の固体撮像装置が得られ
る。
Finally, a transparent polymer resin is applied by a spin coating method and thermally cured to form a flattening layer 13, and a photosensitive polymer resin is also applied by a spin coating method, and a photolithography technique is used. Patterning and heat treatment to soften the micro lens 14
By forming the, the solid-state imaging device of the present invention is obtained.

【0023】転送電極配線10A,15Aを厚くして転
送パルスのなまりを防止しても、N型拡散層3上へ張り
出している転送ゲート電極8−2Aの厚さは薄くできる
ので、遮光膜12の開口17近傍での段差が小さくな
り、図5に示すように、マイクロレンズ14により集束
された光が遮光膜12の端部に当って反射されるのを防
止できる。つまり、集光可能角度θ1 は従来例における
θ2 より大きくできる。
Even if the transfer electrode wirings 10A and 15A are thickened to prevent the transfer pulse from being blunted, the thickness of the transfer gate electrode 8-2A protruding onto the N-type diffusion layer 3 can be reduced, so that the light shielding film 12 is formed. The step difference in the vicinity of the opening 17 becomes small, and as shown in FIG. 5, it is possible to prevent the light focused by the microlens 14 from hitting the end portion of the light shielding film 12 and being reflected. That is, the converging angle θ 1 can be made larger than θ 2 in the conventional example.

【0024】[0024]

【発明の効果】以上説明したように、本発明によれば転
送電極配線より転送ゲート電極の厚さを小さくすること
ができるので、転送パルスのなまりを防ぎかつ集光量を
増加させることができるので固体撮像装置の感度を一層
改善できる効果がある。
As described above, according to the present invention, since the thickness of the transfer gate electrode can be made smaller than that of the transfer electrode wiring, it is possible to prevent the transfer pulse from blunting and increase the amount of light collected. This has the effect of further improving the sensitivity of the solid-state imaging device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.

【図2】図1のA−A線断面図(図2(a))およびB
−B線断面図(図2(b))である。
2 is a sectional view taken along the line AA of FIG. 1 (FIG. 2A) and B.
It is a B-line sectional view (FIG.2 (b)).

【図3】前述の一実施例の製造方法の説明のため(a)
〜(d)に分図して示す工程断面図である。
FIG. 3 (a) for explaining the manufacturing method of the above-described embodiment.
5A to 5D are process sectional views divided into FIGS.

【図4】図3に対応する工程の次工程の説明のため
(a),(b)に分図して示す工程順断面図である。
4A to 4C are cross-sectional views in order of the processes, illustrated in FIGS. 4A and 4B for explaining the process subsequent to the process corresponding to FIG.

【図5】前述の一実施例による集光量の改善を説明する
ための模式図である。
FIG. 5 is a schematic diagram for explaining the improvement of the amount of collected light according to the above-described embodiment.

【図6】従来例を示す平面図である。FIG. 6 is a plan view showing a conventional example.

【図7】図6のA−A線断面図(図7(a))およびB
−B線断面図(図7(b))である。
7 is a sectional view taken along line AA of FIG. 6 (FIG. 7A) and B.
FIG. 9 is a cross-sectional view taken along line B (FIG. 7B).

【図8】従来例の問題点の説明のための模式図である。FIG. 8 is a schematic diagram for explaining problems of the conventional example.

【符号の説明】[Explanation of symbols]

1 N型シリコン基板 2 P型ウェル層 3 N型拡散層 4 N型埋込チャネル 5 P型拡散層 6 チャネルストッパ 7 第1のゲート酸化膜 8−1,8−1A 第1の多結晶シリコン電極(転送
ゲート電極) 8−2,8−2A 第2の多結晶シリコン電極(転送
ゲート電極) 9 第2のゲート酸化膜 10,10A 転送電極配線 11 層間絶縁膜 12 遮光膜 13 平坦化層 14 マイクロレンズ 15,15A 転送電極配線 16 多結晶シリコン膜 17 開口
1 N-type silicon substrate 2 P-type well layer 3 N-type diffusion layer 4 N-type buried channel 5 P-type diffusion layer 6 Channel stopper 7 First gate oxide film 8-1, 8-1A First polycrystalline silicon electrode (Transfer gate electrode) 8-2, 8-2A Second polycrystalline silicon electrode (transfer gate electrode) 9 Second gate oxide film 10, 10A Transfer electrode wiring 11 Interlayer insulating film 12 Light shielding film 13 Flattening layer 14 Micro Lens 15, 15A Transfer electrode wiring 16 Polycrystalline silicon film 17 Opening

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数の光電変換素子からなる光電変換素
子列および前記光電変換素子毎に複数の転送ゲート電極
を設けてなる垂直転送レジスタからなる画素列を複数並
列して集積した半導体チップを層間絶縁膜を介して被覆
し、前記光電変換素子の上部にそれぞれ開口を有する遮
光膜を有する固体撮像装置において、前記各画素列の対
応する転送ゲート電極を行方向に接続する転送電極配線
が前記転送ゲート電極と同一材質でより厚く形成されて
いることを特徴とする固体撮像装置。
1. A semiconductor chip having a plurality of photoelectric conversion element rows formed of a plurality of photoelectric conversion elements and a pixel row formed of a vertical transfer register provided with a plurality of transfer gate electrodes for each photoelectric conversion element arranged in parallel and integrated. In a solid-state imaging device having a light-shielding film that is covered with an insulating film and has an opening above each photoelectric conversion element, transfer electrode wirings that connect corresponding transfer gate electrodes of each pixel column in a row direction are transferred. A solid-state imaging device, which is made of the same material as the gate electrode and is thicker.
【請求項2】 半導体基板表面の所定領域にゲート絶縁
膜を形成し、前記ゲート絶縁膜を第1の導電性膜で被覆
しパターニングして第1の転送電極配線層を形成する工
程と、前記第1の導電性膜と同一材質の第2の導電性膜
を全面に堆積しパターニングすることにより、前記第1
の転送電極配線層に積層されてともに転送電極配線を構
成する第2の転送電極配線層および前記第2の転送電極
配線層から列方向に張り出した転送ゲート電極を形成す
る工程と、しかる後に層間絶縁膜を堆積し、所定領域に
開口を有する遮光膜を形成する工程とを有することを特
徴とする固体撮像装置の製造方法。
2. A step of forming a gate insulating film in a predetermined region of a surface of a semiconductor substrate, covering the gate insulating film with a first conductive film, and patterning to form a first transfer electrode wiring layer, By depositing and patterning a second conductive film of the same material as the first conductive film on the entire surface, the first conductive film is formed.
Forming the second transfer electrode wiring layer and the transfer gate electrode which are stacked on the transfer electrode wiring layer to form the transfer electrode wiring together and the transfer gate electrode projecting in the column direction from the second transfer electrode wiring layer; A step of depositing an insulating film and forming a light-shielding film having an opening in a predetermined region.
JP5133761A 1993-06-04 1993-06-04 Solid-state imaging device and manufacturing method thereof Expired - Lifetime JP2531435B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5133761A JP2531435B2 (en) 1993-06-04 1993-06-04 Solid-state imaging device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5133761A JP2531435B2 (en) 1993-06-04 1993-06-04 Solid-state imaging device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH06350065A true JPH06350065A (en) 1994-12-22
JP2531435B2 JP2531435B2 (en) 1996-09-04

Family

ID=15112340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5133761A Expired - Lifetime JP2531435B2 (en) 1993-06-04 1993-06-04 Solid-state imaging device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2531435B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS633457A (en) * 1986-06-24 1988-01-08 Nec Corp Solid-state image sensing device
JPS63141367A (en) * 1986-12-03 1988-06-13 Mitsubishi Electric Corp Solid-state image sensing device
JPS63127153U (en) * 1987-02-12 1988-08-19

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS633457A (en) * 1986-06-24 1988-01-08 Nec Corp Solid-state image sensing device
JPS63141367A (en) * 1986-12-03 1988-06-13 Mitsubishi Electric Corp Solid-state image sensing device
JPS63127153U (en) * 1987-02-12 1988-08-19

Also Published As

Publication number Publication date
JP2531435B2 (en) 1996-09-04

Similar Documents

Publication Publication Date Title
US7550813B2 (en) Photoelectric converting film stack type solid-state image pickup device, and method of producing the same
US7545423B2 (en) Image sensor having a passivation layer exposing at least a main pixel array region and methods of fabricating the same
KR20200091252A (en) Backside illuminated image sensor and method of manufacturing the same
JP4448087B2 (en) CMOS image sensor and manufacturing method thereof
JPH05167056A (en) Lamination-type solid-state image sensing device
KR940009601B1 (en) Manufacturing method of charge coupled device
JP2006032967A (en) Image sensor and manufacturing method of same
JP2531435B2 (en) Solid-state imaging device and manufacturing method thereof
JPH09172156A (en) Solid-state image pick-up device and its fabrication
JP2919697B2 (en) Method for manufacturing solid-state imaging device
JP2725636B2 (en) Solid-state imaging device and manufacturing method thereof
JP4090221B2 (en) Solid-state imaging device and manufacturing method thereof
JP7574054B2 (en) Manufacturing method of stacked image pickup device
JP3276906B2 (en) Solid-state imaging device and method of manufacturing solid-state imaging device
JPH05152551A (en) Manufacture of solid-state imaging device
JPH02166769A (en) Laminated solid state image sensor and manufacture thereof
JP2007012677A (en) Solid state image sensor and its fabrication process
JP3394878B2 (en) Method for manufacturing solid-state imaging device
JPH07114275B2 (en) Solid-state imaging device
JP2000124435A (en) Solid image pickup element and manufacture thereof
JPH0521780A (en) Solid image pick-up element
JP2003142676A (en) Solid-state imaging device and method of manufacturing the same
WO2011155182A1 (en) Solid-state imaging element
JPH04354161A (en) Solid-state image sensing element
JPH1126743A (en) Solid-state image sensing device and its manufacture

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19960507