JPH063455Y2 - Backup device for CPU built-in RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a backup device for a CPU built-in RAM, and is particularly suitable for suppressing the backup current and reducing the power consumption of the backup battery. C
The present invention relates to a backup device for a RAM with a built-in PU.

(Prior Art) In a system constructed by a microcomputer,
Even when the power of the system is turned off, it may be necessary to retain the stored contents of the RAM. In order to deal with such a case, the RAM is usually backed up by a battery and the RAM is backed up. I try not to rewrite the memory contents.

On the other hand, when constructing a system with a microcomputer, there has been a demand for using a CPU having a built-in ROM and RAM so that the area of a substrate on which components are mounted does not become large in order to miniaturize the system.

In a CPU having such a built-in ROM and RAM, it is necessary to supply backup power to the CPU in order to back up the RAM.

FIG. 4 shows an example of conventional technology in which the CPU is backed up by a battery. In the figure, a power supply terminal (Vcc terminal) of the CPU 1 is connected to a system power supply (not shown) having a voltage of 5V and backup batteries 2 and 3 having a voltage of 3V through diodes D2 and D1. . A crystal oscillator 4a is connected to the connection terminals XIN and XOUT of the oscillation circuit of the CPU 1.

In the above prior art, when the system power is turned off, C
A backup voltage is applied to the Vcc terminal of the PU1 by the batteries 2 and 3, and the RAM built in the CPU1.
The memory content of is retained without being rewritten.

(Problems to be Solved by the Invention) In the above-mentioned conventional technique, when a backup voltage is applied to the CPU 1, a clock signal corresponding to the frequency of the crystal unit 4a is taken into the CPU 1, and not only the RAM but also the CPU 1 is captured. However, as a result, a large amount of backup current flows and the life of the backup batteries 2 and 3 is extremely shortened.

In order to solve such a problem, there has been a method in which the operation of the CPU 1 is forcibly stopped by a "stop instruction" by software. However, since the clock signal itself is not stopped by this method, the operation of the CPU 1 may restart when electrostatic noise or the like is applied to the input terminal for resetting the stop instruction. Therefore, even with the method using the software, a large backup current flows, which is a problem in practical use.

Due to such a problem, in an actual system configuration, a RAM is provided outside the CPU, and when the power is turned off, the external RAM is backed up by a battery so that the contents stored in the RAM can be retained. (Non-volatile memory) was realized.

As described above, if the RAM is provided outside the CPU, the RAM can be backed up, but with respect to the demand for reducing the substrate area, there is still a problem that this cannot be satisfied.

Further, when a new backup battery is installed, a large amount of power is consumed until the system power is turned on due to an unstable state of the CPU internal circuit, which shortens the battery life.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a backup device for a RAM with a built-in CPU that can back up the RAM with a battery without consuming extra power. .

(Means and Actions for Solving the Problems) In order to solve the above problems and achieve the object, the present invention provides a CPU having a built-in RAM and a system power supply for supplying power to a system including the CPU. A backup battery, and the system power supply and the backup battery are respectively connected. When the system power supply is turned on, the system power supply supplies power to the CPU and the system power supply is cut off. If so, a power source switching means for supplying power from the backup battery to the CPU, a power monitor for giving a reset signal to the CPU when the system power source is cut off, and the backup battery power source is turned on. And an initial reset circuit that outputs a control signal of a predetermined time width and a clock signal And an oscillation circuit which controls the oscillation circuit when the system power is turned on or when a control signal of a predetermined time width is output from the initial reset circuit to the CPU. An oscillation circuit control means for giving a clock signal is provided, and when the backup battery is newly incorporated, the CPU uses the power from the backup battery to generate a reset signal for the power monitor and a clock signal for the oscillation circuit. It is characterized in that the reset operation of the internal circuit is performed based on.

In the present invention having the above configuration, when the system power is turned off, the backup power is supplied to the CPU, and the RAM built in the CPU is backed up. On the other hand, the power of the oscillation circuit is not supplied when the system power is turned off, so that the clock signal is not supplied to the CPU and the CPU does not operate.

In addition, when a new backup battery is installed, the CPU uses the power from the battery based on the reset signal of the power monitor and the clock signal of the oscillation circuit.
Resets the internal circuit.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of this embodiment. In the figure, CP
U1 has a built-in RAM (not shown). The CPU1
The backup batteries 2 and 3 and the system power supply are connected to the Vcc terminal of the battery via diodes D1 and D2, respectively. Power monitor 5 for the reset terminal
Are connected, and the system power supply is connected to the power monitor 5.

The power monitor 5 outputs a reset signal to the CPU 1 when the system power is turned on and when the system power is dropped.

The initial reset circuit 6 is composed of an inverter 6a, resistors 6b and 6C, and a capacitor 6d. The voltages of the batteries 2 and 3 are applied to the initial reset circuit 6, the output of the inverter 6a of the initial reset circuit 6 is input to the oscillation circuit 4, and the diode D
It becomes the power supply voltage applied to the inverter 4b via the inverter 4.

The oscillator circuit 4 includes a crystal oscillator 4a, an inverter 4b, a resistor 4c, capacitors 4d and 4e, and diodes D3 and D4. The oscillation circuit 4 outputs a clock signal to the CPU 1 according to the system power supply voltage or the output voltage from the initial reset circuit 6.

A Zener diode 7 is connected between the Vcc terminal and the Vss terminal of the CPU 1 to prevent latchup due to electrostatic noise or the like.

The present embodiment having the above configuration operates as follows. FIG. 2 is a timing chart of the operation of this embodiment.

As shown in the figure, when the batteries 2 and 3 are incorporated into the system after the system is completed, a voltage of 3 V is applied to the initial reset circuit 6, but the inverter 6
Since the output of a is delayed by the time τ determined by the time constant circuit composed of the resistors 6b and 6c and the capacitor 6d, the inverter 4b of the oscillation circuit 4 outputs a high (H) voltage until the delay time τ elapses. Is applied, the oscillation circuit 4
Output a clock signal to U1.

After the elapse of time τ, the output of the initial reset circuit 6, that is, the input of the inverter 4b of the oscillation circuit 4 changes to low (L), and the supply of the clock signal to the CPU 1 is stopped.

As described above, the initial reset circuit 6 is for outputting a clock signal from the oscillation circuit 4 to the CPU 1 when the batteries 2 and 3 are incorporated into the system until a predetermined time elapses. The reset operation of the CPU 1 is performed while the signal is being output.

If the reset operation of the CPU 1 is not performed, the port settings are indefinite, and much power is consumed after the batteries 2 and 3 are installed and before the system power is turned on, which may shorten the battery life. Therefore, after the battery is installed, the port is set to the input port by performing the reset operation, so that the CPU 1 and the external connection are in a high impedance state. As a result, the external circuit of the CPU 1 is substantially disconnected from the external circuit, current leakage does not occur, and useless power consumption is prevented.

In this embodiment, as described above, when the batteries 2 and 3 are assembled, the clock signal is forcibly output for a predetermined time, so that the reset operation of the CPU 1 is reliably performed.

Next, the operation when the system power is turned on and the system is operating will be described according to the timing chart shown in FIG.

While the system power is on, the voltage of 5V is the CPU
The clock signal that is applied to the Vcc terminal of 1, the power monitor 5, and the oscillation circuit 4 and is output from the oscillation circuit 4 is supplied to the CPU 1.

When the system power is turned off, the voltage of the system power is 5
Gradually descend from V. Then, when the voltage of the system power supply drops to 4V, the output of the power monitor 5 drops to 0V all at once, and the reset operation is started. The oscillation circuit 4 outputs a clock signal to the CPU 1 until the system power supply drops to about 0.7V. The reset operation of the CPU 1 is completed by the time the clock signal is no longer output.

When the system power is turned off, the voltages of the backup batteries 2 and 3 are applied to the Vcc terminal this time.
The voltage supplied to PU1 is 3V, which is the voltage of the batteries 2 and 3.
Maintained at.

On the other hand, when the system power is turned on again and the voltage of the power supply is 0.7
When the voltage exceeds V, the clock signal output from the oscillation circuit 4 is incorporated into the CPU 1, and after a predetermined time, the power monitor 5
Output becomes 5V and the reset is released.

As the system power supply voltage rises, the voltage supplied to the CPU 1 also returns to 5V.

As described above, in the present embodiment, the clock signal is supplied to the CPU 1 from the oscillation circuit 4 provided outside the CPU 1 and operated by the power supplied from the system power supply. Therefore, the clock signal is not supplied to the CPU 1 by the power supplied from the backup batteries 2 and 3 of the RAM as in the conventional technique, so that the supply of the clock signal is stopped when the system power is turned off. In this way, RA from the batteries 2 and 3
Only the current required to back up M is supplied to the CPU 1.

In this embodiment, an example in which the initial reset circuit is provided to ensure the reset operation when the battery is incorporated is shown. However, even if the initial reset circuit is not provided, the backup device has low power consumption. Can fulfill the function of.

That is, when the initial reset circuit is provided, the reset operation is performed immediately after the battery is assembled, so that the power consumption until the system power is turned on is reduced, and the life of the battery can be further extended.

(Effect of the Invention) As is apparent from the above description, according to the present invention, when the system power is cut off, the supply of the clock signal to the CPU is stopped to stop the operation of the CPU. Moreover, since the backup battery is used only for the backup of the RAM, the battery consumption is moderated, and a sufficiently practical backup device for the RAM with built-in CPU can be realized.

Also, when installing a new backup battery,
Based on the reset signal of the power monitor and the clock signal of the oscillation circuit, the CP from the power from the battery
Since the reset operation of the U internal circuit is performed, it is possible to prevent the battery life from being shortened due to the unstable state of the CPU internal circuit, which consumes much power until the system power is turned on.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIGS. 2 and 3 are timing charts showing operation timing of the embodiment,
FIG. 4 is a circuit diagram of the prior art. 1 ... CPU, 2, 3 ... Battery, 4 ... Oscillation circuit, 5 ... Power monitor, 6 ... Initial reset circuit

Claims (1)

[Scope of utility model registration request] 1. A CPU having a built-in RAM, a system power source for supplying power to a system including the CPU, a backup battery, and the system power source and the backup battery respectively connected to the system power source. Power is supplied from the system power supply to the CPU when the system power is shut off, and power is switched off when the system power is shut off from the backup battery to the CPU, and the system power is shut off. A power monitor that gives a reset signal to the CPU when it is turned on, an initial reset circuit that outputs a control signal of a predetermined time width when the backup battery power is turned on, and a clock signal that is given to the CPU The oscillator circuit and the system power supply that controls this oscillator circuit And an oscillator circuit control means for giving a clock signal to the CPU when the control signal of a predetermined time width is output from the initial reset circuit. A backup device for a RAM with a built-in CPU, which performs a reset operation of an internal circuit based on a reset signal of the power monitor and a clock signal of the oscillation circuit by electric power from the backup battery when incorporated.