JPH02108125U - - Google Patents
Info
- Publication number
- JPH02108125U JPH02108125U JP1648289U JP1648289U JPH02108125U JP H02108125 U JPH02108125 U JP H02108125U JP 1648289 U JP1648289 U JP 1648289U JP 1648289 U JP1648289 U JP 1648289U JP H02108125 U JPH02108125 U JP H02108125U
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- circuit
- time constant
- battery
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Power Sources (AREA)
Description
第１図は本考案の一実施例の回路図、第２図、
第３図は該実施例の動作タイミングを示すタイミ
ングチヤート、第４図は従来技術の回路図である
。
１…ＣＰＵ、２，３…バツテリ、４…発振回路
、５…パワーモニタ、６…イニシヤルリセツト回
路。
Figure 1 is a circuit diagram of an embodiment of the present invention; Figure 2 is a circuit diagram of an embodiment of the present invention;
FIG. 3 is a timing chart showing the operation timing of this embodiment, and FIG. 4 is a circuit diagram of the prior art. 1... CPU, 2, 3... battery, 4... oscillation circuit, 5... power monitor, 6... initial reset circuit.
Claims (1)
ツプ用のバツテリと、ＣＰＵにクロツク信号を供
給するため、該ＣＰＵの外部に設けられ、システ
ム電源から供給される電力で動作する発振回路と
を具備したことを特徴とするＣＰＵ内蔵ＲＡＭの
バツクアツプ装置。 (2) 時定数回路と、該時定数回路の出力を反転
させるインバータとを具備すると共に、該時定数
回路の入力側に前記バツテリを接続し、さらに前
記インバータの出力側を前記発振回路に接続した
イニシヤルリセツト回路を具備したことを特徴と
する請求項１記載のＣＰＵ内蔵ＲＡＭのバツクア
ツプ装置。[Scope of Claim for Utility Model Registration] (1) A backup battery connected to the Vcc terminal of the CPU, and a battery provided outside the CPU for supplying clock signals to the CPU, and powered by power supplied from the system power supply. A backup device for a RAM built into a CPU, characterized in that it is equipped with an oscillation circuit that operates. (2) comprising a time constant circuit and an inverter that inverts the output of the time constant circuit; the battery is connected to the input side of the time constant circuit; and the output side of the inverter is connected to the oscillation circuit; 2. The CPU built-in RAM backup device according to claim 1, further comprising an initial reset circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989016482U JPH063455Y2 (en) | 1989-02-15 | 1989-02-15 | Backup device for CPU built-in RAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989016482U JPH063455Y2 (en) | 1989-02-15 | 1989-02-15 | Backup device for CPU built-in RAM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02108125U true JPH02108125U (en) | 1990-08-28 |
| JPH063455Y2 JPH063455Y2 (en) | 1994-01-26 |
Family
ID=31229458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989016482U Expired - Lifetime JPH063455Y2 (en) | 1989-02-15 | 1989-02-15 | Backup device for CPU built-in RAM |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH063455Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63175909A (en) * | 1987-01-16 | 1988-07-20 | Nec Corp | One-chip microcomputer |
| JPS6461810A (en) * | 1987-09-01 | 1989-03-08 | Canon Kk | Power unit |
-
1989
- 1989-02-15 JP JP1989016482U patent/JPH063455Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63175909A (en) * | 1987-01-16 | 1988-07-20 | Nec Corp | One-chip microcomputer |
| JPS6461810A (en) * | 1987-09-01 | 1989-03-08 | Canon Kk | Power unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH063455Y2 (en) | 1994-01-26 |
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