JPS62129635U - - Google Patents
Info
- Publication number
- JPS62129635U JPS62129635U JP1844186U JP1844186U JPS62129635U JP S62129635 U JPS62129635 U JP S62129635U JP 1844186 U JP1844186 U JP 1844186U JP 1844186 U JP1844186 U JP 1844186U JP S62129635 U JPS62129635 U JP S62129635U
- Authority
- JP
- Japan
- Prior art keywords
- time
- computer
- memory
- clock signal
- signal sent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims 2
- 230000004397 blinking Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Digital Computer Display Output (AREA)
Description
第１図はこの考案の一実施例を示す図、第２図
はこの考案の要部接続図であり、１はデイスプレ
イ部、２はキーボード、３は電源入、切スイツチ
、４は経過時間表示器、５は時間設定器、６はパ
ルス発生器、７は計算機、９はメモリ、１０は減
算回路、１１はフリツカ信号発生器、１２はＡＮ
Ｄ回路である。なお、図中同一あるいは相当部分
には同一符号を付して示してある。
Figure 1 is a diagram showing an embodiment of this invention, and Figure 2 is a connection diagram of the main parts of this invention, where 1 is a display section, 2 is a keyboard, 3 is a power on/off switch, and 4 is an elapsed time display. 5 is a time setting device, 6 is a pulse generator, 7 is a calculator, 9 is a memory, 10 is a subtraction circuit, 11 is a flicker signal generator, 12 is an AN
This is the D circuit. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.
Claims (1)
計算機につながる周辺・端末装置において、電源
スイツチを「入」にした時の計算機から送られる
時計信号による時刻を記憶するメモリと、電源ス
イツチを「入」にしたあとの経過時間を計算機か
ら送られる時計信号による現在時刻から上記メモ
リに記憶してある使用開始時の時刻を差引くこと
によつて求める減算回路と、上記減算回路の出力
である経過時間を表示せしめる時間表示器と、前
記経過時間が予め設定してある時間と等しくなつ
た時時間表示器を点滅させる手段とを備えたこと
を特徴とする周辺・端末装置。 A peripheral/terminal device that is equipped with a display unit and a keyboard and is connected to the main computer has a memory that stores the time based on the clock signal sent from the computer when the power switch is turned on, and a memory that stores the time based on the clock signal sent from the computer when the power switch is turned on. A subtraction circuit calculates the elapsed time by subtracting the time at the start of use stored in the memory from the current time according to the clock signal sent from the computer, and the elapsed time is the output of the subtraction circuit. A peripheral/terminal device comprising: a time display; and means for blinking the time display when the elapsed time becomes equal to a preset time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1844186U JPS62129635U (en) | 1986-02-12 | 1986-02-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1844186U JPS62129635U (en) | 1986-02-12 | 1986-02-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62129635U true JPS62129635U (en) | 1987-08-17 |
Family
ID=30812116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1844186U Pending JPS62129635U (en) | 1986-02-12 | 1986-02-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62129635U (en) |
-
1986
- 1986-02-12 JP JP1844186U patent/JPS62129635U/ja active Pending